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1. 发明申请

US20070101332A1 METHOD AND APPARATUS FOR RESOURCE-BASED THREAD ALLOCATION IN A MULTIPROCESSOR COMPUTER SYSTEM 审中-公开
标题翻译：在多处理器计算机系统中基于资源的线程分配的方法和装置
公开(公告)号：US20070101332A1
公开(公告)日：2007-05-03
申请号：US11163746
申请日：2005-10-28
申请人： Adam Courchesne , Francis Kampf , Gregory Mann , Jason Norman , Stanley Stanski
发明人： Adam Courchesne , Francis Kampf , Gregory Mann , Jason Norman , Stanley Stanski
IPC分类号： G06F9/46
CPC分类号： G06F9/5011 , G06F2209/507 , G06F2209/508
摘要： Thread entries are stored in a memory of the system to indicate executed instruction threads. Uses of processing resources by the respective instruction threads are detected and history entries for the threads are stored in a memory of the system. Such history entries indicate whether respective processing resources have been used by respective ones of the instruction threads. The history entries of first and second ones of the instruction threads are compared. The second instruction thread is selected for executing if the comparing indicates history of processing resources used by the first thread has a certain difference relative to history of processing resources used by the second thread.
摘要翻译：线程条目存储在系统的存储器中以指示执行的指令线程。检测各个指令线程使用的处理资源，并将线程的历史条目存储在系统的存储器中。这些历史条目表示相应的指令线程是否已经使用相应的处理资源。比较第一和第二条指令线程的历史条目。如果比较指示由第一线程使用的处理资源的历史与第二线程使用的处理资源的历史有一定差异，则选择第二指令线程来执行。

2. 发明申请

US20060242524A1 SYSTEM AND METHOD FOR SYSTEM-ON-CHIP INTERCONNECT VERIFICATION 失效
标题翻译：系统与片上互连验证的系统和方法
公开(公告)号：US20060242524A1
公开(公告)日：2006-10-26
申请号：US10906388
申请日：2005-02-17
申请人： Serafino Bueti , Adam Courchesne , Kenneth Goodnow , Gregory Mann , Jason Norman , Stanley Stanski , Scott Vento
发明人： Serafino Bueti , Adam Courchesne , Kenneth Goodnow , Gregory Mann , Jason Norman , Stanley Stanski , Scott Vento
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G06F11/261 , G01R31/31717 , G01R31/318513 , G06F11/2236 , G06F17/5022
摘要： A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.
摘要翻译：一种用于验证片上系统互连的系统和方法包括：第一线性反馈移位寄存器，其耦合到第一片上系统分量的输出接口;第二线性反馈移位寄存器，其在第二片上系统组件以及耦合到第二线性反馈移位寄存器和第二片上系统的输入接口的比较器。另一种验证方法包括使用第一线性反馈移位寄存器和第二线性反馈移位寄存器使用相同的第一初始状态来产生伪随机数序列，并且将第一线性反馈移位寄存器的输出与第二线性反馈移位寄存器的输出进行比较线性反馈移位寄存器和报告错误比较。

3. 发明申请

US20060095905A1 METHOD AND APPARATUS FOR SERVICING THREADS WITHIN A MULTI-PROCESSOR SYSTEM 审中-公开
标题翻译：用于在多处理器系统中维护螺纹的方法和装置
公开(公告)号：US20060095905A1
公开(公告)日：2006-05-04
申请号：US10904259
申请日：2004-11-01
申请人： Adam Courchesne , Kenneth Goodnow , Gregory Mann , Jason Norman , Stanley Stanski , Scott Vento
发明人： Adam Courchesne , Kenneth Goodnow , Gregory Mann , Jason Norman , Stanley Stanski , Scott Vento
IPC分类号： G06F9/46
CPC分类号： G06F9/485
摘要： A method for servicing threads within a multi-processor system is disclosed. In response to an input/output (I/O) request to a peripheral by a thread, a latency time is assigned to the thread such that the thread will not be interrogated until the latency time has lapsed. After the latency time is lapsed, a determination is made as to whether or not the I/O request has been responded. If the I/O request has not been responded after the latency time is lapsed, the latency time is assigned to the thread again. Otherwise, if the I/O request has been responded after the latency time is lapsed, the latency time is updated with an actual response time. The actual response time is from a time when the I/O request was made to a time when the I/O request was actually responded.
摘要翻译：公开了一种用于在多处理器系统内维护线程的方法。响应于线程对外设的输入/输出（I / O）请求，延迟时间被分配给线程，使得在延迟时间过去之前线程将不被询问。在延迟时间过去之后，确定I / O请求是否已被响应。如果延迟时间过后I / O请求未被响应，则延迟时间将再次分配给该线程。否则，如果在延迟时间过后已经响应了I / O请求，则延迟时间将以实际响应时间更新。实际的响应时间是从I / O请求到实际响应I / O请求时的时间。

4. 发明申请

US20070006108A1 APPARATUS AND METHOD FOR IMPLEMENTING AN INTEGRATED CIRCUIT IP CORE LIBRARY ARCHITECTURE 有权
标题翻译：实现一体化电路IP核心图书馆架构的装置和方法
公开(公告)号：US20070006108A1
公开(公告)日：2007-01-04
申请号：US11160609
申请日：2005-06-30
申请人： Serafino Bueti , Adam Courchesne , Kenneth Goodnow , Gregory Mann , Stanley Stanski
发明人： Serafino Bueti , Adam Courchesne , Kenneth Goodnow , Gregory Mann , Stanley Stanski
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： An integrated circuit (IC) architecture includes a library of intellectual property (IP) cores configured to provide a plurality of individual circuit functions. The IP cores arranged in a manner compatible with a customized, functional selection of individual ones of the IP cores, wherein individually selected cores are accessible through a communication structure included within the library.
摘要翻译：集成电路（IC）架构包括被配置为提供多个单独电路功能的知识产权（IP）核心库。所述IP核以与所述IP核中的各个IP核的定制功能选择相兼容的方式布置，其中通过包括在所述库内的通信结构来访问单独选择的核。

5. 发明申请

US20060038444A1 COMMUNICATION SYSTEMS AND METHODS USING MICROELECTRONICS POWER DISTRIBUTION NETWORK 失效
标题翻译：通信系统和使用微电子功率分配网络的方法
公开(公告)号：US20060038444A1
公开(公告)日：2006-02-23
申请号：US10711082
申请日：2004-08-20
申请人： Serafino Bueti , Adam Courchesne , Kai Feng , Kenneth Goodnow , Gregory Mann , Scott Vento
发明人： Serafino Bueti , Adam Courchesne , Kai Feng , Kenneth Goodnow , Gregory Mann , Scott Vento
IPC分类号： H04B3/54 , G05B11/01
CPC分类号： H04B3/54 , H04B2203/5416
摘要： A communication system, which includes a microelectronics chip including a power distribution network; a transmitter operatively configured to generate a communication signal and provide the communication signal to the power distribution network; and a receiver operatively configured to receive the communication signal from the power distribution network. A method is also provided for transmitting a communication signal via a power distribution network of a microelectronics chip.
摘要翻译：一种通信系统，其包括具有配电网络的微电子芯片; 发射机，可操作地配置为产生通信信号并将所述通信信号提供给所述配电网络; 以及可操作地配置为从所述配电网接收所述通信信号的接收器。还提供了一种通过微电子芯片的配电网传送通信信号的方法。

6. 发明申请

US20060041705A1 SYSTEM AND METHOD FOR ARBITRATION BETWEEN SHARED PERIPHERAL CORE DEVICES IN SYSTEM ON CHIP ARCHITECTURES 审中-公开
标题翻译：芯片结构体系中共享外围核心器件之间的仲裁系统和方法
公开(公告)号：US20060041705A1
公开(公告)日：2006-02-23
申请号：US10711084
申请日：2004-08-20
申请人： Serafino Bueti , Kenneth Goodnow , Gregory Mann , Jason Norman , Scott Vento
发明人： Serafino Bueti , Kenneth Goodnow , Gregory Mann , Jason Norman , Scott Vento
IPC分类号： G06F13/36
CPC分类号： G06F13/4031 , G06F2213/0038
摘要： A system for implementing arbitration between one or more shared peripheral core devices in system on chip (SOC) integrated circuit architecture includes a first microprocessor in communication with a first system bus, and a second microprocessor in communication with a second system bus. At least one peripheral core device is accessible by both the first microprocessor and said second microprocessor, and an arbitration unit is in communication with the first system bus and the second system bus. The arbitration unit is configured to control communication between the at least one peripheral core device and the first and second microprocessors.
摘要翻译：一种用于在系统级芯片（SOC）集成电路架构中的一个或多个共享外围核心装置之间实现仲裁的系统包括与第一系统总线通信的第一微处理器和与第二系统总线通信的第二微处理器。至少一个外围核心设备可由第一微处理器和所述第二微处理器访问，并且仲裁单元与第一系统总线和第二系统总线通信。仲裁单元被配置为控制至少一个外围核心设备与第一和第二微处理器之间的通信。

7. 发明申请

US20070245290A1 METHOD OF MANUFACTURING INTEGRATED CIRCUITS USING PRE-MADE AND PRE-QUALIFIED EXPOSURE MASKS FOR SELECTED BLOCKS OF CIRCUITRY 失效
标题翻译：使用预先制作的集成电路的方法和用于选择的电路块的预先准许的接触掩模
公开(公告)号：US20070245290A1
公开(公告)日：2007-10-18
申请号：US11279666
申请日：2006-04-13
申请人： Serafino Bueti , Kenneth Goodnow , Gregory Mann , Jason Norman
发明人： Serafino Bueti , Kenneth Goodnow , Gregory Mann , Jason Norman
IPC分类号： G06F17/50 , G03F1/00
CPC分类号： G03F1/84
摘要： Disclosed are embodiments of a manufacturing method that establishes a library of pre-made and pre-qualified masks for patterning different blocks of circuitry that meet established performance and timing requirements. The embodiments of the method use stepped exposures of multiple masks, including at least one mask selected from this library, to pattern a chip design onto a silicon wafer, where the chip design is made up of two or more interconnected blocks of circuitry. Consequently, for a given integrated circuit design, pre-made/pre-qualified mask(s) can be selected from the library to pattern one, some or all blocks of circuitry for the design. Optionally, additional masks can be specially made and qualified to pattern other block(s) of circuitry (e.g., application specific logic) within the design. The blocks of circuitry patterned in this manner can be electrically connected via generic or customized interfaces in order to complete the chip design.
摘要翻译：公开了一种制造方法的实施例，其建立用于图案化满足已确定的性能和时序要求的不同电路块的预制和预先限定的掩模库。该方法的实施例使用多个掩模的步进曝光，包括从该库选择的至少一个掩模，以将芯片设计图案化到硅晶片上，其中芯片设计由两个或更多个互连的电路块组成。因此，对于给定的集成电路设计，可以从库中选择预制/预先限定的掩模，以对设计的一个，一些或所有电路块进行图案化。可选地，附加掩模可以被特别地制造并且被限定以在设计中对其他电路块（例如，应用专用逻辑）进行图案化。以这种方式图案化的电路块可通过通用或定制界面电连接，以完成芯片设计。

8. 发明申请

US20050268209A1 CYCLIC REDUNDANCY CHECK GENERATION CIRCUIT 有权
标题翻译：循环冗余检查生成电路
公开(公告)号：US20050268209A1
公开(公告)日：2005-12-01
申请号：US10709794
申请日：2004-05-28
申请人： Gregory Mann
发明人： Gregory Mann
IPC分类号： H03M13/00 , H03M13/09
CPC分类号： H03M13/091 , H03M13/6572
摘要： A circuit, a method, and a method of designing the circuit, the circuit including: multiple W-bit packet data slice latches; a data partition comprising multiple data XOR subtree levels and having data latches between the data XOR subtree levels; a remainder partition comprising multiple remainder XOR subtree levels and having remainder latches between the remainder XOR subtree levels; a combinatorial XOR tree, outputs of the remainder partition and outputs of the data partition connected to inputs of the combinatorial XOR tree; and a remainder latch, combinatorial XOR tree connected to the remainder latch and the outputs of the remainder latch connected to the remainder partition.
摘要翻译：一种设计电路的电路，方法和方法，所述电路包括：多个W位分组数据片锁存器; 数据分区，包括多个数据XOR子树级别，并且在数据XOR子树级之间具有数据锁存器; 剩余分区包括多个余数XOR子树级别，并且在余数XOR子树级别之间具有余数锁存器; 组合XOR树，连续到组合XOR树的输入的数据分区的剩余分区和输出的输出; 以及连接到剩余锁存器的剩余锁存组合XOR树，并且剩余锁存器的输出连接到其余分区。

9. 发明申请

US20050090738A1 Disposable single-use external dosimeters for detecting radiation in fluoroscopy and other medical procedures/therapies 有权
标题翻译：一次性一次性外用剂量计，用于检测荧光透视和其他医疗程序/治疗中的辐射
公开(公告)号：US20050090738A1
公开(公告)日：2005-04-28
申请号：US10865430
申请日：2004-06-10
申请人： Robert Black , Steven Widener , John Carroll , Gregory Mann , Phillip Lehman
发明人： Robert Black , Steven Widener , John Carroll , Gregory Mann , Phillip Lehman
IPC分类号： G01T1/00 , A61N5/10 , G01T1/02 , G01T1/161 , A61B6/00
CPC分类号： G01T1/026 , A61N5/1048 , A61N5/1071 , A61N2005/1072
摘要： Methods, systems, devices, and computer program products include positioning single-use radiation sensor patches that have adhesive onto the skin of a patient to evaluate the radiation dose delivered during a medical procedure or treatment session. The sensor patches are configured to be relatively unobtrusive and operate during radiation without the use of externally extending power cords or lead wires.
摘要翻译：方法，系统，设备和计算机程序产品包括将具有粘合剂的单次使用的辐射传感器贴片定位在患者的皮肤上，以评估在医疗过程或治疗期间递送的辐射剂量。传感器贴片被配置为相对不引人注意并且在辐射期间操作，而不使用外部延伸的电源线或引线。

10. 发明申请

US20050172205A1 Multilevel parallel CRC generation and checking circuit 失效
标题翻译：多级并行CRC生成和检查电路
公开(公告)号：US20050172205A1
公开(公告)日：2005-08-04
申请号：US10771823
申请日：2004-02-03
申请人： Ming-i Lin , Brian Connolly , Todd Leonard , Gregory Mann , Jonathan Raymond
发明人： Ming-i Lin , Brian Connolly , Todd Leonard , Gregory Mann , Jonathan Raymond
IPC分类号： G06K5/04 , G11B5/00 , G11B20/20 , H03M13/00 , H03M13/09
CPC分类号： H03M13/091
摘要： A CRC generator/checker for generating CRC results, comprising: a set of CRC circuits connected in series, each CRC circuit responsive to a different control signal generated by a control logic, each CRC circuit having a seed input adapted to receive a seed, a data input adapted to receive and process a different set of M-bits of a data unit and a result output adapted to generate a result, the result output of a previous CRC circuit connected to the seed input of an immediately subsequent CRC circuit, the seed input of a first CRC circuit connected to an output of a remainder register, an input of the remainder register connected to an output of a multiplexer, the result outputs of the multiplicity of CRC circuits connected to different inputs of the multiplexer, the multiplexer responsive to a select signal generated by the control logic.
摘要翻译：一种用于生成CRC结果的CRC发生器/检验器，包括：串联连接的一组CRC电路，每个CRC电路响应于由控制逻辑产生的不同控制信号，每个CRC电路具有适于接收种子的种子输入，数据输入，适于接收和处理数据单元的不同的M位组，以及适于产生结果的结果输出，连接到紧接着的CRC电路的种子输入的先前CRC电路的结果输出，种子连接到余数寄存器的输出的第一CRC电路的输入，连接到多路复用器的输出的剩余寄存器的输入，结果连接到多路复用器的不同输入的多个CRC电路的输出，多路复用器响应于由控制逻辑产生的选择信号。

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