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1. 发明申请

US20060041705A1 SYSTEM AND METHOD FOR ARBITRATION BETWEEN SHARED PERIPHERAL CORE DEVICES IN SYSTEM ON CHIP ARCHITECTURES 审中-公开
标题翻译：芯片结构体系中共享外围核心器件之间的仲裁系统和方法
公开(公告)号：US20060041705A1
公开(公告)日：2006-02-23
申请号：US10711084
申请日：2004-08-20
申请人： Serafino Bueti , Kenneth Goodnow , Gregory Mann , Jason Norman , Scott Vento
发明人： Serafino Bueti , Kenneth Goodnow , Gregory Mann , Jason Norman , Scott Vento
IPC分类号： G06F13/36
CPC分类号： G06F13/4031 , G06F2213/0038
摘要： A system for implementing arbitration between one or more shared peripheral core devices in system on chip (SOC) integrated circuit architecture includes a first microprocessor in communication with a first system bus, and a second microprocessor in communication with a second system bus. At least one peripheral core device is accessible by both the first microprocessor and said second microprocessor, and an arbitration unit is in communication with the first system bus and the second system bus. The arbitration unit is configured to control communication between the at least one peripheral core device and the first and second microprocessors.
摘要翻译：一种用于在系统级芯片（SOC）集成电路架构中的一个或多个共享外围核心装置之间实现仲裁的系统包括与第一系统总线通信的第一微处理器和与第二系统总线通信的第二微处理器。至少一个外围核心设备可由第一微处理器和所述第二微处理器访问，并且仲裁单元与第一系统总线和第二系统总线通信。仲裁单元被配置为控制至少一个外围核心设备与第一和第二微处理器之间的通信。

2. 发明申请

US20060242524A1 SYSTEM AND METHOD FOR SYSTEM-ON-CHIP INTERCONNECT VERIFICATION 失效
标题翻译：系统与片上互连验证的系统和方法
公开(公告)号：US20060242524A1
公开(公告)日：2006-10-26
申请号：US10906388
申请日：2005-02-17
申请人： Serafino Bueti , Adam Courchesne , Kenneth Goodnow , Gregory Mann , Jason Norman , Stanley Stanski , Scott Vento
发明人： Serafino Bueti , Adam Courchesne , Kenneth Goodnow , Gregory Mann , Jason Norman , Stanley Stanski , Scott Vento
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G06F11/261 , G01R31/31717 , G01R31/318513 , G06F11/2236 , G06F17/5022
摘要： A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.
摘要翻译：一种用于验证片上系统互连的系统和方法包括：第一线性反馈移位寄存器，其耦合到第一片上系统分量的输出接口;第二线性反馈移位寄存器，其在第二片上系统组件以及耦合到第二线性反馈移位寄存器和第二片上系统的输入接口的比较器。另一种验证方法包括使用第一线性反馈移位寄存器和第二线性反馈移位寄存器使用相同的第一初始状态来产生伪随机数序列，并且将第一线性反馈移位寄存器的输出与第二线性反馈移位寄存器的输出进行比较线性反馈移位寄存器和报告错误比较。

3. 发明申请

US20060038444A1 COMMUNICATION SYSTEMS AND METHODS USING MICROELECTRONICS POWER DISTRIBUTION NETWORK 失效
标题翻译：通信系统和使用微电子功率分配网络的方法
公开(公告)号：US20060038444A1
公开(公告)日：2006-02-23
申请号：US10711082
申请日：2004-08-20
申请人： Serafino Bueti , Adam Courchesne , Kai Feng , Kenneth Goodnow , Gregory Mann , Scott Vento
发明人： Serafino Bueti , Adam Courchesne , Kai Feng , Kenneth Goodnow , Gregory Mann , Scott Vento
IPC分类号： H04B3/54 , G05B11/01
CPC分类号： H04B3/54 , H04B2203/5416
摘要： A communication system, which includes a microelectronics chip including a power distribution network; a transmitter operatively configured to generate a communication signal and provide the communication signal to the power distribution network; and a receiver operatively configured to receive the communication signal from the power distribution network. A method is also provided for transmitting a communication signal via a power distribution network of a microelectronics chip.
摘要翻译：一种通信系统，其包括具有配电网络的微电子芯片; 发射机，可操作地配置为产生通信信号并将所述通信信号提供给所述配电网络; 以及可操作地配置为从所述配电网接收所述通信信号的接收器。还提供了一种通过微电子芯片的配电网传送通信信号的方法。

4. 发明申请

US20070005290A1 METHOD AND APPARATUS FOR MONITORING INTEGRATED CIRCUIT TEMPERATURE THROUGH DETERMINISTIC PATH DELAYS 失效
标题翻译：通过确定性延迟监测集成电路温度的方法和装置
公开(公告)号：US20070005290A1
公开(公告)日：2007-01-04
申请号：US11160601
申请日：2005-06-30
申请人： Serafino Bueti , Adam Courchesne , Kenneth Goodnow , Jason Norman , Stanley Stanski , Scott Vento
发明人： Serafino Bueti , Adam Courchesne , Kenneth Goodnow , Jason Norman , Stanley Stanski , Scott Vento
IPC分类号： G01K1/00
CPC分类号： G01K3/14 , G01K3/10
摘要： An apparatus for monitoring the temperature of an integrated circuit device includes a conductive wiring pattern formed on the integrated circuit device, extending into areas of the device to be monitored. A deterministic signal source is configured to generate a deterministic signal along the conductive wiring pattern, with one or more return paths tapped from selected locations along the pattern. A temperature change determination circuit is coupled to the one or more return paths and to a reference signal taken from the deterministic signal source. The circuit is configured to determine a delay between the reference signal and a delay signal traveling through at least a portion of the wiring pattern and a corresponding one of the return paths.
摘要翻译：用于监测集成电路器件的温度的装置包括形成在集成电路器件上的导电布线图形，延伸到待监视器件的区域中。确定性信号源被配置为沿着导电布线图形生成确定性信号，其中从沿着图案的选定位置抽头的一个或多个返回路径。温度变化确定电路耦合到一个或多个返回路径以及从确定性信号源获取的参考信号。该电路被配置为确定参考信号和穿过布线图案的至少一部分和相应的一个返回路径的延迟信号之间的延迟。

5. 发明申请

US20070245290A1 METHOD OF MANUFACTURING INTEGRATED CIRCUITS USING PRE-MADE AND PRE-QUALIFIED EXPOSURE MASKS FOR SELECTED BLOCKS OF CIRCUITRY 失效
标题翻译：使用预先制作的集成电路的方法和用于选择的电路块的预先准许的接触掩模
公开(公告)号：US20070245290A1
公开(公告)日：2007-10-18
申请号：US11279666
申请日：2006-04-13
申请人： Serafino Bueti , Kenneth Goodnow , Gregory Mann , Jason Norman
发明人： Serafino Bueti , Kenneth Goodnow , Gregory Mann , Jason Norman
IPC分类号： G06F17/50 , G03F1/00
CPC分类号： G03F1/84
摘要： Disclosed are embodiments of a manufacturing method that establishes a library of pre-made and pre-qualified masks for patterning different blocks of circuitry that meet established performance and timing requirements. The embodiments of the method use stepped exposures of multiple masks, including at least one mask selected from this library, to pattern a chip design onto a silicon wafer, where the chip design is made up of two or more interconnected blocks of circuitry. Consequently, for a given integrated circuit design, pre-made/pre-qualified mask(s) can be selected from the library to pattern one, some or all blocks of circuitry for the design. Optionally, additional masks can be specially made and qualified to pattern other block(s) of circuitry (e.g., application specific logic) within the design. The blocks of circuitry patterned in this manner can be electrically connected via generic or customized interfaces in order to complete the chip design.
摘要翻译：公开了一种制造方法的实施例，其建立用于图案化满足已确定的性能和时序要求的不同电路块的预制和预先限定的掩模库。该方法的实施例使用多个掩模的步进曝光，包括从该库选择的至少一个掩模，以将芯片设计图案化到硅晶片上，其中芯片设计由两个或更多个互连的电路块组成。因此，对于给定的集成电路设计，可以从库中选择预制/预先限定的掩模，以对设计的一个，一些或所有电路块进行图案化。可选地，附加掩模可以被特别地制造并且被限定以在设计中对其他电路块（例如，应用专用逻辑）进行图案化。以这种方式图案化的电路块可通过通用或定制界面电连接，以完成芯片设计。

6. 发明申请

US20070006108A1 APPARATUS AND METHOD FOR IMPLEMENTING AN INTEGRATED CIRCUIT IP CORE LIBRARY ARCHITECTURE 有权
标题翻译：实现一体化电路IP核心图书馆架构的装置和方法
公开(公告)号：US20070006108A1
公开(公告)日：2007-01-04
申请号：US11160609
申请日：2005-06-30
申请人： Serafino Bueti , Adam Courchesne , Kenneth Goodnow , Gregory Mann , Stanley Stanski
发明人： Serafino Bueti , Adam Courchesne , Kenneth Goodnow , Gregory Mann , Stanley Stanski
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： An integrated circuit (IC) architecture includes a library of intellectual property (IP) cores configured to provide a plurality of individual circuit functions. The IP cores arranged in a manner compatible with a customized, functional selection of individual ones of the IP cores, wherein individually selected cores are accessible through a communication structure included within the library.
摘要翻译：集成电路（IC）架构包括被配置为提供多个单独电路功能的知识产权（IP）核心库。所述IP核以与所述IP核中的各个IP核的定制功能选择相兼容的方式布置，其中通过包括在所述库内的通信结构来访问单独选择的核。

7. 发明授权

US08347019B2 Structure for hardware assisted bus state transition circuit using content addressable memories 失效
标题翻译：使用内容可寻址存储器的硬件辅助总线状态转换电路的结构
公开(公告)号：US08347019B2
公开(公告)日：2013-01-01
申请号：US12122321
申请日：2008-05-16
申请人： Serafino Bueti , Kenneth Joseph Goodnow , Todd Edwin Leonard , Gregory John Mann , Jason Michael Norman , Clarence Rosser Ogilvie , Peter Anthony Sandon , Charles S. Woodruff
发明人： Serafino Bueti , Kenneth Joseph Goodnow , Todd Edwin Leonard , Gregory John Mann , Jason Michael Norman , Clarence Rosser Ogilvie , Peter Anthony Sandon , Charles S. Woodruff
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F13/4059
摘要： A design structure including universal peripheral processor architecture on an integrated circuit (IC) includes a first data bus and a second data bus communicating with first and second ternary content addressable memory (TCAM) devices configured as state machines. First and second processors are coupled to the first bus interface logic and the second bus interface logic. First and second data storage devices communicate with the first and second processors and are coupled to the first and second data buses and communicate with each other. The TCAM devices are configured as state machines and are coupled to and adapted to interface with the processors, the data storage devices, and the bus interface logic using predefined protocols.
摘要翻译：包括集成电路（IC）上的通用外围处理器架构的设计结构包括与配置为状态机的第一和第二三进制内容可寻址存储器（TCAM）设备通信的第一数据总线和第二数据总线。第一和第二处理器耦合到第一总线接口逻辑和第二总线接口逻辑。第一和第二数据存储设备与第一和第二处理器进行通信，并且耦合到第一和第二数据总线并彼此通信。 TCAM设备被配置为状态机，并且使用预定义的协议耦合到并适于与处理器，数据存储设备和总线接口逻辑的接口。

8. 发明申请

US20090094566A1 DESIGN STRUCTURE FOR CHIP IDENTIFICATION SYSTEM 审中-公开
标题翻译：芯片识别系统设计结构
公开(公告)号：US20090094566A1
公开(公告)日：2009-04-09
申请号：US12105883
申请日：2008-04-18
申请人： Serafino Bueti , Adam J. Courchesne , Kenneth J. Goodnow , Todd E. Leonard , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
发明人： Serafino Bueti , Adam J. Courchesne , Kenneth J. Goodnow , Todd E. Leonard , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
IPC分类号： G06F17/50
CPC分类号： G06K19/067
摘要： Disclosed is a design structure for an on-chip identification circuitry. In one embodiment, pairs of conductors (e.g., metal pads, vias, lines) are formed within one or more metallization layers. The distance between the conductors in each pair is predetermined so that, given known across chip line variations, there is a random chance (i.e., an approximately 50/50 chance) of a short. In another embodiment different masks form first conductors (e.g., metal lines separated by varying distances and having different widths) and second conductors (e.g., metal vias separated by varying distances and having equal widths). The first and second conductors alternate across the chip. Due to the different separation distances and widths of the first conductors, the different separation distances of the second conductors and, random mask alignment variations, each first conductor can short to up to two second conductors. In each embodiment the resulting pattern of shorts and opens, can be used as an on-chip identifier or private key.
摘要翻译：公开了用于片上识别电路的设计结构。在一个实施例中，在一个或多个金属化层内形成导体对（例如，金属焊盘，通孔，线）。每对中的导体之间的距离是预先确定的，因此，在已知的跨越芯片线的变化中，存在短路的随机机会（即，大约50/50的几率）。在另一个实施例中，不同的掩模形成第一导体（例如，由变化的距离分隔并具有不同宽度的金属线）和第二导体（例如，通过变化的距离分开并具有相等宽度的金属通孔）。第一和第二导体在芯片之间交替。由于第一导体的分离距离和宽度不同，第二导体的不同间隔距离和随机掩模对准变化，每个第一导体可以短至多达两个第二导体。在每个实施例中，所得到的短路和开路模式可用作片上标识符或私钥。

9. 发明申请

US20090091351A1 CHIP IDENTIFICATION SYSTEM AND METHOD 有权
标题翻译：芯片识别系统和方法
公开(公告)号：US20090091351A1
公开(公告)日：2009-04-09
申请号：US11869179
申请日：2007-10-09
申请人： Serafino Bueti , Adams J. Courchesne , Kenneth J. Goodnow , Todd E. Leonard , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
发明人： Serafino Bueti , Adams J. Courchesne , Kenneth J. Goodnow , Todd E. Leonard , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
IPC分类号： H03K19/00 , H01L23/544
CPC分类号： H01L23/544 , H01L23/5286 , H01L2223/5444 , H01L2924/0002 , H01L2924/14 , H01L2924/19043 , H01L2924/00
摘要： Disclosed are embodiments of on-chip identification circuitry. In one embodiment, pairs of conductors (e.g., metal pads, vias, lines) are formed within one or more metallization layers. The distance between the conductors in each pair is predetermined so that, given known across chip line variations, there is a random chance (i.e., an approximately 50/50 chance) of a short. In another embodiment different masks form first conductors (e.g., metal lines separated by varying distances and having different widths) and second conductors (e.g., metal vias separated by varying distances and having equal widths). The first and second conductors alternate across the chip. Due to the different separation distances and widths of the first conductors, the different separation distances of the second conductors and, random mask alignment variations, each first conductor can short to up to two second conductors. In each embodiment the resulting pattern of shorts and opens, can be used as an on-chip identifier or private key.
摘要翻译：公开了片上识别电路的实施例。在一个实施例中，在一个或多个金属化层内形成导体对（例如，金属焊盘，通孔，线）。每对中的导体之间的距离是预先确定的，因此，在已知的跨越芯片线的变化中，存在短路的随机机会（即，大约50/50的几率）。在另一个实施例中，不同的掩模形成第一导体（例如，由变化的距离分隔并具有不同宽度的金属线）和第二导体（例如，通过变化的距离分开并具有相等宽度的金属通孔）。第一和第二导体在芯片之间交替。由于第一导体的分离距离和宽度不同，第二导体的不同间隔距离和随机掩模对准变化，每个第一导体可以短至多达两个第二导体。在每个实施例中，所得到的短路和开路模式可用作片上标识符或私钥。

10. 发明授权

US07511548B2 Clock distribution network, structure, and method for providing balanced loading in integrated circuit clock trees 失效
标题翻译：用于在集成电路时钟树中提供均衡负载的时钟分配网络，结构和方法
公开(公告)号：US07511548B2
公开(公告)日：2009-03-31
申请号：US11610963
申请日：2006-12-14
申请人： Serafino Bueti , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Serafino Bueti , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： G06F1/04
CPC分类号： G06F17/5045 , G06F2217/62
摘要： A clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.
摘要翻译：公开了一种用于提供平衡负载的时钟分配网络，结构和方法。特别地，时钟分配网络可以由一个或多个时钟扇出分配级别形成。每个相应的分配级别可以包括具有基本相同的物理和电气特性的相等数量的缓冲电路和布线路线。此外，最终分配级别可以包括具有将缓冲器电路连接到一个或多个逻辑叶连接节点的基本相同的物理和电气特性的布线路线。

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