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1. 发明授权

US06794282B2 Three layer aluminum deposition process for high aspect ratio CL contacts 失效
标题翻译：三层铝沉积工艺，用于高纵横比CL接触
公开(公告)号：US06794282B2
公开(公告)日：2004-09-21
申请号：US10305063
申请日：2002-11-27
申请人： Thomas Goebel , Werner Robl , Rajeev Malik , Mihel Seitz
发明人： Thomas Goebel , Werner Robl , Rajeev Malik , Mihel Seitz
IPC分类号： H01L2144
CPC分类号： H01L27/10888 , H01L21/76882
摘要： A method of forming a semiconductor device includes providing a semiconductor device including a conductor formed thereon. A dielectric layer is formed over the conductor and a recess is formed in the dielectric layer by removing a portion of the dielectric layer to expose at least a portion of the conductor. A first layer of aluminum is deposited over the top surface of the dielectric, along the sidewalls of the dielectric layer and over the exposed portion of the conductor without altering the temperature of the semiconductor device. A second layer of aluminum is deposited over the first layer of aluminum at a temperature greater than about 300° C. A third layer of aluminum is deposited over the second layer of aluminum so as to completely fill the recess in the dielectric layer. The third layer of aluminum is slow deposited at a temperature greater than about 300° C.
摘要翻译：形成半导体器件的方法包括提供包括形成在其上的导体的半导体器件。在导体上形成电介质层，并且通过去除电介质层的一部分以露出导体的至少一部分，在电介质层中形成凹陷。沿着电介质层的侧壁并在导体的暴露部分之上沉积在电介质的顶表面上的第一层铝，而不改变半导体器件的温度。在大于约300℃的温度下，在第一层铝上沉积第二层铝。第三层铝沉积在第二层铝上，以便完全填充介电层中的凹槽。第三层铝在大于约300℃的温度下缓慢沉积

2. 发明申请

US20060001162A1 Nitride and polysilicon interface with titanium layer 审中-公开
标题翻译：氮化物和多晶硅界面与钛层
公开(公告)号：US20060001162A1
公开(公告)日：2006-01-05
申请号：US11084724
申请日：2005-03-18
申请人： Ronald Schutz , Werner Robl , Rajeev Malik , Lawrence Clevenger , Oleg Gluschenkov , Cyril Cabral , Roy Iggulden , Yun-Yu Wang , Keith Wong , Irene McStay
发明人： Ronald Schutz , Werner Robl , Rajeev Malik , Lawrence Clevenger , Oleg Gluschenkov , Cyril Cabral , Roy Iggulden , Yun-Yu Wang , Keith Wong , Irene McStay
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/7685 , H01L21/28052 , H01L21/28061 , H01L21/76838 , H01L21/76855 , H01L21/823828 , H01L21/823842 , H01L29/4941 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/78 , H01L2221/1078
摘要： A conductive structure in an integrated circuit (12), and a method of forming the structure, is provided that includes a polysilicon layer (30), a thin layer containing titanium over the polysilicon, a tungsten nitride layer (34) over the titanium-containing layer and a tungsten layer over the tungsten nitride layer. The structure also includes a silicon nitride interfacial region (38) between the polysilicon layer and the titanium-containing layer. The structure withstands high-temperature processing without substantial formation of metal silicides in the polysilicon layer (30) and the tungsten layer (32), and provides low interface resistance between the tungsten layer and the polysilicon layer.
摘要翻译：提供集成电路（12）中的导电结构和形成该结构的方法，其包括多晶硅层（30），在多晶硅上含有钛的薄层，在钛 - 钛层上的氮化钨层（34）并且在氮化钨层上形成钨层。该结构还包括在多晶硅层和含钛层之间的氮化硅界面区域（38）。该结构经受高温处理，而在多晶硅层（30）和钨层（32）中基本不形成金属硅化物，并且在钨层和多晶硅层之间提供低的界面电阻。

3. 发明授权

US06720212B2 Method of eliminating back-end rerouting in ball grid array packaging 有权
标题翻译：消除球栅阵列封装中后端重路由的方法
公开(公告)号：US06720212B2
公开(公告)日：2004-04-13
申请号：US10098840
申请日：2002-03-14
申请人： Werner Robl , Thomas Goebel , Axel Christoph Brintzinger , Gerald Friese
发明人： Werner Robl , Thomas Goebel , Axel Christoph Brintzinger , Gerald Friese
IPC分类号： H01L2182
CPC分类号： H01L24/12 , H01L23/3114 , H01L24/11 , H01L2224/0231 , H01L2224/0401 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05548 , H01L2224/05624 , H01L2224/13099 , H01L2224/45144 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/10253 , H01L2924/14 , H01L2924/19043 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： Disclosed is a method of ball grid array packaging, comprising the steps of providing a semiconductor die having a metal conductors thereon, covering said metal conductors with an insulative layer, etching through said insulative layer so as to provide one or more openings to said metal conductors, depositing a compliant material layer, etching through said compliant material layer so as to provide one or more openings to said metal conductors, depositing a substantially homogenous conductive layer, patterning said conductive layer so as to bring at least one of said metal conductors in electrical contact with one or more pads, each said pad comprising a portion of said conductive layer disposed upon said compliant material, and providing solder balls disposed upon said pads. Also disclosed is the apparatus made from the method.
摘要翻译：公开了一种球栅阵列封装的方法，包括以下步骤：提供其上具有金属导体的半导体管芯，用绝缘层覆盖所述金属导体，蚀刻穿过所述绝缘层，以便向所述金属导体提供一个或多个开口沉积柔性材料层，蚀刻穿过所述柔性材料层，以便向所述金属导体提供一个或多个开口;沉积基本上均匀的导电层;图案化所述导电层，以将所述金属导体中的至少一个导入电与一个或多个焊盘接触，每个所述焊盘包括设置在所述柔性材料上的所述导电层的一部分，以及设置在所述焊盘上的焊球。还公开了由该方法制成的装置。

4. 发明授权

US06943114B2 Integration scheme for metal gap fill, with fixed abrasive CMP 有权
标题翻译：金属间隙填充的集成方案，固定磨料CMP
公开(公告)号：US06943114B2
公开(公告)日：2005-09-13
申请号：US10084194
申请日：2002-02-28
申请人： Peter Wrschka , Werner Robl , Thomas Goebel
发明人： Peter Wrschka , Werner Robl , Thomas Goebel
IPC分类号： H01L21/3105 , H01L21/302 , H01L21/461
CPC分类号： H01L21/31053 , Y10S438/959
摘要： In a method of planarizing a semiconductor wafer, the improvement comprising polishing above metal interconnect lines to uniformly polish the topography of the wafer to a predetermined endpoint on the wafer sufficiently close above the metal interconnect lines, yet far enough away from the lines to prevent damage to the lines, comprising:a) filling gaps between metal interconnect lines of an inter metal dielectric in a wafer being formed, by depositing HDP fill on top of the metal interconnects, between the metal interconnects, and on the surface of a dielectric layer between the metal interconnects to create an HDP overfill;b) contacting the surface of HDP overfill of the processed semiconductor wafer from step a) with a fixed abrasive polishing pad; andc) relatively moving the wafer and the fixed abrasive polishing pad to affect a polishing rate sufficient to reach a predetermined endpoint and uniformly planar surface on the wafer sufficiently close above the metal interconnect lines and yet far enough away from the lines to prevent damage to the lines.
摘要翻译：在平坦化半导体晶片的方法中，改进包括在金属互连线上方抛光，以将晶片的形貌均匀地抛光到晶片上的预定端点上，该晶圆足够靠近金属互连线上方，远离线路远离线以防止损坏包括：a）通过在金属互连件的顶部，金属互连件之间以及电介质层的表面上沉积HDP填充物，填充在形成的晶片之间的金属互连线之间的间隙，金属互连以产生HDP溢出; b）使来自步骤a）的经处理的半导体晶片的HDP的填充表面与固定的研磨抛光垫接触; 以及c）相对移动所述晶片和所述固定研磨抛光垫以影响足以达到所述晶片上的预定端点和所述晶片上的均匀平坦表面的抛光速率，所述平坦表面足够靠近所述金属互连线，并且远离所述线远离所述线，以防止损坏线条。

5. 发明授权

US06960306B2 Low Cu percentages for reducing shorts in AlCu lines 失效
标题翻译：用于减少AlCu线中短路的低Cu百分比
公开(公告)号：US06960306B2
公开(公告)日：2005-11-01
申请号：US10207773
申请日：2002-07-31
申请人： Roy C. Iggulden , Padraic Shafer , Kwong Hon (Keith) Wong , Michael M. Iwatake , Jay W. Strane , Thomas Goebel , Donna D. Miura , Chet Dziobkowski , Werner Robl , Brian Hughes
发明人： Roy C. Iggulden , Padraic Shafer , Kwong Hon (Keith) Wong , Michael M. Iwatake , Jay W. Strane , Thomas Goebel , Donna D. Miura , Chet Dziobkowski , Werner Robl , Brian Hughes
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/00
CPC分类号： H01L21/32051 , H01L21/76838
摘要： In a method of fabricating a metallization structure during formation of a microelectronic device, the improvement of reducing metal shorts in blanket metal deposition layers later subjected to reactive ion etching, comprising: a) depositing on a first underlayer, a blanket of an aluminum compound containing an electrical short reducing amount of an alloy metal in electrical contact with the underlayer; b) depositing a photoresist and exposing and developing to leave patterns of photoresist on the blanket aluminum compound containing an electrical short reducing amount of an alloy metal; and c) reactive ion etching to obtain an aluminum compound containing an alloy metal line characterized by reduced shorts in amounts less than the aluminum compound without said short reducing amount of alloy metal.
摘要翻译：在微电子器件形成期间制造金属化结构的方法中，改进后续进行反应离子蚀刻的覆盖金属沉积层中的金属短路，包括：a）沉积在第一底层上，与底层电接触的合金金属的电短路减少量; b）沉积光致抗蚀剂并曝光和显影以在包含合金金属的电短缩量的橡皮布铝化合物上留下光刻胶图案; 和c）反应离子蚀刻，以获得含有合金金属线的铝化合物，其特征在于少于铝化合物的短路量，而没有所述合金金属的减少量。

6. 发明授权

US08334202B2 Device fabricated using an electroplating process 有权
标题翻译：使用电镀工艺制造的器件
公开(公告)号：US08334202B2
公开(公告)日：2012-12-18
申请号：US12611609
申请日：2009-11-03
申请人： Jens Pohl , Hans-Joachim Barth , Gottfried Beer , Rainer Steiner , Werner Robl , Mathias Vaupel
发明人： Jens Pohl , Hans-Joachim Barth , Gottfried Beer , Rainer Steiner , Werner Robl , Mathias Vaupel
IPC分类号： H01L23/48
CPC分类号： H01L23/5389 , H01L21/486 , H01L21/76873 , H01L21/76879 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L24/82 , H01L24/97 , H01L2221/1089 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1461 , H01L2924/181 , H01L2224/82 , H01L2924/00
摘要： A method for fabricating a device includes providing a substrate including at least one contact and applying a dielectric layer over the substrate. The method includes applying a first seed layer over the dielectric layer, applying an inert layer over the seed layer, and structuring the inert layer, the first seed layer, and the dielectric layer to expose at least a portion of the contact. The method includes applying a second seed layer over exposed portions of the structured dielectric layer and the contact such that the second seed layer makes electrical contact with the structured first seed layer. The method includes electroplating a metal on the second seed layer.
摘要翻译：一种用于制造器件的方法包括提供包括至少一个接触的衬底并在衬底上施加电介质层。该方法包括在电介质层上施加第一种子层，在种子层上施加惰性层，以及构造惰性层，第一种子层和电介质层以暴露至少一部分接触。该方法包括在结构化介电层和触点的暴露部分上施加第二种子层，使得第二籽晶层与结构化的第一籽晶层电接触。该方法包括在第二种子层上电镀金属。

7. 发明申请

US20130278372A1 Semiconductor Component with Coreless Transformer 有权
标题翻译：无芯变压器半导体元件
公开(公告)号：US20130278372A1
公开(公告)日：2013-10-24
申请号：US13452075
申请日：2012-04-20
申请人： Matthias Stecher , Markus Menath , Andreas Zankl , Werner Robl
发明人： Matthias Stecher , Markus Menath , Andreas Zankl , Werner Robl
IPC分类号： H01F5/00
CPC分类号： H01L28/10 , H01F27/2804 , H01F2017/0086 , H01L23/5225 , H01L23/5227 , H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor component has integrated a coreless transformer with a first connection contact, a second connection contact, an electrically conductive spiral first coil, an electrically conductive first ring, and an electrically conductive second ring. The electrically conductive spiral first coil is electrically connected between the first connection contact and the second connection contact. The electrically conductive first ring surrounds the first coil and one or both of the first connection contact and the second connection contact. The electrically conductive second ring is arranged between the first coil and the first ring, electrically connected to the first coil, and surrounds the first coil and one or both of the first connection contact and the second connection contact.
摘要翻译：半导体部件集成了无芯变压器与第一连接触点，第二连接触点，导电螺旋第一线圈，导电第一环和导电第二环。导电螺旋第一线圈电连接在第一连接触点和第二连接触点之间。导电的第一环围绕第一线圈和第一连接触点和第二连接触点中的一个或两个。导电的第二环被布置在第一线圈和第一环之间，电连接到第一线圈，并且包围第一线圈以及第一连接触点和第二连接触点中的一个或两者。

8. 发明申请

US20130147047A1 Integrated Circuit and Method of Forming an Integrated Circuit 有权
标题翻译：集成电路和形成集成电路的方法
公开(公告)号：US20130147047A1
公开(公告)日：2013-06-13
申请号：US13315642
申请日：2011-12-09
申请人： Thomas Detzel , Johann Gross , Robert Illing , Maximilian Krug , Sven Gustav Lanzerstorfer , Michael Nelhiebel , Werner Robl , Michael Rogalli , Stefan Woehlert
发明人： Thomas Detzel , Johann Gross , Robert Illing , Maximilian Krug , Sven Gustav Lanzerstorfer , Michael Nelhiebel , Werner Robl , Michael Rogalli , Stefan Woehlert
IPC分类号： H01L23/48 , H01L21/28
CPC分类号： H01L23/3735 , H01L21/2885 , H01L21/4882 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a base element and a copper element over the base element, the copper element having a thickness of at least 5 μm and a ratio of average grain size to thickness of less than 0.7.
摘要翻译：集成电路包括在基底元件上的基底元件和铜元件，铜元件具有至少5μm的厚度，并且平均晶粒尺寸与厚度之比小于0.7。

9. 发明授权

US06734097B2 Liner with poor step coverage to improve contact resistance in W contacts 有权
标题翻译：衬垫差步幅覆盖，以提高W触点的接触电阻
公开(公告)号：US06734097B2
公开(公告)日：2004-05-11
申请号：US09965094
申请日：2001-09-28
申请人： Roy C. Iggulden , Padraic Shafer , Werner Robl , Kwong Hon Wong
发明人： Roy C. Iggulden , Padraic Shafer , Werner Robl , Kwong Hon Wong
IPC分类号： H01L214763
CPC分类号： H01L21/76844 , H01L21/76807 , H01L2924/0002 , H01L2924/00
摘要： A method of filling a damascene structure with liner and W characterized by improved resistance and resistance spread and adequate adhesion comprising: a given damascene structure coated by a liner which purposely provides poor step coverage into the afore mentioned structure, followed by a CVD W deposition, and followed by a metal isolation technique.
摘要翻译：一种用衬垫填充镶嵌结构的方法，其特征在于改进的阻力和阻力扩展以及足够的粘合性，其包括：由衬垫涂覆的给定镶嵌结构，其有目的地为上述结构提供差的步骤覆盖，随后进行CVD W沉积，其次是金属隔离技术。

10. 发明授权

US08665054B2 Semiconductor component with coreless transformer 有权
标题翻译：具有无芯变压器的半导体元件
公开(公告)号：US08665054B2
公开(公告)日：2014-03-04
申请号：US13452075
申请日：2012-04-20
申请人： Matthias Stecher , Markus Menath , Andreas Zankl , Werner Robl
发明人： Matthias Stecher , Markus Menath , Andreas Zankl , Werner Robl
IPC分类号： H01F5/00 , H01L27/08
CPC分类号： H01L28/10 , H01F27/2804 , H01F2017/0086 , H01L23/5225 , H01L23/5227 , H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor component has integrated a coreless transformer with a first connection contact, a second connection contact, an electrically conductive spiral first coil, an electrically conductive first ring, and an electrically conductive second ring. The electrically conductive spiral first coil is electrically connected between the first connection contact and the second connection contact. The electrically conductive first ring surrounds the first coil and one or both of the first connection contact and the second connection contact. The electrically conductive second ring is arranged between the first coil and the first ring, electrically connected to the first coil, and surrounds the first coil and one or both of the first connection contact and the second connection contact.
摘要翻译：半导体部件集成了无芯变压器与第一连接触点，第二连接触点，导电螺旋第一线圈，导电第一环和导电第二环。导电螺旋第一线圈电连接在第一连接触点和第二连接触点之间。导电的第一环围绕第一线圈和第一连接触点和第二连接触点中的一个或两个。导电的第二环被布置在第一线圈和第一环之间，电连接到第一线圈，并且包围第一线圈以及第一连接触点和第二连接触点中的一个或两者。

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