专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06794282B2 Three layer aluminum deposition process for high aspect ratio CL contacts 失效
标题翻译：三层铝沉积工艺，用于高纵横比CL接触
公开(公告)号：US06794282B2
公开(公告)日：2004-09-21
申请号：US10305063
申请日：2002-11-27
申请人： Thomas Goebel , Werner Robl , Rajeev Malik , Mihel Seitz
发明人： Thomas Goebel , Werner Robl , Rajeev Malik , Mihel Seitz
IPC分类号： H01L2144
CPC分类号： H01L27/10888 , H01L21/76882
摘要： A method of forming a semiconductor device includes providing a semiconductor device including a conductor formed thereon. A dielectric layer is formed over the conductor and a recess is formed in the dielectric layer by removing a portion of the dielectric layer to expose at least a portion of the conductor. A first layer of aluminum is deposited over the top surface of the dielectric, along the sidewalls of the dielectric layer and over the exposed portion of the conductor without altering the temperature of the semiconductor device. A second layer of aluminum is deposited over the first layer of aluminum at a temperature greater than about 300° C. A third layer of aluminum is deposited over the second layer of aluminum so as to completely fill the recess in the dielectric layer. The third layer of aluminum is slow deposited at a temperature greater than about 300° C.
摘要翻译：形成半导体器件的方法包括提供包括形成在其上的导体的半导体器件。在导体上形成电介质层，并且通过去除电介质层的一部分以露出导体的至少一部分，在电介质层中形成凹陷。沿着电介质层的侧壁并在导体的暴露部分之上沉积在电介质的顶表面上的第一层铝，而不改变半导体器件的温度。在大于约300℃的温度下，在第一层铝上沉积第二层铝。第三层铝沉积在第二层铝上，以便完全填充介电层中的凹槽。第三层铝在大于约300℃的温度下缓慢沉积

2. 发明授权

US06294423B1 Method for forming and filling isolation trenches 有权
标题翻译：用于形成和填充隔离沟槽的方法
公开(公告)号：US06294423B1
公开(公告)日：2001-09-25
申请号：US09718211
申请日：2000-11-21
申请人： Rajeev Malik , Mihel Seitz , Andreas Knorr
发明人： Rajeev Malik , Mihel Seitz , Andreas Knorr
IPC分类号： H01L218242
CPC分类号： H01L21/76229 , H01L27/1087
摘要： A method for forming isolation trenches for a semiconductor device forms, in a substrate, a plurality of trenches having different widths including widths above a threshold size and widths below a threshold size. The plurality of trenches have a same first depth. A masking layer is deposited in the plurality of trenches, the masking layer has a thickness sufficient to both line the trenches with the widths above the threshold size and completely fill the trenches with the widths below the threshold size. A portion of the substrate is exposed at a bottom of the trenches with the widths above the threshold size by etching the masking layer. The plurality of trenches is etched to extend the trenches with the widths above the threshold size to different depths.
摘要翻译：用于形成用于半导体器件的隔离沟槽的方法在衬底中形成具有不同宽度的多个沟槽，所述宽度包括高于阈值尺寸的宽度和低于阈值尺寸的宽度。多个沟槽具有相同的第一深度。掩蔽层沉积在多个沟槽中，掩模层具有足够的厚度以使沟槽线宽度高于阈值尺寸，并以宽度低于阈值尺寸完全填充沟槽。通过蚀刻掩模层，将衬底的一部分暴露在沟槽底部，宽度高于阈值大小。多个沟槽被蚀刻以将具有高于阈值尺寸的宽度的沟槽延伸到不同的深度。

3. 发明授权

US06724054B1 Self-aligned contact formation using double SiN spacers 失效
标题翻译：使用双SiN间隔物的自对准接触形成
公开(公告)号：US06724054B1
公开(公告)日：2004-04-20
申请号：US10320867
申请日：2002-12-17
申请人： Woo-tag Kang , Rajeev Malik , Mihel Seitz
发明人： Woo-tag Kang , Rajeev Malik , Mihel Seitz
IPC分类号： H01L31119
CPC分类号： H01L21/76897 , H01L29/6656
摘要： A method for fabricating a self-aligned contact in an integrated circuit includes defining first spacer layers over the sidewalls of a pair of wordline stacks. An oxide layer is deposited over the tops of the wordline stacks, the first spacer layers and a surface of the substrate disposed between the first spacer layers. The oxide layer is removed from the first spacer layers, thereby forming a remaining oxide layer that covers the surface of the substrate disposed between the first spacer layers. Second spacer layers are formed over the first spacer layers, and which cover respective portions of the remaining oxide layer. The remaining oxide layer is removed to thereby form undercut regions. The undercut regions are substantially filled with contact material during formation of the contact.
摘要翻译：在集成电路中制造自对准接触的方法包括在一对字线堆叠的侧壁上限定第一间隔层。氧化物层沉积在字线堆叠的顶部上，第一间隔层和设置在第一间隔层之间的衬底的表面。从第一间隔层去除氧化物层，从而形成覆盖设置在第一间隔层之间的衬底的表面的剩余氧化物层。第二间隔层形成在第一间隔层之上，并且覆盖剩余氧化物层的各个部分。除去剩余的氧化物层，从而形成底切区域。在形成接触期间，底切区域基本上被接触材料填充。

4. 发明授权

US06509226B1 Process for protecting array top oxide 有权
标题翻译：保护阵列顶部氧化物的方法
公开(公告)号：US06509226B1
公开(公告)日：2003-01-21
申请号：US09670741
申请日：2000-09-27
申请人： Venkatachalam C. Jaiprakash , Jack Mandelman , Ramachandra Divakaruni , Rajeev Malik , Mihel Seitz
发明人： Venkatachalam C. Jaiprakash , Jack Mandelman , Ramachandra Divakaruni , Rajeev Malik , Mihel Seitz
IPC分类号： H01L218242
CPC分类号： H01L27/10861
摘要： Processing of a DRAM device containing vertical MOSFET arrays proceeds through planarization of the array gate conductor (GC) polysilicon of the vertical MOSFET to the top surface of the top oxide. A thin polysilicon layer is deposited over the planarized surface and an active area (M) pad nitride and tetraethyl orthosilicate (TEOS) stack is deposited. The M mask is used to open the pad layer to the silicon surface, and shallow trench isolation (STI) etching is used to form isolation trenches. An AA oxidation is performed, the isolation trenches are filled with high density plasma (HDP) oxide and planarized to the top surface of the AA pad nitride. Following isolation trench (IT) planarization, the AA pad nitride is stripped, with the thin silicon layer serving as an etch stop protecting the underlying top oxide. The etch support (ES) nitride liner is deposited, and the ES mask is patterned to open the support areas. The ES nitride, thin polysilicon layer and top oxide are etched from the exposed areas. A sacrificial oxidation is applied along with well implants, support gate oxidation and support gate polysilicon deposition. Using the etch array (EA) mask, the support gate polysilicon is opened in the array. The ES nitride is removed selective to the underlying silicon layer, protecting the top oxide. The gate stack is deposited and patterned and the process continues to completion.
摘要翻译：包含垂直MOSFET阵列的DRAM器件的处理通过将垂直MOSFET的阵列栅极导体（GC）多晶硅平坦化到顶部氧化物的顶表面进行。在平坦化表面上沉积薄多晶硅层，并沉积有源区（M）衬垫氮化物和原硅酸四乙酯（TEOS）堆叠。 M掩模用于将焊盘层打开到硅表面，并且使用浅沟槽隔离（STI）蚀刻来形成隔离沟槽。执行AA氧化，隔离沟槽填充有高密度等离子体（HDP）氧化物，并且平坦化到AA衬垫氮化物的顶表面。在隔离沟槽（IT）平坦化之后，剥离AA衬垫氮化物，薄硅层用作保护底层氧化物的蚀刻停止层。沉积蚀刻载体（ES）氮化物衬垫，并且将ES掩模图案化以打开支撑区域。从暴露的区域蚀刻ES氮化物，薄多晶硅层和顶部氧化物。牺牲氧化与井注入一起施加，支持栅极氧化和支撑栅极多晶硅沉积。使用蚀刻阵列（EA）掩模，在阵列中打开支撑栅极多晶硅。对于下层硅层选择性地除去ES氮化物，保护顶部氧化物。沉积栅极堆叠并图案化，并且该工艺继续完成。

5. 发明申请

US20060001162A1 Nitride and polysilicon interface with titanium layer 审中-公开
标题翻译：氮化物和多晶硅界面与钛层
公开(公告)号：US20060001162A1
公开(公告)日：2006-01-05
申请号：US11084724
申请日：2005-03-18
申请人： Ronald Schutz , Werner Robl , Rajeev Malik , Lawrence Clevenger , Oleg Gluschenkov , Cyril Cabral , Roy Iggulden , Yun-Yu Wang , Keith Wong , Irene McStay
发明人： Ronald Schutz , Werner Robl , Rajeev Malik , Lawrence Clevenger , Oleg Gluschenkov , Cyril Cabral , Roy Iggulden , Yun-Yu Wang , Keith Wong , Irene McStay
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/7685 , H01L21/28052 , H01L21/28061 , H01L21/76838 , H01L21/76855 , H01L21/823828 , H01L21/823842 , H01L29/4941 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/78 , H01L2221/1078
摘要： A conductive structure in an integrated circuit (12), and a method of forming the structure, is provided that includes a polysilicon layer (30), a thin layer containing titanium over the polysilicon, a tungsten nitride layer (34) over the titanium-containing layer and a tungsten layer over the tungsten nitride layer. The structure also includes a silicon nitride interfacial region (38) between the polysilicon layer and the titanium-containing layer. The structure withstands high-temperature processing without substantial formation of metal silicides in the polysilicon layer (30) and the tungsten layer (32), and provides low interface resistance between the tungsten layer and the polysilicon layer.
摘要翻译：提供集成电路（12）中的导电结构和形成该结构的方法，其包括多晶硅层（30），在多晶硅上含有钛的薄层，在钛 - 钛层上的氮化钨层（34）并且在氮化钨层上形成钨层。该结构还包括在多晶硅层和含钛层之间的氮化硅界面区域（38）。该结构经受高温处理，而在多晶硅层（30）和钨层（32）中基本不形成金属硅化物，并且在钨层和多晶硅层之间提供低的界面电阻。

6. 发明授权

US07446395B2 Device having dual etch stop liner and protective layer 有权
标题翻译：具有双蚀刻停止衬垫和保护层的器件
公开(公告)号：US07446395B2
公开(公告)日：2008-11-04
申请号：US11845888
申请日：2007-08-28
申请人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha
发明人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha
IPC分类号： H01L23/58
CPC分类号： H01L21/0217 , H01L21/02271 , H01L21/02274 , H01L21/31116 , H01L21/3185 , H01L21/823807 , H01L21/84 , H01L29/7842 , H01L29/7843
摘要： The present invention provides a semiconductor device having dual nitride liners, a silicide layer, and a protective layer beneath one of the nitride liners for preventing the etching of the silicide layer. A first aspect of the invention provides a semiconductor device comprising a protective layer adjacent a first device, a first silicon nitride liner over the protective layer, a second silicon nitride liner adjacent a second device, and a first silicide layer adjacent the first device and a second silicide layer adjacent the second device, wherein a thickness is substantially the same in the first and second silicide layers.
摘要翻译：本发明提供一种半导体器件，其具有双氮化物衬垫，硅化物层和位于氮化物衬底之下的保护层，用于防止蚀刻硅化物层。本发明的第一方面提供一种半导体器件，其包括与第一器件相邻的保护层，保护层上的第一氮化硅衬垫，与第二器件相邻的第二氮化硅衬底以及与第一器件相邻的第一硅化物层和第二硅化物层，其中第一和第二硅化物层中的厚度基本相同。

7. 发明申请

US20070292696A1 DEVICE HAVING DUAL ETCH STOP LINER AND PROTECTIVE LAYER 有权
标题翻译：具有双层止动衬板和保护层的装置
公开(公告)号：US20070292696A1
公开(公告)日：2007-12-20
申请号：US11845888
申请日：2007-08-28
申请人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha
发明人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha
IPC分类号： B32B9/04
CPC分类号： H01L21/0217 , H01L21/02271 , H01L21/02274 , H01L21/31116 , H01L21/3185 , H01L21/823807 , H01L21/84 , H01L29/7842 , H01L29/7843
摘要： The present invention provides a semiconductor device having dual nitride liners, a silicide layer, and a protective layer beneath one of the nitride liners for preventing the etching of the silicide layer. A first aspect of the invention provides a semiconductor device comprising a protective layer adjacent a first device, a first silicon nitride liner over the protective layer, a second silicon nitride liner adjacent a second device, and a first silicide layer adjacent the first device and a second silicide layer adjacent the second device, wherein a thickness is substantially the same in the first and second silicide layers.
摘要翻译：本发明提供一种半导体器件，其具有双氮化物衬垫，硅化物层和位于氮化物衬底之下的保护层，用于防止蚀刻硅化物层。本发明的第一方面提供一种半导体器件，其包括与第一器件相邻的保护层，保护层上的第一氮化硅衬垫，与第二器件相邻的第二氮化硅衬底以及与第一器件相邻的第一硅化物层和第二硅化物层，其中第一和第二硅化物层中的厚度基本相同。

8. 发明申请

US20060128086A1 DEVICE HAVING DUAL ETCH STOP LINER AND PROTECTIVE LAYER AND RELATED METHODS 有权
标题翻译：具有双层阻挡层和保护层的装置及相关方法
公开(公告)号：US20060128086A1
公开(公告)日：2006-06-15
申请号：US10905024
申请日：2004-12-10
申请人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha
发明人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha
IPC分类号： H01L21/8238 , H01L21/31
CPC分类号： H01L21/0217 , H01L21/02271 , H01L21/02274 , H01L21/31116 , H01L21/3185 , H01L21/823807 , H01L21/84 , H01L29/7842 , H01L29/7843
摘要： The present invention provides a semiconductor device having dual nitride liners, a silicide layer, and a protective layer beneath one of the nitride liners for preventing the etching of the silicide layer. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a protective layer to a device, applying a first silicon nitride liner to the device, removing a portion of the first silicon nitride liner, removing a portion of the protective layer, and applying a second silicon nitride liner to the device.
摘要翻译：本发明提供一种半导体器件，其具有双氮化物衬垫，硅化物层和位于氮化物衬底之下的保护层，用于防止蚀刻硅化物层。本发明的第一方面提供一种用于制造半导体器件的方法，包括以下步骤：向器件施加保护层，向器件施加第一氮化硅衬垫，去除第一氮化硅衬垫的一部分，去除所述保护层的一部分，以及向所述装置施加第二氮化硅衬垫。

9. 发明申请

US20060110685A1 Apparatus and method to improve resist line roughness in semiconductor wafer processing 审中-公开
标题翻译：改善半导体晶片处理中抗蚀剂线粗糙度的装置和方法
公开(公告)号：US20060110685A1
公开(公告)日：2006-05-25
申请号：US11329991
申请日：2006-01-10
申请人： Wai-kin Li , Rajeev Malik , Joseph Mezzapelle
发明人： Wai-kin Li , Rajeev Malik , Joseph Mezzapelle
IPC分类号： G03F7/00
CPC分类号： G03F7/091 , G03F7/11 , Y10S430/151
摘要： A process for prohibiting amino group transport from the top surface of a layered semiconductor wafer to a photoresist layer introduces a thin film oxynitride over the silicon nitride layer using a high temperature step of nitrous oxide (N2O) plus oxygen (O2) at approximately 300° C. for about 50 to 120 seconds. By oxidizing the silicon nitride layer, the roughness resulting from the adverse affects of amino group transport eliminated. Moreover, this high temperature step, non-plasma process can be used with the more advanced 193 nanometer technology, and is not limited to the 248 nanometer technology. A second method for exposing the silicon nitride layer to an oxidizing ambient, prior to the application of antireflective coating, introduces a mixture of N2H2 and oxygen (O2) ash at a temperature greater than or equal to 250° C. for approximately six minutes. This is followed by an O2 plasma clean and/or an Ozone clean, and then the subsequent layering of the ARC and photoresist.
摘要翻译：用于禁止从层状半导体晶片的顶表面到光致抗蚀剂层的氨基转移的方法使用一氧化二氮（N 2 O 2 O）的高温步骤在氮化硅层上引入薄膜氧氮化物，在约300℃下加氧气（O 2 H 2）约50至120秒。通过氧化氮化硅层，消除了由氨基转移的不利影响产生的粗糙度。此外，这种高温步骤，非等离子体工艺可以采用更先进的193纳米技术，并不限于248纳米技术。在施加抗反射涂层之前，将氮化硅层暴露于氧化环境的第二种方法是引入N 2 H 2 O 2和氧的混合物（O _{2℃）灰分，温度大于或等于250℃约6分钟。之后是等离子体清洁和/或臭氧清洁，然后再分层ARC和光致抗蚀剂。}

10. 发明授权

US06897107B2 Method for forming TTO nitride liner for improved collar protection and TTO reliability 失效
标题翻译：用于形成TTO氮化物衬垫以改善套环保护和TTO可靠性的方法
公开(公告)号：US06897107B2
公开(公告)日：2005-05-24
申请号：US10720490
申请日：2003-11-24
申请人： Rama Divakaruni , Thomas W. Dyer , Rajeev Malik , Jack A. Mandelman , Venkatachajam C. Jaiprakash
发明人： Rama Divakaruni , Thomas W. Dyer , Rajeev Malik , Jack A. Mandelman , Venkatachajam C. Jaiprakash
IPC分类号： H01L21/316 , H01L21/318 , H01L21/8242 , H01L21/20
CPC分类号： H01L27/10864 , H01L21/31612 , H01L21/3185 , H01L27/10867
摘要： A structure and method which enables the deposit of a thin nitride liner just before Trench Top Oxide TTO (High Density Plasma) HDP deposition during the formation of a vertical MOSFET DRAM cell device. This liner is subsequently removed after TTO sidewall etch. One function of this liner is to protect the collar oxide from being etched during the TTO oxide sidewall etch and generally provides lateral etch protection which is not realized in the current processing scheme. The process sequence does not rely on previously deposited films for collar protection, and decouples TTO sidewall etch protection from previous processing steps to provide additional process flexibility, such as allowing a thinner strap Cut Mask nitride and greater nitride etching during node nitride removal and buried strap nitrided interface removal. Advantageously, the presence of the nitride liner beneath the TTO reduces possibility of TTO dielectric breakdown between the gate and capacitor node electrode of the vertical MOSFET DRAM cell, while assuring strap diffusion to gate conductor overlap.
摘要翻译：在垂直MOSFET DRAM单元器件形成期间，能够在沟槽顶氧化物TTO（高密度等离子体）HDP沉积之前沉积薄氮化物衬垫的结构和方法。随后在TTO侧壁蚀刻之后移除该衬垫。该衬垫的一个功能是在TTO氧化物侧壁蚀刻期间保护套环氧化物不被蚀刻，并且通常提供在当前处理方案中未实现的横向蚀刻保护。工艺顺序不依赖于以前沉积的膜用于套环保护，并且将TTO侧壁蚀刻保护与先前的处理步骤解耦以提供附加的工艺灵活性，例如在节点氮化物去除期间允许更薄的带切割掩模氮化物和更大的氮化物蚀刻和掩埋带氮化界面去除。有利地，在TTO之下的氮化物衬垫的存在降低了垂直MOSFET DRAM单元的栅极和电容器节点电极之间的TTO介质击穿的可能性，同时确保带扩散到栅极导体重叠。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式