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1. 发明授权

US06608512B2 Full rail drive enhancement to differential SEU hardening circuit 有权
标题翻译：全轨驱动增强差分SEU硬化电路
公开(公告)号：US06608512B2
公开(公告)日：2003-08-19
申请号：US10034808
申请日：2001-12-28
申请人： Theodore T. Ta , Keith W. Golke
发明人： Theodore T. Ta , Keith W. Golke
IPC分类号： H03K3037
CPC分类号： G11C11/4125
摘要： A hardening circuit is provided for an integrated circuit which includes a data state reinforcing feedback path having a data node Q and a data complement node QN. A first hardening transistor is coupled between a rail and the data node Q, and a second hardening transistor coupled between the rail and the data complement node QN. The first and second hardening transistors provide additional drive to the data node Q and the data complement node QN. Gate controls operate the first and second hardening transistors and provide full rail drive to SEU sensitive nodes.
摘要翻译：提供一种用于集成电路的硬化电路，其包括具有数据节点Q和数据补码节点QN的数据状态加强反馈路径。第一固化晶体管耦合在轨道和数据节点Q之间，以及耦合在轨道和数据补码节点QN之间的第二硬化晶体管。第一和第二硬化晶体管为数据节点Q和数据补码节点QN提供额外的驱动。门控制操作第一和第二硬化晶体管，并为SEU敏感节点提供完整的轨道驱动。

2. 发明授权

US5309389A Read-only memory with complementary data lines 失效
标题翻译：具有互补数据线的只读存储器
公开(公告)号：US5309389A
公开(公告)日：1994-05-03
申请号：US112485
申请日：1993-08-27
申请人： Keith W. Golke , Mai T. MacLennan
发明人： Keith W. Golke , Mai T. MacLennan
IPC分类号： G11C5/00 , G11C17/12
CPC分类号： G11C5/005 , G11C17/12
摘要： A plurality of single transistor memory cells arrayed in columns with the memory cells within a column connected to one or the other of precharged first and second output lines. An input line connected to the gate of the single transistor causes the first output line to be pulled to a first voltage when the cell is programmed a "true" and to be pulled to a second voltage when the cell is programmed a "complement". A pair of cross-coupled transistors connected between the first and second output lines of a column cause the second output line to be maintained at the precharged voltage when programmed a "true" and causes the first output line to be maintained at a precharged voltage when programmed a "complement".
摘要翻译：多个单个晶体管存储单元排列成列，其中存储单元位于连接到预充电的第一和第二输出线之一或另一个的列内。连接到单个晶体管的栅极的输入线使得当单元被编程为“真”时将第一输出线拉至第一电压，并且当单元被编程为“补码”时将其拉至第二电压。连接在列的第一和第二输出线之间的一对交叉耦合晶体管使第二输出线在编程为“真”时保持在预充电电压，并且使第一输出线保持在预充电电压，当编程为“补充”。

3. 发明授权

US06180984B2 Integrated circuit impedance device and method of manufacture therefor 失效
标题翻译：集成电路阻抗装置及其制造方法
公开(公告)号：US06180984B2
公开(公告)日：2001-01-30
申请号：US09219804
申请日：1998-12-23
申请人： Keith W. Golke , Paul S. Fechner
发明人： Keith W. Golke , Paul S. Fechner
IPC分类号： H01L2910
CPC分类号： H01L21/84 , H01L27/1203
摘要： A multi-purpose device that can serve as either a resistor, MOSFET or JFET is disclosed. The resistor is formed by selecting a first metal interconnect configuration, the MOSFET is formed by selecting a second metal interconnect configuration, and the JFET is formed by selecting a third metal interconnect configuration. Because of the dual transistor/resistor nature of this device, the density of a typical gate array that uses resistors may be increased. In addition, and because no special processing is typically required, the device may be desirable for use in other types of structures such as standard cells and custom logic.
摘要翻译：公开了可以用作电阻器，MOSFET或JFET的多用途器件。通过选择第一金属互连配置来形成电阻器，通过选择第二金属互连配置形成MOSFET，并且通过选择第三金属互连配置来形成JFET。由于该器件的双晶体管/电阻器性质，可能会增加使用电阻器的典型栅极阵列的密度。此外，由于通常不需要特殊处理，所以该装置可能需要用于其他类型的结构，例如标准单元和定制逻辑。

4. 发明授权

US6058041A SEU hardening circuit 有权
标题翻译： SEU硬化电路
公开(公告)号：US6058041A
公开(公告)日：2000-05-02
申请号：US219807
申请日：1998-12-23
申请人： Keith W. Golke , Paul S. Fechner
发明人： Keith W. Golke , Paul S. Fechner
IPC分类号： H03K19/0944 , G11C5/00 , G11C11/412 , G11C11/00
CPC分类号： G11C5/005 , G11C11/4125
摘要： A SEU hardening circuit for use with a data storage circuit is described. The SEU hardening circuit may use a transmission gate to provide full rail drive during a write operation. The SEU hardening circuit may also be configured so that the transistors of the SEU hardening circuit are not susceptible to parasitic bipolar turn-on particularly during a radiation event, which can increase the SEU protection provided by the circuit.
摘要翻译：描述了与数据存储电路一起使用的SEU硬化电路。 SEU硬化电路可以在写入操作期间使用传输门来提供完整的轨道驱动。 SEU硬化电路也可以被配置为使得SEU硬化电路的晶体管不易受寄生双极导通，特别是在辐射事件期间，这可能增加由电路提供的SEU保护。

5. 发明授权

US07322015B2 Simulating a dose rate event in a circuit design 有权
标题翻译：模拟电路设计中的剂量率事件
公开(公告)号：US07322015B2
公开(公告)日：2008-01-22
申请号：US11029308
申请日：2005-01-05
申请人： Harry H. L. Liu , Keith W. Golke , Eric E. Vogt , Michael S. Liu
发明人： Harry H. L. Liu , Keith W. Golke , Eric E. Vogt , Michael S. Liu
IPC分类号： G06F17/50 , G06G7/62
CPC分类号： G06F17/5036
摘要： Behaviors of a transistor during a dose rate event can be modeled using a circuit simulation software package. A subcircuit model replaces a transistor in a circuit design to be simulated. The subcircuit model can be in the form of a schematic-based representation or a netlist. The subcircuit model provides a model of a source junction and a drain junction in the transistor during the dose rate event. The subcircuit model also includes the size of the transistor being replaced and the dose rate of the dose rate event. Once the transistor is replaced with the subcircuit model, a dose rate simulation may be performed to determine the dose rate hardness of the circuit design.
摘要翻译：在剂量率事件期间晶体管的行为可以使用电路仿真软件包进行建模。子电路模型取代要仿真的电路设计中的晶体管。子电路模型可以是基于原理图的表示形式或网表。子电路模型在剂量率事件期间提供晶体管中的源极结和漏极结的模型。子电路模型还包括被替换的晶体管的尺寸和剂量率事件的剂量率。一旦晶体管被子电路模型替代，可以执行剂量率模拟来确定电路设计的剂量率硬度。

6. 发明授权

US5867039A CMOS output driver with p-channel substrate tracking for cold spare capability 失效
标题翻译： CMOS输出驱动器，具有p沟道衬底跟踪，用于冷备用能力
公开(公告)号：US5867039A
公开(公告)日：1999-02-02
申请号：US649344
申请日：1996-05-17
申请人： Keith W. Golke
发明人： Keith W. Golke
IPC分类号： H03K19/0175 , H03K19/003 , H03K19/0185
CPC分类号： H03K19/00315
摘要： A CMOS output driver circuit with p-channel substrate tracking provides an output driver to full power supply voltage. The circuit is especially useful as a redundant circuit where its power supply connection is connected to ground and the circuit is kept in unbiased storage until it is needed.
摘要翻译：具有p沟道衬底跟踪的CMOS输出驱动器电路为全电源电压提供了一个输出驱动器。该电路作为其电源连接连接到地的冗余电路是特别有用的，并且该电路在需要时保持在无偏压的存储中。

7. 发明授权

US5410501A Read-only memory 失效
标题翻译：只读存储器
公开(公告)号：US5410501A
公开(公告)日：1995-04-25
申请号：US113569
申请日：1993-08-27
申请人： Keith W. Golke , Malt MacLennan
发明人： Keith W. Golke , Malt MacLennan
IPC分类号： G11C5/00 , G11C17/12
CPC分类号： G11C5/005 , G11C17/12
摘要： A plurality of memory cells arrayed in columns with the memory cells within a column connected between precharged first and second output lines. An input line selects a memory cell within a volume causing the first output line to be pulled to a first voltage when the cell is programmed a true and causing the second output line to be pulled to a first voltage when the cell is programmed a "complement". A pair of cross-coupled transistors connected between the first and second output lines of a column causes the second output line to be maintained at the precharged voltage when programmed a "true" and causes the first output line to be maintained at a precharged voltage when the cell is programmed a "complement".
摘要翻译：多个存储单元排列成列，其中存储单元位于连接在预充电的第一和第二输出行之间的列内。输入线选择体积内的存储器单元，使得当单元被编程为真时将第一输出线拉至第一电压，并且当单元被编程为“补码”时使第二输出线被拉至第一电压 “。连接在列的第一和第二输出线之间的一对交叉耦合晶体管使第二输出线在编程为“真”时保持在预充电电压，并使第一输出线保持在预充电电压，当单元被编程为“补码”。

8. 发明授权

US07693001B2 SRAM split write control for a delay element 有权
标题翻译：用于延迟元件的SRAM分离写入控制
公开(公告)号：US07693001B2
公开(公告)日：2010-04-06
申请号：US12013856
申请日：2008-01-14
申请人： Keith W. Golke , Harry H L Liu , David K. Nelson
发明人： Keith W. Golke , Harry H L Liu , David K. Nelson
IPC分类号： G11C8/00
CPC分类号： G11C7/02 , G11C5/005 , G11C8/14 , G11C11/4125
摘要： A Static Random Access Memory (SRAM) having a split write control is described. The SRAM includes bit, write, and write-word lines. Each memory cell within the SRAM includes a delay which is coupled to a dedicated write-word line. When a cell is not being written, its delay receives a delay signal on its associated write-word line, which increases the response time of the cell. When a cell is to be written, however, its delay receives a bypass signal on its associated write-word line, which decreases the response time of the SRAM cell.
摘要翻译：描述具有分离写入控制的静态随机存取存储器（SRAM）。 SRAM包括位，写和写字线。 SRAM内的每个存储单元包括耦合到专用写字线的延迟。当单元未被写入时，其延迟在其相关联的写字线上接收延迟信号，这增加了单元的响应时间。然而，当单元被写入时，其延迟在其相关的写字线上接收旁路信号，这降低了SRAM单元的响应时间。

9. 发明授权

US06909637B2 Full rail drive enhancement to differential SEU hardening circuit while loading data 有权
标题翻译：在加载数据时，全速驱动增强到差分SEU硬化电路
公开(公告)号：US06909637B2
公开(公告)日：2005-06-21
申请号：US10306465
申请日：2002-11-27
申请人： David K. Nelson , Keith W. Golke
发明人： David K. Nelson , Keith W. Golke
IPC分类号： G11C5/00 , G11C11/00 , G11C11/412 , G11C16/04 , H03K3/00
CPC分类号： G11C5/005
摘要： A hardening system includes a data storage device having a data input, a clock input, a data node Q, and a data complement node QN. The data storage device provides drive to the data node Q and the data complement node QN. A hardening circuit includes first, second, third, fourth, and fifth transistor circuits. The first and second transistor circuits form a first node therebetween, and the first transistor circuit prevents the data node Q from changing states in the presence of radiation. The third and fourth transistor circuits form a second node therebetween, and the third transistor circuit prevents the data complement node QN from changing states in the presence of radiation. The first node is coupled to the third transistor circuit, and the second node is coupled to the first transistor circuit. The fifth transistor circuit prevents the first and second nodes from floating.
摘要翻译：硬化系统包括具有数据输入，时钟输入，数据节点Q和数据补码节点QN的数据存储装置。数据存储设备向数据节点Q和数据补码节点QN提供驱动。硬化电路包括第一，第二，第三，第四和第五晶体管电路。第一和第二晶体管电路在它们之间形成第一节点，并且第一晶体管电路防止数据节点Q在存在辐射的情况下改变状态。第三和第四晶体管电路在其间形成第二节点，并且第三晶体管电路防止数据补码节点QN在存在辐射的情况下改变状态。第一节点耦合到第三晶体管电路，第二节点耦合到第一晶体管电路。第五晶体管电路防止第一和第二节点浮动。

10. 发明授权

US4761571A Memory circuit enchancement to stablize the signal lines with additional capacitance 失效
标题翻译：记忆电路使用增加电容来稳定信号线
公开(公告)号：US4761571A
公开(公告)日：1988-08-02
申请号：US811145
申请日：1985-12-19
申请人： Keith W. Golke , Robert L. Rabe
发明人： Keith W. Golke , Robert L. Rabe
IPC分类号： G11C7/12 , G11C11/419 , G11C11/24 , G06F1/00 , G11C11/40 , H03K19/003
CPC分类号： G11C7/12 , G11C11/419
摘要： A memory system having voltage level circuit switching portions operated between signal lines stabilized by additional capacitance.
摘要翻译：一种存储器系统，其具有在由附加电容稳定的信号线之间操作的电压电平电路切换部

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