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1. 发明授权

US06794916B1 Double edge-triggered flip-flops 失效
标题翻译：双边沿触发器
公开(公告)号：US06794916B1
公开(公告)日：2004-09-21
申请号：US10449791
申请日：2003-05-30
申请人： Pradeep Varma
发明人： Pradeep Varma
IPC分类号： H03K3037
CPC分类号： H03K3/012 , H03K3/037 , H03K3/356156
摘要： A static, double-edged triggered flip-flop has an upper data path and a lower data path connected between a data input node and an output terminal. The upper path includes a switch connected to a first data loop, and the lower path includes a switch connected to a second data loop. The first and second data loop share a forward path having a data-inverting circuit and a feedback loop having a switch. In addition, each loop has a feedback path having a weak transistor. For the upper data path, the feedback transistor is operated on the basis of a skewed clock signal. For the lower data path the feedback transistor is operated on the basis of a complementary skewed clock signal. The use of clock skew and feedforward assist in race resolution. The use of extra resistance in the feedback transistor of the shared path similarly ensures that a race will be correctly resolved.
摘要翻译：静态双边触发触发器具有连接在数据输入节点和输出端子之间的较高数据路径和较低数据路径。上部路径包括连接到第一数据环路的开关，并且下部路径包括连接到第二数据环路的开关。第一和第二数据环共享具有数据反相电路的正向路径和具有开关的反馈回路。此外，每个环路具有具有弱晶体管的反馈路径。对于较高的数据路径，反馈晶体管基于偏斜的时钟信号进行操作。对于较低的数据通路，反馈晶体管基于互补偏移时钟信号进行工作。使用时钟偏移和前馈帮助种族分辨率。在共享路径的反馈晶体管中使用额外的电阻类似地确保了竞赛将被正确地解决。

2. 发明授权

US06700424B2 Multiple-channel optical transceiver input buffer with zero static current and symmetrical hysteresis 失效
标题翻译：具有零静态电流和对称滞后的多通道光收发器输入缓冲器
公开(公告)号：US06700424B2
公开(公告)日：2004-03-02
申请号：US09682044
申请日：2001-07-13
申请人： Kai Di Feng
发明人： Kai Di Feng
IPC分类号： H03K3037
CPC分类号： H03K3/3565 , H03K17/223
摘要： An input buffer for an optical receiver or transceiver which provides symmetrical hysteresis and zero static current, comprises two field effect transistors (FETs) which form the basic buffer logic circuit, two FETs which respectively provide offset voltages to the buffer logic FETs, and two FETs which provide positive feedback. In the preferred embodiment the input buffer provides multiple-channels, each channel comprising a component inverter designed to provide zero static current and symmetrical hysteresis for a different input signal mode.
摘要翻译：用于提供对称滞后和零静态电流的光接收器或收发器的输入缓冲器包括形成基本缓冲逻辑电路的两个场效应晶体管（FET），分别向缓冲逻辑FET提供偏置电压的两个FET和两个FET 这提供了积极的反馈。在优选实施例中，输入缓冲器提供多通道，每个通道包括被设计成为不同的输入信号模式提供零静态电流和对称滞后的分量反相器。

3. 发明授权

US06608512B2 Full rail drive enhancement to differential SEU hardening circuit 有权
标题翻译：全轨驱动增强差分SEU硬化电路
公开(公告)号：US06608512B2
公开(公告)日：2003-08-19
申请号：US10034808
申请日：2001-12-28
申请人： Theodore T. Ta , Keith W. Golke
发明人： Theodore T. Ta , Keith W. Golke
IPC分类号： H03K3037
CPC分类号： G11C11/4125
摘要： A hardening circuit is provided for an integrated circuit which includes a data state reinforcing feedback path having a data node Q and a data complement node QN. A first hardening transistor is coupled between a rail and the data node Q, and a second hardening transistor coupled between the rail and the data complement node QN. The first and second hardening transistors provide additional drive to the data node Q and the data complement node QN. Gate controls operate the first and second hardening transistors and provide full rail drive to SEU sensitive nodes.
摘要翻译：提供一种用于集成电路的硬化电路，其包括具有数据节点Q和数据补码节点QN的数据状态加强反馈路径。第一固化晶体管耦合在轨道和数据节点Q之间，以及耦合在轨道和数据补码节点QN之间的第二硬化晶体管。第一和第二硬化晶体管为数据节点Q和数据补码节点QN提供额外的驱动。门控制操作第一和第二硬化晶体管，并为SEU敏感节点提供完整的轨道驱动。

4. 发明授权

US06531905B1 Flip-flop with metastability reduction 失效
标题翻译：触发器与亚稳态减少
公开(公告)号：US06531905B1
公开(公告)日：2003-03-11
申请号：US10024816
申请日：2001-12-19
申请人： David Y. Wang
发明人： David Y. Wang
IPC分类号： H03K3037
CPC分类号： H03K3/0375
摘要： A flip-flop circuit with metastability reduction having two internal flip-flops connected in a parallel configuration relative to an input line with a input data delay connected to the data input of one of the flip-flops. The outputs are combined and since at least one of the flip-flop outputs should be stable, if the output of one of the flip-flop goes into a metastable state, the output of the other flip-flop will stabilize it, thus producing a stable output.
摘要翻译：具有亚稳态降低的触发器电路具有两个内部触发器，其以相对于输入线的并行配置连接，其输入数据延迟连接到触发器之一的数据输入。输出被组合，并且由于触发器输出中的至少一个应该是稳定的，如果触发器之一的输出进入亚稳态，则另一个触发器的输出将使其稳定，从而产生一个稳定输出。

5. 发明授权

US06492857B2 Method and apparatus for reducing the vulnerability of latches to single event upsets 失效
标题翻译：用于减少锁存器对单个事件扰乱的脆弱性的方法和装置
公开(公告)号：US06492857B2
公开(公告)日：2002-12-10
申请号：US09840684
申请日：2001-04-20
申请人： Robert L. Shuler, Jr.
发明人： Robert L. Shuler, Jr.
IPC分类号： H03K3037
CPC分类号： H03K3/356165 , H03K3/0375
摘要： A delay circuit includes a first network having an input and an output node, a second network having an input and an output, the input of the second network being coupled to the output node of the first network. The first network and the second network are configured such that: a glitch at the input to the first network having a length of approximately one-half of a standard glitch time or less does not cause the voltage at the output of the second network to cross a threshold, a glitch at the input to the first network having a length of between approximately one-half and two standard glitch times causes the voltage at the output of the second network to cross the threshold for less than the length of the glitch, and a glitch at the input to the first network having a length of greater than approximately two standard glitch times causes the voltage at the output of the second network to cross the threshold for approximately the time of the glitch. A method reduces the vulnerability of a latch to single event upsets. The latch includes a gate having an input and an output and a feedback path from the output to the input of the gate. The method includes inserting a delay into the feedback path and providing a delay in the gate.
摘要翻译：延迟电路包括具有输入和输出节点的第一网络，具有输入和输出的第二网络，第二网络的输入耦合到第一网络的输出节点。第一网络和第二网络被配置为使得在第一网络的输入处的毛刺具有标准毛刺时间或更短的大约二分之一的长度不会导致第二网络的输出处的电压交叉阈值，在第一网络的输入处的毛刺具有大约二分之二和两个标准毛刺时间之间的长度，导致第二网络的输出处的电压跨越阈值小于毛刺的长度，以及在具有大于大约两个标准毛刺时间的长度的第一网络的输入处的毛刺导致第二网络的输出处的电压在大概时间内穿过阈值。一种方法降低了锁存器的脆弱性单个事件的烦恼。锁存器包括具有输入和输出的门，以及从输出到门的输入的反馈路径。该方法包括将延迟插入反馈路径并在门中提供延迟。

6. 发明授权

US06486720B2 Flip-flop circuit arrangement with increased cut-off frequency 失效
标题翻译：触发器电路布置具有增加的截止频率
公开(公告)号：US06486720B2
公开(公告)日：2002-11-26
申请号：US09925904
申请日：2001-08-09
申请人： Reinhard Reimann
发明人： Reinhard Reimann
IPC分类号： H03K3037
CPC分类号： H03K3/012 , H03K3/2885
摘要： In a flip-flop including a control element and a holding element, in which a first current causes the control element to set a logic state and a second current causes the holding element to maintain the logic state, the cut-off frequency is increased by dimensioning the transistors of the holding element to be smaller than the transistors of the control element. In other words the transistors of the holding element have a smaller current-carrying capacity than the transistors of the control element.
摘要翻译：在包括控制元件和保持元件的触发器中，其中第一电流使控制元件设置为逻辑状态，而第二电流使保持元件保持逻辑状态，则截止频率增加将保持元件的晶体管的尺寸设定为小于控制元件的晶体管。换句话说，保持元件的晶体管具有比控制元件的晶体管更小的载流能力。

7. 发明授权

US06388488B1 Schmitt trigger with hysteresis and previous-state memory 有权
标题翻译：具有滞后和先前状态存储器的施密特触发器
公开(公告)号：US06388488B1
公开(公告)日：2002-05-14
申请号：US09704870
申请日：2000-11-02
申请人： Franklin Sai-Wai Ho
发明人： Franklin Sai-Wai Ho
IPC分类号： H03K3037
CPC分类号： H03K3/356008 , H03K3/3565
摘要： Described is a level-detection circuit having hysteresis and which may be powered down without losing the last state of the circuit. The level-detection circuit includes a first detection circuit, a trip-level adjustment circuit, and a second detection circuit. The first detection circuit may be essentially an inverter, with the output signal of the inverter fed to an input of the second detection circuit. The trip-level adjustment circuit is connected to the output signal and has control connections tied to the input signal. The trip-level adjustment circuit also includes control connections tied to the output signal of the circuit. In short, the trip-level adjustment circuit is configured such that one element of the trip-level adjustment circuit is connected in parallel with one element of the inverter of the first detection circuit when the input signal moves from a one potential to another potential. In addition, the trip-level adjustment circuit may include another element connected in parallel with another element of the inverter of the first detection circuit when the input signal moves in the opposite direction, e.g. from the other potential to the one potential. Moreover, the circuit includes latching circuitry, under control of an enable signal, configured to latch a last state of the trip-level adjustment circuit during a power-down event so that the input signal to the second detection circuit will have the same state when the circuit is powered back up.
摘要翻译：描述了具有滞后的电平检测电路，并且可以在不损失电路的最后状态的情况下断电。电平检测电路包括第一检测电路，跳闸电平调节电路和第二检测电路。第一检测电路可以基本上是逆变器，其中逆变器的输出信号被馈送到第二检测电路的输入端。跳闸电平调节电路连接到输出信号，并具有连接到输入信号的控制连接。跳闸电平调节电路还包括连接到电路的输出信号的控制连接。简而言之，当输入信号从一个电位移动到另一个电位时，跳闸电平调整电路被配置为使得跳闸电平调节电路的一个元件与第一检测电路的反相器的一个元件并联连接。此外，当输入信号沿相反方向移动时，跳闸电平调节电路可以包括与第一检测电路的反相器的另一元件并联连接的另一元件，例如，从另一个潜力到一个潜力。此外，该电路包括在使能信号的控制下的锁存电路，其被配置为在掉电事件期间锁存跳闸电平调整电路的最后状态，使得到第二检测电路的输入信号将具有相同的状态电路通电。

8. 发明授权

US06339352B1 Anticipatory Schmitt trigger 有权
标题翻译：预期施密特触发器
公开(公告)号：US06339352B1
公开(公告)日：2002-01-15
申请号：US09810662
申请日：2001-03-19
申请人： Muhammet Cosan , Harold R. Schnetzka
发明人： Muhammet Cosan , Harold R. Schnetzka
IPC分类号： H03K3037
CPC分类号： H03K3/0377
摘要： A system and method for providing an anticipatory Schmitt trigger circuit that changes the output level of the trigger circuit in anticipation of crossing a predetermined voltage value such as a zero voltage level. In an exemplary embodiment, the anticipatory Schmitt trigger includes a comparator, a feedback resistor, an input resistor, a pull-up resistor, a plurality of voltage divider resistors, and a capacitor.
摘要翻译：一种用于提供预期的施密特触发电路的系统和方法，该电路改变触发电路的输出电平，以预期跨越诸如零电压电平的预定电压值。在示例性实施例中，预期施密特触发器包括比较器，反馈电阻器，输入电阻器，上拉电阻器，多个分压器电阻器和电容器。

9. 发明授权

US06204707B1 Flip-flop circuit with clock signal control function and clock control circuit 有权
标题翻译：触发电路具有时钟信号控制功能和时钟控制电路
公开(公告)号：US06204707B1
公开(公告)日：2001-03-20
申请号：US09383880
申请日：1999-08-26
申请人： Mototsugu Hamada , Tadahiro Kuroda
发明人： Mototsugu Hamada , Tadahiro Kuroda
IPC分类号： H03K3037
CPC分类号： H03K3/0375 , H03K3/012
摘要： A flip-flop circuit 10 is provided with a discord detecting circuit DDC and a clock control circuit CCC. The discord detecting circuit DDC detects the discord of a data input signal DIS of the flip-flop circuit 10 with a data output signal DOS thereof. When the data input signal DIS discords with the data output signal DOS, the clock control circuit CCC supplies a short pulse to the flip-flop circuit 10 as an internal clock signal ICLK in synchronism with the rising of an external clock signal ECLK. On the other hand, when the data input signal DIS coincides with the data output signal DOS, the clock control circuit CCC supplies a low level signal to the flip-flop circuit 10 as the internal clock signal ICLK. Thus, it is possible to suppress electric power consumption required to supply a clock signal, and to prevent errors from being caused in a flip-flop operation.
摘要翻译：触发电路10具有不对称检测电路DDC和时钟控制电路CCC。不对称检测电路DDC利用其数据输出信号DOS检测触发器电路10的数据输入信号DIS的不一致。当数据输入信号DIS与数据输出信号DOS不一致时，时钟控制电路CCC与外部时钟信号ECLK的上升同步地作为内部时钟信号ICLK向触发器电路10提供短脉冲。另一方面，当数据输入信号DIS与数据输出信号DOS一致时，时钟控制电路CCC将作为内部时钟信号ICLK的低电平信号提供给触发器电路10。因此，可以抑制提供时钟信号所需的电力消耗，并且防止在触发器操作中引起错误。

10. 发明授权

US06741112B2 Input circuit with hysteresis 失效
标题翻译：具有滞后的输入电路
公开(公告)号：US06741112B2
公开(公告)日：2004-05-25
申请号：US10255577
申请日：2002-09-27
申请人： Janardhanan S. Ajit
发明人： Janardhanan S. Ajit
IPC分类号： H03K3037
CPC分类号： H03K3/356113 , H03K3/013 , H03K3/3565
摘要： An input circuit has hysteresis to mitigate the effects of input noise. The input circuit receives an analog input signal and determines whether the unregulated analog input signal is a high or a low voltage. The input circuit outputs a regulated low voltage (i.e., “0”) for a low input signal, and outputs a regulated high voltage (i.e., “1”) for a high input signal. The low-to-high transition occurs at a higher voltage than a high-to-low transition, which mitigates noise on the input signal. Furthermore, the comparator includes a feedback path from an output of the comparator to an input of the comparator. The feedback path causes some delay in any output voltage transition (i.e. high-to-low output transition or low-to-high transition), which further enhances the hystersis effect and improves noise immunity. An embodiment of the circuit interfaces with high voltage (e.g., 5V) input signals and outputs low voltage (e.g., 1.2V) output signals. In other words, the input circuit also provides a voltage transition while detecting the low-to-high and high-to-low transitions.
摘要翻译：输入电路具有迟滞以减轻输入噪声的影响。输入电路接收模拟输入信号，并确定未调节的模拟输入信号是高电平还是低电压。输入电路为低输入信号输出稳定的低电压（即“0”），并输出用于高输入信号的调节高电压（即“1”）。低电平到高电平的转换发生在高于高电平转换的电压上，这降低了输入信号的噪声。此外，比较器包括从比较器的输出到比较器的输入的反馈路径。反馈路径在任何输出电压转换（即从高到低输出转换或低到高转换）中都会产生一些延迟，这进一步增强了后门槛效应并提高了噪声抗扰度。电路的一个实施例与高电压（例如5V）输入信号接口并输出低电压（例如，1.2V）输出信号。换句话说，输入电路还提供电压转换，同时检测从低到高和从高到低的转变。

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