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1. 发明授权

US07322015B2 Simulating a dose rate event in a circuit design 有权
标题翻译：模拟电路设计中的剂量率事件
公开(公告)号：US07322015B2
公开(公告)日：2008-01-22
申请号：US11029308
申请日：2005-01-05
申请人： Harry H. L. Liu , Keith W. Golke , Eric E. Vogt , Michael S. Liu
发明人： Harry H. L. Liu , Keith W. Golke , Eric E. Vogt , Michael S. Liu
IPC分类号： G06F17/50 , G06G7/62
CPC分类号： G06F17/5036
摘要： Behaviors of a transistor during a dose rate event can be modeled using a circuit simulation software package. A subcircuit model replaces a transistor in a circuit design to be simulated. The subcircuit model can be in the form of a schematic-based representation or a netlist. The subcircuit model provides a model of a source junction and a drain junction in the transistor during the dose rate event. The subcircuit model also includes the size of the transistor being replaced and the dose rate of the dose rate event. Once the transistor is replaced with the subcircuit model, a dose rate simulation may be performed to determine the dose rate hardness of the circuit design.
摘要翻译：在剂量率事件期间晶体管的行为可以使用电路仿真软件包进行建模。子电路模型取代要仿真的电路设计中的晶体管。子电路模型可以是基于原理图的表示形式或网表。子电路模型在剂量率事件期间提供晶体管中的源极结和漏极结的模型。子电路模型还包括被替换的晶体管的尺寸和剂量率事件的剂量率。一旦晶体管被子电路模型替代，可以执行剂量率模拟来确定电路设计的剂量率硬度。

2. 发明授权

US07286393B2 System and method for hardening MRAM bits 有权
标题翻译：用于硬化MRAM位的系统和方法
公开(公告)号：US07286393B2
公开(公告)日：2007-10-23
申请号：US11096179
申请日：2005-03-31
申请人： Owen J. Hynes , Romney Katti , Harry H. L. Liu , Michael S. Liu
发明人： Owen J. Hynes , Romney Katti , Harry H. L. Liu , Michael S. Liu
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： A device is connected in parallel with an MTJ structure of an MRAM bit to shunt photocurrent away from and/or limit voltage across the MTJ structure during a dose rate event. The device may include at least one transistor and/or at least one diode. One device may be used to protect an entire row and/or column of MRAM bits. As a result, the MRAM bits are protected during a dose rate event.
摘要翻译：器件与MRAM位的MTJ结构并联连接，以在剂量率事件期间跨越MTJ结构分流光电流和/或限制跨越MTJ结构的电压。该器件可以包括至少一个晶体管和/或至少一个二极管。一个设备可用于保护MRAM位的整个行和/或列。结果，在剂量率事件期间MRAM位被保护。

3. 发明授权

US06775178B2 SEU resistant SRAM using feedback MOSFET 有权
标题翻译：使用反馈MOSFET的SEU抗静电SRAM
公开(公告)号：US06775178B2
公开(公告)日：2004-08-10
申请号：US10116296
申请日：2002-04-04
申请人： Michael S. Liu , Shankar P. Sinha
发明人： Michael S. Liu , Shankar P. Sinha
IPC分类号： G11C1100
CPC分类号： G11C11/4125
摘要： A random access memory cell has first and second inverters each having an input and an output. The input of the first inverter is coupled to the output of the second inverter by a Schottky-diode-free MOSFET. The input of the second inverter is coupled to the output of the first inverter.
摘要翻译：随机存取存储器单元具有每个具有输入和输出的第一和第二反相器。第一反相器的输入通过肖特基二极管的MOSFET耦合到第二反相器的输出。第二反相器的输入耦合到第一反相器的输出端。

4. 发明授权

US5344524A SOI substrate fabrication 失效
标题翻译： SOI衬底制造
公开(公告)号：US5344524A
公开(公告)日：1994-09-06
申请号：US85422
申请日：1993-06-30
申请人： Kalluri R. Sharma , Michael S. Liu
发明人： Kalluri R. Sharma , Michael S. Liu
IPC分类号： H01L27/12 , H01L21/02 , H01L21/20 , H01L21/3065 , H01L21/762 , H01L21/306
CPC分类号： H01L21/76264 , H01L21/2007 , H01L21/3065 , H01L21/76256 , H01L21/76275 , H01L21/76283 , H01L21/76289 , Y10S148/012 , Y10S438/97
摘要： A back-etch silicon-on-insulator SOI process that has a silicon handle wafer with an oxide layer bonded at room temperature to a silicon device wafer with an etch stop and silicon device layer. The surfaces that are bonded at room temperature are first conditioned to be hydrophilic. After bonding, the edges of the layers are sealed. The silicon device wafer, the etch-stop layer and the device layer are boron doped. Most of the silicon device wafer is ground away. Then, the remaining portion of the silicon device wafer and the etch stop layer are chemically etched away, thereby leaving a uniform layer of silicon device layer on the oxide layer of the silicon handle wafer. Because the bonding, grinding and selective etching are performed at room temperature, inter-diffusion of the boron between the various layers is prevented and thus permits the selective etching process to result in a nearly perfect silicon device layer in terms of an even-surfaced, defect-free and thin layer on the buried oxide layer of silicon handle wafer. The resulting SOI wafer is then annealed at a high temperature, prior to device processing.
摘要翻译：背面蚀刻绝缘体上硅SOI工艺，其具有硅处理晶片，其氧化物层在室温下与蚀刻停止和硅器件层结合到硅器件晶片。首先将在室温下结合的表面调节为亲水性。粘合后，层的边缘被密封。硅器件晶片，蚀刻停止层和器件层是硼掺杂的。大多数硅器件晶片被磨掉。然后，硅器件晶片和蚀刻停止层的剩余部分被化学蚀刻掉，从而在硅处理晶片的氧化物层上留下均匀的硅器件层层。由于在室温下进行接合，研磨和选择性蚀刻，因此可以防止各层之间的硼的相互扩散，从而允许选择性蚀刻工艺在均匀表面，在硅处理晶圆的掩埋氧化层上的无缺陷和薄层。然后在器件处理之前，将所得的SOI晶片在高温下退火。

5. 发明授权

US5212108A Fabrication of stabilized polysilicon resistors for SEU control 失效
标题翻译：用于SEU控制的稳定多晶硅电阻器的制造
公开(公告)号：US5212108A
公开(公告)日：1993-05-18
申请号：US807307
申请日：1991-12-13
申请人： Michael S. Liu , Gordon A. Shaw , Jerry Yue
发明人： Michael S. Liu , Gordon A. Shaw , Jerry Yue
IPC分类号： H01L21/02 , H01L21/3215 , H01L27/11
CPC分类号： H01L28/20 , H01L21/32155 , H01L27/1112
摘要： A method for fabricating polysilicon resistors of intermediate high value for use as cross-coupling or =ingle event upset (SEU) resistors in memory cells. A thin polysilicon film is implanted with arsenic ions to produce a predetermined resistivity. The thin film is then implanted with fluorine ions to stabilize the grain boundaries and thereby the barrier height. Reducing the variation in barrier height from run to run of wafers allows the fabrication of reproducible SEU resistors.
摘要翻译：一种用于制造中间值高的多晶硅电阻器的方法，用作存储器单元中的交叉耦合或单个事件镦粗（SEU）电阻器。用砷离子注入薄的多晶硅膜以产生预定的电阻率。然后用氟离子注入薄膜以稳定晶界，从而稳定势垒高度。降低栅极高度从运行到晶圆运行的变化允许制造可再现的SEU电阻器。

6. 发明授权

US5925915A Semiconductor on insulator devices 失效
标题翻译：半导体绝缘体器件
公开(公告)号：US5925915A
公开(公告)日：1999-07-20
申请号：US251011
申请日：1994-05-31
申请人： Michael S. Liu , James C. Lai
发明人： Michael S. Liu , James C. Lai
IPC分类号： H01L27/12 , H01L27/01 , H01L29/76
CPC分类号： H01L27/1203
摘要： A pair of complementary MOSFET's having regions of a common conductivity type separating the source and drain regions thereof which are provided on a support structure formed of an electrical insulating layer on a semiconductor material base. MOSFET's has a gate oxide layer on which is provided a gate semiconductor structure, with these structures each being of a common conductivity type and located across the gate oxide layers from the corresponding common conductivity type region.
摘要翻译：一对互补MOSFET，其具有分开其源极和漏极区域的共同导电类型的区域，其设置在由半导体材料基底上的电绝缘层形成的支撑结构上。 MOSFET具有栅极氧化层，在栅极氧化物层上设置栅极半导体结构，这些结构各自具有公共导电类型，并且从相应的公共导电类型区域跨越栅极氧化物层。

7. 发明授权

US4551394A Integrated three-dimensional localized epitaxial growth of Si with localized overgrowth of GaAs 失效
标题翻译： Si的集成三维局部外延生长与GaAs的局部过度生长
公开(公告)号：US4551394A
公开(公告)日：1985-11-05
申请号：US674903
申请日：1984-11-26
申请人： Regis J. Betsch , Michael S. Liu , Obert N. Tufte
发明人： Regis J. Betsch , Michael S. Liu , Obert N. Tufte
IPC分类号： H01L21/20 , H01L21/205 , H01L21/822 , H01L21/8252 , H01L29/267
CPC分类号： H01L29/267 , H01L21/02381 , H01L21/0245 , H01L21/02502 , H01L21/02546 , H01L21/02639 , H01L21/02647 , H01L21/8221 , H01L21/8252 , Y10S148/026 , Y10S148/059 , Y10S148/072 , Y10S148/084 , Y10S438/933 , Y10T428/12674 , Y10T428/12681
摘要： Localized epitaxial growth of GaAs from a silicon monocrystalline substrate to provide a three-dimensional Si-GaAs structure and method. The silicon has an insulating layer deposited thereover and a window is opened through the layer to expose a small area of the underlying silicon from which silicon is epitaxially grown until the window is nearly full whereupon a thin buffer layer such as germanium is epitaxially grown over the epi-silicon to fill the window. Al.sub.x Ga.sub.1-x As (where x.gtoreq.0) is then locally epitaxially grown from the buffer layer and it grows laterally as well as vertically to cover the surrounding insulating layer surface and provide a site for high frequency electronics.
摘要翻译：从硅单晶衬底的GaAs的局部外延生长提供三维Si-GaAs结构和方法。该硅具有沉积在其上的绝缘层，并且通过该层开放窗口以暴露硅外延生长直到窗口几乎完整的下面的硅的小区域，于是在诸如锗之类的薄缓冲层如外延生长外延硅填充窗口。 Al x Ga 1-x As（其中x> / = 0）然后从缓冲层局部外延生长，并且其横向和垂直生长以覆盖周围的绝缘层表面并提供用于高频电子器件的部位。

8. 发明授权

US07679139B2 Non-planar silicon-on-insulator device that includes an “area-efficient” body tie 有权
标题翻译：非平面绝缘体上硅器件，其包括“区域高效”的身体系带
公开(公告)号：US07679139B2
公开(公告)日：2010-03-16
申请号：US11853611
申请日：2007-09-11
申请人： Bradley J. Larsen , Michael S. Liu , Paul S. Fechner
发明人： Bradley J. Larsen , Michael S. Liu , Paul S. Fechner
IPC分类号： H01L29/786
CPC分类号： H01L29/7853 , H01L29/66795 , H01L29/78615
摘要： Non-planar SOI devices that include an “area-efficient” body tie are disclosed. The device includes a bulk substrate, an insulator layer formed on a surface of the bulk substrate, and a silicon body formed on a surface of the insulator layer. The silicon body preferably includes (i) a non-planar channel connecting a source region and a drain region, and (ii) a body tie that is adjacent to the channel and couples the channel to a voltage potential. The device further includes a gate dielectric formed on the channel and a gate material formed on the gate dielectric.
摘要翻译：公开了包括“面积效率”的身体搭接的非平面SOI器件。该器件包括体基片，形成在本体基片的表面上的绝缘体层，以及形成在绝缘体层的表面上的硅体。硅体优选地包括（i）连接源极区域和漏极区域的非平面沟道，以及（ii）与沟道相邻并且将沟道耦合到电压电位的主体连接。该器件还包括形成在沟道上的栅极电介质和形成在栅极电介质上的栅极材料。

9. 发明授权

US5659192A SOI substrate fabrication 失效
标题翻译： SOI衬底制造
公开(公告)号：US5659192A
公开(公告)日：1997-08-19
申请号：US791354
申请日：1997-01-27
申请人： Kalluri R. Sarma , Michael S. Liu
发明人： Kalluri R. Sarma , Michael S. Liu
IPC分类号： H01L21/20 , H01L21/762 , H01L27/01 , H01L27/12 , H01L29/04 , H01L31/0392
CPC分类号： H01L21/76256 , H01L21/2007 , H01L21/76264 , H01L21/76275 , H01L21/76283 , H01L21/76289
摘要： A back-etch silicon-on-insulator SOI process that has a silicon handle wafer with an oxide layer bonded at room temperature to a silicon device wafer with an etch stop and silicon device layer. The surfaces that are bonded at room temperature are first conditioned to be hydrophilic. After bonding, the edges of the layers are sealed. The silicon device wafer, the etch-stop layer and the device layer are boron doped. Most of the silicon device wafer is ground away. Then, the remaining portion of the silicon device wafer and the etch stop layer are chemically etched away, thereby leaving a uniform layer of silicon device layer on the oxide layer of the silicon handle wafer. Because the bonding, grinding and selective etching are performed at room temperature, inter-diffusion of the boron between the various layers is prevented and thus permits the selective etching process to result in a nearly perfect silicon device layer in terms of an even-surfaced, defect-free and thin layer on the buried oxide layer of silicon handle wafer. The resulting SOI wafer is then annealed at a high temperature, prior to device processing.
摘要翻译：背面蚀刻绝缘体上硅SOI工艺，其具有硅处理晶片，其氧化物层在室温下与蚀刻停止和硅器件层结合到硅器件晶片。首先将在室温下结合的表面调节为亲水性。粘合后，层的边缘被密封。硅器件晶片，蚀刻停止层和器件层是硼掺杂的。大多数硅器件晶片被磨掉。然后，硅器件晶片和蚀刻停止层的剩余部分被化学蚀刻掉，从而在硅处理晶片的氧化物层上留下均匀的硅器件层层。由于在室温下进行接合，研磨和选择性蚀刻，因此可以防止各层之间的硼的相互扩散，从而允许选择性蚀刻工艺在均匀表面，在硅处理晶圆的掩埋氧化层上的无缺陷和薄层。然后在器件处理之前，将所得的SOI晶片在高温下退火。

10. 发明授权

US5429981A Method of making linear capacitors for high temperature applications 失效
标题翻译：制造高温应用的线性电容器的方法
公开(公告)号：US5429981A
公开(公告)日：1995-07-04
申请号：US269265
申请日：1994-06-30
申请人： Gary R. Gardner , Michael S. Liu
发明人： Gary R. Gardner , Michael S. Liu
IPC分类号： H01L21/02 , H01L21/84 , H01L21/70
CPC分类号： H01L28/40 , H01L21/84
摘要： A method for making a voltage linear capacitor for use with a metal oxide semiconductor field transistor wherein a capacitor portion of an SOI substrate is heavily doped with phosphorus. The thin oxide layer used for the transistor gate oxide also serves as the capacitor dielectric and the thickness of the dielectric relative to the gate oxide is controlled.
摘要翻译：一种用于与金属氧化物半导体场晶体管一起使用的电压线性电容器的方法，其中SOI衬底的电容器部分被磷重掺杂。用于晶体管栅极氧化物的薄氧化物层也用作电容器电介质，并且控制电介质相对于栅极氧化物的厚度。

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