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1. 发明授权

US07693001B2 SRAM split write control for a delay element 有权
标题翻译：用于延迟元件的SRAM分离写入控制
公开(公告)号：US07693001B2
公开(公告)日：2010-04-06
申请号：US12013856
申请日：2008-01-14
申请人： Keith W. Golke , Harry H L Liu , David K. Nelson
发明人： Keith W. Golke , Harry H L Liu , David K. Nelson
IPC分类号： G11C8/00
CPC分类号： G11C7/02 , G11C5/005 , G11C8/14 , G11C11/4125
摘要： A Static Random Access Memory (SRAM) having a split write control is described. The SRAM includes bit, write, and write-word lines. Each memory cell within the SRAM includes a delay which is coupled to a dedicated write-word line. When a cell is not being written, its delay receives a delay signal on its associated write-word line, which increases the response time of the cell. When a cell is to be written, however, its delay receives a bypass signal on its associated write-word line, which decreases the response time of the SRAM cell.
摘要翻译：描述具有分离写入控制的静态随机存取存储器（SRAM）。 SRAM包括位，写和写字线。 SRAM内的每个存储单元包括耦合到专用写字线的延迟。当单元未被写入时，其延迟在其相关联的写字线上接收延迟信号，这增加了单元的响应时间。然而，当单元被写入时，其延迟在其相关的写字线上接收旁路信号，这降低了SRAM单元的响应时间。

2. 发明授权

US06909637B2 Full rail drive enhancement to differential SEU hardening circuit while loading data 有权
标题翻译：在加载数据时，全速驱动增强到差分SEU硬化电路
公开(公告)号：US06909637B2
公开(公告)日：2005-06-21
申请号：US10306465
申请日：2002-11-27
申请人： David K. Nelson , Keith W. Golke
发明人： David K. Nelson , Keith W. Golke
IPC分类号： G11C5/00 , G11C11/00 , G11C11/412 , G11C16/04 , H03K3/00
CPC分类号： G11C5/005
摘要： A hardening system includes a data storage device having a data input, a clock input, a data node Q, and a data complement node QN. The data storage device provides drive to the data node Q and the data complement node QN. A hardening circuit includes first, second, third, fourth, and fifth transistor circuits. The first and second transistor circuits form a first node therebetween, and the first transistor circuit prevents the data node Q from changing states in the presence of radiation. The third and fourth transistor circuits form a second node therebetween, and the third transistor circuit prevents the data complement node QN from changing states in the presence of radiation. The first node is coupled to the third transistor circuit, and the second node is coupled to the first transistor circuit. The fifth transistor circuit prevents the first and second nodes from floating.
摘要翻译：硬化系统包括具有数据输入，时钟输入，数据节点Q和数据补码节点QN的数据存储装置。数据存储设备向数据节点Q和数据补码节点QN提供驱动。硬化电路包括第一，第二，第三，第四和第五晶体管电路。第一和第二晶体管电路在它们之间形成第一节点，并且第一晶体管电路防止数据节点Q在存在辐射的情况下改变状态。第三和第四晶体管电路在其间形成第二节点，并且第三晶体管电路防止数据补码节点QN在存在辐射的情况下改变状态。第一节点耦合到第三晶体管电路，第二节点耦合到第一晶体管电路。第五晶体管电路防止第一和第二节点浮动。

3. 发明授权

US08963590B2 Power cycling power on reset circuit for fuse initialization circuitry 有权
标题翻译：保险丝初始化电路的电源循环电源复位电路
公开(公告)号：US08963590B2
公开(公告)日：2015-02-24
申请号：US12424446
申请日：2009-04-15
申请人： Joe G. Guimont , David K. Nelson , Walter W. Heikkila , Anuj Kohli
发明人： Joe G. Guimont , David K. Nelson , Walter W. Heikkila , Anuj Kohli
IPC分类号： H03L7/00 , H03K3/02 , H03K17/04 , H03K17/22
CPC分类号： H03K17/223
摘要： A system for initializing circuitry is presented. The system employs a power-on reset circuit having a threshold voltage and a programmable switch circuit. The power-on reset circuit has a detector circuit for detecting a reference voltage, and a one-sided latch for generating an output voltage reflective of the reference voltage. The detector circuit has a threshold after which the one-sided latch is activated. The programmable switch circuit receives the output voltage of the power-on reset circuit and generates an enable signal and its complement based on the status of an internal fuse. The switch point of the power-on reset circuit provides for a rapid increase in output voltage that offsets parasitic leakage current in the programmable switch circuit that can result in improper enable signal output. A high resistance direct path to ground on an output node of the power-on reset circuit prevents residual charge from causing an undesired misfire.
摘要翻译：提出了一种用于初始化电路的系统。该系统采用具有阈值电压和可编程开关电路的上电复位电路。上电复位电路具有用于检测参考电压的检测器电路和用于产生反映参考电压的输出电压的单侧锁存器。检测器电路具有阈值，之后单侧锁存器被激活。可编程开关电路接收上电复位电路的输出电压，并根据内部保险丝的状态产生使能信号及其补码。上电复位电路的开关点提供输出电压的快速增加，以抵消可编程开关电路中的寄生漏电流，这可能导致不正确的使能信号输出。在电源复位电路的输出节点上的高电阻直接接地路径可防止剩余电荷引起不期望的失火。

4. 发明申请

US20080309384A1 Initialization Circuitry Having Fuse Leakage Current Tolerance 审中-公开
标题翻译：具有保险丝泄漏电流公差的初始化电路
公开(公告)号：US20080309384A1
公开(公告)日：2008-12-18
申请号：US11762317
申请日：2007-06-13
申请人： Joe G. Guimont , David K. Nelson , Walter W. Heikkila , Anuj Kohli
发明人： Joe G. Guimont , David K. Nelson , Walter W. Heikkila , Anuj Kohli
IPC分类号： H03L7/00
CPC分类号： H03K17/223 , G06F1/24
摘要： A system for initializing circuitry is presented. The system employs a power-on reset circuit having a threshold voltage and a programmable switch circuit. The power-on reset circuit has a detector circuit for detecting a reference voltage, and a one-sided latch for generating an output voltage reflective of the reference voltage. The detector circuit has a threshold after which the one-sided latch is activated. The programmable switch circuit receives the output voltage of the power-on reset circuit and generates an enable signal arid its complement based on the status of an internal fuse. The switch point of the power-on reset circuit provides for a rapid increase in output voltage, offsetting parasitic leakage current in the programmable switch circuit that can result in improper enable signal output.
摘要翻译：提出了一种用于初始化电路的系统。该系统采用具有阈值电压和可编程开关电路的上电复位电路。上电复位电路具有用于检测参考电压的检测器电路和用于产生反映参考电压的输出电压的单侧锁存器。检测器电路具有阈值，之后单侧锁存器被激活。可编程开关电路接收上电复位电路的输出电压，并根据内部保险丝的状态产生使能信号和补码。上电复位电路的开关点提供输出电压的快速增加，抵消可编程开关电路中的寄生漏电流，从而导致不正确的使能信号输出。

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