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1. 发明申请

US20050145908A1 High polarization ferroelectric capacitors for integrated circuits 审中-公开
标题翻译：用于集成电路的高极化铁电电容器
公开(公告)号：US20050145908A1
公开(公告)日：2005-07-07
申请号：US10749668
申请日：2003-12-30
申请人： Theodore Moise , Scott Summerfelt , K.R. Udayakumar
发明人： Theodore Moise , Scott Summerfelt , K.R. Udayakumar
IPC分类号： H01L21/02 , H01L21/8246 , H01L27/115 , H01L21/00 , H01L29/76
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55
摘要： One aspect of the invention relates to a method of manufacturing an integrated circuit comprising forming an array of ferroelectric memory cells on a semiconductor substrate, heating the substrate to a temperature near a Curie temperature of the ferroelectric cores, and subjecting the substrate to a temperature program, whereby thermally induced stresses on the ferroelectric cores cause a switched polarization of the cores to increase by at least about 25% as the cores cool to about room temperature. Embodiments of the invention include metal filled vias of expanded cross-section above and below the ferroelectric cores, which increase the thermal stresses on the ferroelectic cores during cooling.
摘要翻译：本发明的一个方面涉及一种制造集成电路的方法，包括在半导体衬底上形成铁电存储器单元的阵列，将衬底加热到铁电芯的居里温度附近的温度，并对衬底进行温度程序，由此当铁芯冷却至约室温时，铁电芯上的热诱导应力使芯的开关极化增加至少约25％。本发明的实施例包括在铁电芯上方和下方的膨胀横截面的金属填充通孔，其在冷却期间增加铁电芯上的热应力。

2. 发明申请

US20050112898A1 Method for etching a substrate and a device formed using the method 有权
标题翻译：用于蚀刻基板的方法和使用该方法形成的器件
公开(公告)号：US20050112898A1
公开(公告)日：2005-05-26
申请号：US10721932
申请日：2003-11-25
申请人： K.R. Udayakumar , Ted Moise , Scott Summerfelt , Martin Albrecht , William Dostalik , Francis Celii
发明人： K.R. Udayakumar , Ted Moise , Scott Summerfelt , Martin Albrecht , William Dostalik , Francis Celii
IPC分类号： H01L21/02 , H01L21/311 , H01L21/316 , H01L21/768 , H01L21/302 , H01L21/461
CPC分类号： H01L21/31116 , H01L21/31616 , H01L21/76895 , H01L28/55
摘要： The present invention provides a method for etching a substrate, a method for forming an integrated circuit, an integrated circuit formed using the method, and an integrated circuit. The method for etching a substrate includes, among other steps, providing a substrate 140 having an aluminum oxide etch stop layer 130 located thereunder, and then etching an opening 150, 155, in the substrate 140 using an etchant comprising carbon oxide, a fluorocarbon, an etch rate modulator, and an inert carrier gas, wherein a flow rate of the carbon oxide is greater than about 80 sccm and the etchant is selective to the aluminum oxide etch stop layer 130. The aluminum oxide etch stop layer may also be used in the back-end of advanced CMOS processes as a via etch stop layer.
摘要翻译：本发明提供了蚀刻基板的方法，集成电路的形成方法，使用该方法形成的集成电路和集成电路。除了其他步骤之外，用于蚀刻衬底的方法包括提供具有位于其下方的氧化铝蚀刻停止层130的衬底140，然后使用包含碳氧化物，碳氟化合物的蚀刻剂在衬底140中蚀刻开口150,155，蚀刻速率调制器和惰性载气，其中碳氧化物的流速大于约80sccm，并且蚀刻剂对氧化铝蚀刻停止层130是选择性的。氧化铝蚀刻停止层也可用作先进CMOS工艺的后端作为通孔蚀刻停止层。

3. 发明申请

US20050230725A1 Ferroelectric capacitor having an oxide electrode template and a method of manufacture therefor 审中-公开
标题翻译：具有氧化物电极模板的铁电电容器及其制造方法
公开(公告)号：US20050230725A1
公开(公告)日：2005-10-20
申请号：US10828446
申请日：2004-04-20
申请人： Sanjeev Aggarwal , K.R. Udayakumar , Scott Summerfelt
发明人： Sanjeev Aggarwal , K.R. Udayakumar , Scott Summerfelt
IPC分类号： H01L21/00 , H01L21/02 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/57 , H01L28/65 , H01L28/75
摘要： The present invention provides a ferroelectric capacitor, a method for manufacture therefor, and a ferroelectric random access memory (FeRAM) device. The ferroelectric capacitor (100), among other elements, may include a first electrode layer (162) located over a substrate (110), wherein the first electrode layer (162) includes iridium, and an oxide electrode template (164) located over the first electrode layer (162). The ferroelectric capacitor (100) may further include a ferroelectric dielectric layer (165) located over the oxide electrode template (164), and a second electrode layer (170) located over the ferroelectric dielectric layer (165).
摘要翻译：本发明提供一种铁电电容器及其制造方法以及铁电随机存取存储器（FeRAM）器件。铁电电容器（100）以及其他元件可以包括位于基板（110）上方的第一电极层（162），其中第一电极层（162）包括铱，以及氧化物电极模板（164）第一电极层（162）。铁电电容器（100）还可以包括位于氧化物电极模板（164）上方的铁电介质层（165）和位于铁电介质层（165）上方的第二电极层（170）。

4. 发明申请

US20050227378A1 Integrated circuit and method 有权
公开(公告)号：US20050227378A1
公开(公告)日：2005-10-13
申请号：US11145663
申请日：2005-06-06
申请人： Theodore Moise , Guoqiang Xing , Mark Visokay , Justin Gaynor , Stephen Gilbert , Francis Celii , Scott Summerfelt , Luigi Colombo
发明人： Theodore Moise , Guoqiang Xing , Mark Visokay , Justin Gaynor , Stephen Gilbert , Francis Celii , Scott Summerfelt , Luigi Colombo
IPC分类号： H01L21/02 , H01L21/311 , H01L21/768 , H01L21/8242 , H01L21/8246 , H01L27/108 , H01L27/115
CPC分类号： H01L27/11502 , H01L21/31116 , H01L21/76895 , H01L27/10811 , H01L27/10814 , H01L27/10852 , H01L27/11507 , H01L28/55
摘要： A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.

5. 发明申请

US20050205911A1 Ferroelectric capacitor hydrogen barriers and methods for fabricating the same 有权
标题翻译：铁电电容器氢屏障及其制造方法
公开(公告)号：US20050205911A1
公开(公告)日：2005-09-22
申请号：US11033224
申请日：2005-01-11
申请人： K. Udayakumar , Theodore Moise , Scott Summerfelt
发明人： K. Udayakumar , Theodore Moise , Scott Summerfelt
IPC分类号： H01L27/105 , H01L21/02 , H01L21/8246 , H01L29/76 , H01L29/94
CPC分类号： H01L27/11507 , H01L28/57
摘要： Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (CFE) from hydrogen diffusion in semiconductor devices (102), wherein nitrided aluminum oxide (N—AlOx) is formed over a ferroelectric capacitor (CFE), and one or more silicon nitride layers (112, 117) are formed over the nitrided aluminum oxide (N—AlOx). Hydrogen barriers are also provided in which an aluminum oxide (AlOx, N—AlOx) is formed over the ferroelectric capacitors (CFE), with two or more silicon nitride layers (112, 117) formed over the aluminum oxide (AlOx, N—AlOx), wherein the second silicon nitride layer (112) comprises a low silicon-hydrogen SiN material.
摘要翻译：提供氢屏障和制造方法用于在半导体器件（102）中保护铁电电容器（C LIMIT）免受氢扩散，其中氮化的氧化铝（N-AlOx）形成在铁电电容器（C < 在氮化的氧化铝（N-AlOx）上形成一个或多个氮化硅层（112,117）。还提供了氢屏障，其中在铁电电容器（CFE）上形成氧化铝（AlOx，N-AlOx），其上形成有两个或更多个氮化硅层（112,117）氧化铝（AlOx，N-AlOx），其中第二氮化硅层（112）包括低硅氢SiN材料。

6. 发明申请

US20050032301A1 Low silicon-hydrogen sin layer to inhibit hydrogen related degradation in semiconductor devices having ferroelectric components 有权
标题翻译：低硅氢层，用于抑制具有铁电元件的半导体器件中的氢相关退化
公开(公告)号：US20050032301A1
公开(公告)日：2005-02-10
申请号：US10635994
申请日：2003-08-07
申请人： K. Udayakumar , Maritin Albrecht , Theodore Moise , Scott Summerfelt , Sarah Hartwig
发明人： K. Udayakumar , Maritin Albrecht , Theodore Moise , Scott Summerfelt , Sarah Hartwig
IPC分类号： H01L21/02 , H01L21/318 , H01L21/768 , H01L21/8246 , H01L27/115 , H01L21/8242 , H01L21/31 , H01L21/00 , H01L21/469
CPC分类号： H01L21/76829 , H01L21/3185 , H01L21/76828 , H01L21/76832 , H01L21/76834 , H01L27/11502 , H01L27/11507 , H01L28/57
摘要： Semiconductor devices and fabrication methods are disclosed, in which one or more low silicon-hydrogen SiN barriers are provided to inhibit hydrogen diffusion into ferroelectric capacitors and into transistor gate dielectric interface areas. The barriers may be used as etch stop layers in various levels of the semiconductor device structure above and/or below the level at which the ferroelectric capacitors are formed so as to reduce the hydrogen related degradation of the switched polarization properties of the ferroelectric capacitors and to reduce negative bias temperature instability in the device transistors.
摘要翻译：公开了半导体器件和制造方法，其中提供一个或多个低硅氢SiN栅极以阻止氢扩散到铁电电容器中并进入晶体管栅极电介质界面区域。可以将阻挡层用作在形成强电介质电容器的电平以上和/或以下的半导体器件结构的各种级别的蚀刻停止层，以便降低铁电电容器的开关极化特性的氢相关劣化，并且降低器件晶体管的负偏压温度不稳定性。

7. 发明申请

US20050205906A1 FERROELECTRIC CAPACITOR HYDROGEN BARRIERS AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：电磁电容器氢气阻隔器及其制造方法
公开(公告)号：US20050205906A1
公开(公告)日：2005-09-22
申请号：US10803445
申请日：2004-03-18
申请人： K. Udayakumar , Theodore Moise , Scott Summerfelt
发明人： K. Udayakumar , Theodore Moise , Scott Summerfelt
IPC分类号： H01L27/105 , H01L21/02 , H01L21/8246 , H01L29/76 , H01L29/94
CPC分类号： H01L27/11507 , H01L28/57
摘要： Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (CFE) from hydrogen diffusion in semiconductor devices (102), wherein nitrided aluminum oxide (N—AlOx) is formed over a ferroelectric capacitor (CFE), and one or more silicon nitride layers (112, 117) are formed over the nitrided aluminum oxide (N—AlOx). Hydrogen barriers are also provided in which an aluminum oxide (AlOx, N—AlOx) is formed over the ferroelectric capacitors (CFE), with two or more silicon nitride layers (112, 117) formed over the aluminum oxide (AlOx, N—AlOx), wherein the second silicon nitride layer (112) comprises a low silicon-hydrogen SiN material.
摘要翻译：提供氢屏障和制造方法用于在半导体器件（102）中保护铁电电容器（C LIMIT）免受氢扩散，其中氮化的氧化铝（N-AlOx）形成在铁电电容器（C < 在氮化的氧化铝（N-AlOx）上形成一个或多个氮化硅层（112,117）。还提供了氢屏障，其中在铁电电容器（CFE）上形成氧化铝（AlOx，N-AlOx），其上形成有两个或更多个氮化硅层（112,117）氧化铝（AlOx，N-AlOx），其中第二氮化硅层（112）包括低硅氢SiN材料。

8. 发明申请

US20060134808A1 Ferroelectric capacitor stack etch cleaning methods 有权
标题翻译：铁电电容堆栈蚀刻清洗方法
公开(公告)号：US20060134808A1
公开(公告)日：2006-06-22
申请号：US11016400
申请日：2004-12-17
申请人： Scott Summerfelt , Lindsey Hall , K. Udayakumar , Theodore Moise
发明人： Scott Summerfelt , Lindsey Hall , K. Udayakumar , Theodore Moise
IPC分类号： H01L21/00
CPC分类号： H01L21/0206 , H01L21/02071 , H01L28/55 , H01L28/57 , H01L28/65 , H01L28/75
摘要： Methods (100) are provided for fabricating a ferroelectric capacitor structure including methods (128) for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The methods comprise etching (140, 200) portions of an upper electrode, etching (141, 201) ferroelectric material, and etching (142, 202) a lower electrode to define a patterned ferroelectric capacitor structure, and etching (143, 206) a portion of a lower electrode diffusion barrier structure. The methods further comprise ashing (144, 203) the patterned ferroelectric capacitor structure using a first ashing process, performing (145, 204) a wet clean process after the first ashing process, and ashing (146, 205) the patterned ferroelectric capacitor structure using a second ashing process directly after the wet clean process at a high temperature in an oxidizing ambient.
摘要翻译：提供了用于制造铁电电容器结构的方法（100），其包括用于在半导体器件中蚀刻和清洁图案化的铁电电容器结构的方法（128）。所述方法包括：上电极的蚀刻（140,200）部分，蚀刻（141,201）铁电材料和蚀刻（142,202）下电极以限定图案化的铁电电容器结构，以及蚀刻（143,206）a 部分下部电极扩散阻挡结构。所述方法还包括使用第一灰化处理灰化（144,203）所述图案化的铁电电容器结构，在第一灰化过程之后执行（145,204）湿式清洁处理，以及使用所述图案化铁电电容器结构灰化（146,205）在氧化环境中的高温下在湿式清洁工艺之后直接进行第二次灰化处理。

9. 发明申请

US20050012126A1 Hydrogen barrier for protecting ferroelectric capacitors in a semiconductor device and methods for fabricating the same 有权
标题翻译：用于保护半导体器件中的铁电电容器的氢屏障及其制造方法
公开(公告)号：US20050012126A1
公开(公告)日：2005-01-20
申请号：US10620516
申请日：2003-07-16
申请人： K. Udayakumar , Martin Albrecht , Theodore Moise , Scott Summerfelt , Sanjeev Aggarwal , Jeff Large
发明人： K. Udayakumar , Martin Albrecht , Theodore Moise , Scott Summerfelt , Sanjeev Aggarwal , Jeff Large
IPC分类号： H01L21/02 , H01L23/00 , H01L29/06 , H01L21/00 , H01L31/0328 , H01L31/0336 , H01L31/072
CPC分类号： H01L28/57 , H01L23/564 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and fabrication methods are presented, in which a hydrogen barrier is provided above a ferroelectric capacitor to prevent degradation of the ferroelectric material during back-end manufacturing processes employing hydrogen. The hydrogen barrier comprises silicon rich silicon oxide or amorphous silicon, which can be used in combination with an aluminum oxide layer to inhibit diffusion of process-related hydrogen into the ferroelectric capacitor layer.
摘要翻译：提出了半导体器件和制造方法，其中在铁电电容器上方设置氢气阻挡层，以防止在使用氢的后端制造工艺期间铁电材料的劣化。氢势垒包括富硅氧化物或非晶硅，其可以与氧化铝层组合使用以抑制工艺相关氢扩散到铁电电容器层中。

10. 发明申请

US20120170350A1 METHOD AND APPARATUS PERTAINING TO A FERRO-MAGNETIC RANDOM ACCESS MEMORY 有权
标题翻译：对于磁性随机存取存储器的方法和装置
公开(公告)号：US20120170350A1
公开(公告)日：2012-07-05
申请号：US13243875
申请日：2011-09-23
申请人： Michael Patrick Clinton , Steven Craig Bartling , Scott Summerfelt , Hugh McAdams
发明人： Michael Patrick Clinton , Steven Craig Bartling , Scott Summerfelt , Hugh McAdams
IPC分类号： G11C11/22
CPC分类号： G11C11/1673 , G11C11/1677 , G11C11/22 , G11C29/12 , G11C29/30 , G11C2029/1202 , G11C2029/5002
摘要： An FRAM device can comprise a sense amplifier, at least a first bitcell, a first control line, and a second control line. The first bitcell can have a bit line that connects to the sense amplifier via a first isolator and a complimentary bit line that connects to the sense amplifier via a second isolator that is different from the first isolator. The first control line can connect to and control the aforementioned first isolator. And the second control line can connect to and control the second isolator such that the second isolator is independently controlled with respect to the first isolator to facilitate testing the device.
摘要翻译： FRAM设备可以包括读出放大器，至少第一位单元，第一控制线和第二控制线。第一位单元可以具有通过第一隔离器和与第一隔离器不同的第二隔离器连接到读出放大器的互补位线连接到读出放大器的位线。第一控制线可以连接到并控制上述第一隔离器。并且第二控制线可以连接到并控制第二隔离器，使得第二隔离器相对于第一隔离器被独立地控制，以便于测试设备。

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