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1. 发明申请

US20050227378A1 Integrated circuit and method 有权
公开(公告)号：US20050227378A1
公开(公告)日：2005-10-13
申请号：US11145663
申请日：2005-06-06
申请人： Theodore Moise , Guoqiang Xing , Mark Visokay , Justin Gaynor , Stephen Gilbert , Francis Celii , Scott Summerfelt , Luigi Colombo
发明人： Theodore Moise , Guoqiang Xing , Mark Visokay , Justin Gaynor , Stephen Gilbert , Francis Celii , Scott Summerfelt , Luigi Colombo
IPC分类号： H01L21/02 , H01L21/311 , H01L21/768 , H01L21/8242 , H01L21/8246 , H01L27/108 , H01L27/115
CPC分类号： H01L27/11502 , H01L21/31116 , H01L21/76895 , H01L27/10811 , H01L27/10814 , H01L27/10852 , H01L27/11507 , H01L28/55
摘要： A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.

2. 发明申请

US20050112898A1 Method for etching a substrate and a device formed using the method 有权
标题翻译：用于蚀刻基板的方法和使用该方法形成的器件
公开(公告)号：US20050112898A1
公开(公告)日：2005-05-26
申请号：US10721932
申请日：2003-11-25
申请人： K.R. Udayakumar , Ted Moise , Scott Summerfelt , Martin Albrecht , William Dostalik , Francis Celii
发明人： K.R. Udayakumar , Ted Moise , Scott Summerfelt , Martin Albrecht , William Dostalik , Francis Celii
IPC分类号： H01L21/02 , H01L21/311 , H01L21/316 , H01L21/768 , H01L21/302 , H01L21/461
CPC分类号： H01L21/31116 , H01L21/31616 , H01L21/76895 , H01L28/55
摘要： The present invention provides a method for etching a substrate, a method for forming an integrated circuit, an integrated circuit formed using the method, and an integrated circuit. The method for etching a substrate includes, among other steps, providing a substrate 140 having an aluminum oxide etch stop layer 130 located thereunder, and then etching an opening 150, 155, in the substrate 140 using an etchant comprising carbon oxide, a fluorocarbon, an etch rate modulator, and an inert carrier gas, wherein a flow rate of the carbon oxide is greater than about 80 sccm and the etchant is selective to the aluminum oxide etch stop layer 130. The aluminum oxide etch stop layer may also be used in the back-end of advanced CMOS processes as a via etch stop layer.
摘要翻译：本发明提供了蚀刻基板的方法，集成电路的形成方法，使用该方法形成的集成电路和集成电路。除了其他步骤之外，用于蚀刻衬底的方法包括提供具有位于其下方的氧化铝蚀刻停止层130的衬底140，然后使用包含碳氧化物，碳氟化合物的蚀刻剂在衬底140中蚀刻开口150,155，蚀刻速率调制器和惰性载气，其中碳氧化物的流速大于约80sccm，并且蚀刻剂对氧化铝蚀刻停止层130是选择性的。氧化铝蚀刻停止层也可用作先进CMOS工艺的后端作为通孔蚀刻停止层。

3. 发明申请

US20070221974A1 Method for Forming Ferroelectric Memory Capacitor 审中-公开
标题翻译：形成铁电存储电容器的方法
公开(公告)号：US20070221974A1
公开(公告)日：2007-09-27
申请号：US11756372
申请日：2007-05-31
申请人： Francis Celii , Mahesh Thakre , Scott Summerfelt
发明人： Francis Celii , Mahesh Thakre , Scott Summerfelt
IPC分类号： H01L29/94
CPC分类号： H01L28/55 , H01L21/31122 , H01L21/32136 , H01L28/75
摘要： A ferroelectric memory capacitor is formed by forming a barrier layer, a first metal layer, a ferroelectric layer, a second metal layer, and a hard mask layer, on dielectric layer (70). Using the patterned hard mask layer (255), the layers are etched to form an etched barrier layer (205), and etched first metal layer (215), and etched ferroelectric layer (225), and etched second metal layers (235, 245). The etched layers form a ferroelectric memory capacitor (270) with sidewalls that form an angle with the plane of the upper surface of the dielectric layer (70) between 78° and 88°. The processes used to etch the layers are plasma processes performed at temperatures between 200° C. and 500° C.
摘要翻译：在电介质层（70）上形成阻挡层，第一金属层，铁电体层，第二金属层和硬掩模层，形成铁电存储电容器。使用图案化的硬掩模层（255），蚀刻这些层以形成蚀刻的阻挡层（205），蚀刻第一金属层（215）和蚀刻铁电层（225），并蚀刻第二金属层）。蚀刻层形成具有与电介质层（70）的上表面的平面形成角度为78°至88°的侧壁的铁电存储电容器（270）。用于蚀刻层的工艺是在200℃和500℃之间的温度下进行的等离子体处理。

4. 发明授权

US06692976B1 Post-etch cleaning treatment 有权
标题翻译：蚀刻后清洗处理
公开(公告)号：US06692976B1
公开(公告)日：2004-02-17
申请号：US09650224
申请日：2000-08-31
申请人： Laura Wills Mirkarimi , Stephen R. Gilbert , Guoqiang Xing , Scott Summerfelt , Tomoyuki Sakoda , Ted Moise
发明人： Laura Wills Mirkarimi , Stephen R. Gilbert , Guoqiang Xing , Scott Summerfelt , Tomoyuki Sakoda , Ted Moise
IPC分类号： H01L21306
CPC分类号： H01L28/55 , H01L21/02052 , H01L21/0206 , H01L21/31111 , H01L21/32134 , H01L28/75
摘要： The present disclosure relates to a post-etch cleaning treatment for a semiconductor device such as a FeRAM. The treatment comprises providing an etchant comprising both a fluorine compound and a chlorine compound, and applying the etchant to the semiconductor device in a wet cleaning process.
摘要翻译：本公开涉及用于诸如FeRAM的半导体器件的后蚀刻清洁处理。该处理包括提供包括氟化合物和氯化合物两者的蚀刻剂，以及在湿清洗工艺中将蚀刻剂施加到半导体器件。

5. 发明申请

US20050054122A1 FeRAM capacitor stack etch 有权
标题翻译： FeRAM电容堆栈蚀刻
公开(公告)号：US20050054122A1
公开(公告)日：2005-03-10
申请号：US10968721
申请日：2004-10-19
申请人： Francis Celii , Scott Summerfelt , Mahesh Thakre
发明人： Francis Celii , Scott Summerfelt , Mahesh Thakre
IPC分类号： H01L21/3065 , H01L21/02 , H01L21/311 , H01L21/316 , H01L21/3213 , H01L21/8246 , H01L27/105 , H01L27/115 , H01L21/00
CPC分类号： H01L27/11502 , H01L21/31122 , H01L21/31691 , H01L21/32139 , H01L27/11507 , H01L28/55
摘要： The present invention is directed to a method of forming an FeRAM integrated circuit, which includes performing a capacitor stack etch to define the FeRAM capacitor. The method comprises etching a PZT ferroelectric layer with a high temperature BCl3 etch which provides substantial selectivity with respect to the hard mask. Alternatively, the PZT ferroelectric layer is etch using a low temperature fluorine component etch chemistry such as CHF3 to provide a non-vertical PZT sidewall profile. Such a profile prevents conductive material associated with a subsequent bottom electrode layer etch from depositing on the PZT sidewall, thereby preventing leakage or a “shorting out” of the resulting FeRAM capacitor.
摘要翻译：本发明涉及形成FeRAM集成电路的方法，其包括执行电容器堆叠蚀刻以限定FeRAM电容器。该方法包括用提供相对于硬掩模的实质选择性的高温BCl3蚀刻来蚀刻PZT铁电层。或者，PZT铁电层是使用诸如CHF 3的低温氟成分蚀刻化学品进行蚀刻，以提供非垂直PZT侧壁轮廓。这种轮廓防止与随后的底部电极层蚀刻相关联的导电材料沉积在PZT侧壁上，从而防止所得FeRAM电容器的泄漏或“短路”。

6. 发明授权

US06576546B2 Method of enhancing adhesion of a conductive barrier layer to an underlying conductive plug and contact for ferroelectric applications 有权
公开(公告)号：US06576546B2
公开(公告)日：2003-06-10
申请号：US09741677
申请日：2000-12-19
申请人： Stephen R. Gilbert , Scott Summerfelt , Luigi Colombo
发明人： Stephen R. Gilbert , Scott Summerfelt , Luigi Colombo
IPC分类号： H01L214763
CPC分类号： H01L21/32051 , H01L21/76802 , H01L21/76814 , H01L21/76826 , H01L21/76828 , H01L21/76832 , H01L21/76847 , H01L21/76849 , H01L21/76855 , H01L21/7687 , H01L21/76877 , H01L21/76889 , H01L28/75
摘要： An embodiment of the instant invention is a method of forming a conductive barrier layer on a dielectric layer, the method comprising the steps of: providing the dielectric layer (112 of FIG. 7d) having a top surface, a bottom surface, and an opening extending from the top surface to the bottom surface, and including a conductive plug (704 of FIG. 7d) having a top surface substantially coplanar with the top surface of the dielectric layer; subjecting the top surface of the dielectric layer and the top surface of the conductive plug to a gas selected from the group consisting of: argon, nitrogen, hydrogen, CH4, and any combination thereof, the gas being incorporated into a high-temperature ambient or a plasma; and forming the conductive barrier layer on the top surface of the dielectric layer and the top surface of the conductive plug after the step of subjecting the top surface of the dielectric layer and the top surface of the conductive plug to the gas incorporated into the high-temperature ambient or the plasma.

7. 发明授权

US06635528B2 Method of planarizing a conductive plug situated under a ferroelectric capacitor 有权
标题翻译：平面化位于铁电电容器下方的导电插塞的方法
公开(公告)号：US06635528B2
公开(公告)日：2003-10-21
申请号：US09741675
申请日：2000-12-19
申请人： Stephen R. Gilbert , Scott Summerfelt , Luigi Colombo
发明人： Stephen R. Gilbert , Scott Summerfelt , Luigi Colombo
IPC分类号： H01L2100
CPC分类号： H01L21/32139 , H01L21/76832 , H01L21/76834 , H01L21/7684 , H01L21/76849 , H01L21/7687 , H01L21/76877 , H01L27/11502 , H01L27/11507 , H01L28/55
摘要： An embodiment of the instant invention is a method of fabricating a planar conductive via in an opening through a dielectric layer having a top surface, a bottom surface and the opening having sides, the method comprising the steps of: depositing a first conductive material (114 of FIG. 7d) on the top surface of the dielectric layer and in the opening in the dielectric layer to substantially fill the opening with the conductive material; removing the portion of the first conductive material located on the dielectric layer and removing a portion of the first conductive material located in the opening in the dielectric layer to recess (406 of FIG. 7d) the first conductive material below the top surface of the dielectric layer; depositing a second conductive material (704 of FIG. 7d) in the recess to form a substantially planar top surface substantially coplanar with the top surface of the dielectric layer; and forming a third conductive material (302 of FIG. 7d) on the second conductive material, at least one of the second conductive material and the third conductive material acting as a diffusion barrier to prevent oxidation of the first conductive material.
摘要翻译：本发明的一个实施例是一种在具有顶表面，底表面和开口具有侧面的电介质层的开口中制造平面导电通孔的方法，所述方法包括以下步骤：将第一导电材料（114 在电介质层的顶表面和电介质层的开口中，以基本上用导电材料填充开口; 去除位于电介质层上的第一导电材料的部分，并且去除位于电介质层中的开口中的第一导电材料的一部分以凹陷（图7d的406）第一导电材料在电介质顶表面下方层; 在凹槽中沉积第二导电材料（图7d的704）以形成与介电层的顶表面基本上共面的基本平坦的顶表面; 以及在所述第二导电材料上形成第三导电材料（图7d的302），所述第二导电材料和所述第三导电材料中的至少一个用作扩散阻挡层以防止所述第一导电材料的氧化。

8. 发明授权

US06709875B2 Contamination control for embedded ferroelectric device fabrication processes 失效
标题翻译：嵌入式铁电元件制造工艺的污染控制
公开(公告)号：US06709875B2
公开(公告)日：2004-03-23
申请号：US09925201
申请日：2001-08-08
申请人： Stephen R. Gilbert , Trace Q. Hurd , Laura W. Mirkarimi , Scott Summerfelt , Luigi Colombo
发明人： Stephen R. Gilbert , Trace Q. Hurd , Laura W. Mirkarimi , Scott Summerfelt , Luigi Colombo
IPC分类号： H01G706
CPC分类号： H01L21/6708 , H01L21/31122 , H01L21/32136 , H01L27/0805 , H01L27/11502 , H01L28/55
摘要： A ferroelectric device fabrication process is described in which ferroelectric device contaminant substances (e.g., Pb, Zr, Ti, and Ir) that are incompatible with standard CMOS fabrication processes are tightly controlled. In particular, specific etch chemistries have been developed to remove incompatible substances from the backside and edge surfaces of the substrate after a ferroelectric device has been formed. In addition, a sacrificial layer may be disposed over the bottom and edge surfaces (and, in some embodiments, the frontside edge exclusion zone surface) of the substrate to assist in the removal of difficult-to-etch contaminants (e.g., Ir). In this way, the ferroelectric device fabrication process may be integrated with a standard semiconductor fabrication process, whereby ferroelectric devices may be formed together with semiconductor integrated circuits without substantial risk of cross-contamination through shared equipment (e.g., steppers, metrology tools, and the like).
摘要翻译：描述了与标准CMOS制造工艺不兼容的铁电体器件污染物质（例如，Pb，Zr，Ti和Ir）被严格控制的铁电器件制造工艺。特别地，已经开发了特定的蚀刻化学物质，以在形成铁电体器件之后从衬底的背面和边缘表面去除不相容的物质。此外，牺牲层可以设置在衬底的底部和边缘表面（以及在一些实施例中，前侧边缘排除区域表面）之上，以帮助去除难以蚀刻的污染物（例如Ir）。以这种方式，铁电体器件的制造工艺可以与标准的半导体制造工艺集成在一起，由此铁电器件可以与半导体集成电路一起形成，而没有通过共享设备（例如，步进器，计量工具和喜欢）。

9. 发明申请

US20050205911A1 Ferroelectric capacitor hydrogen barriers and methods for fabricating the same 有权
标题翻译：铁电电容器氢屏障及其制造方法
公开(公告)号：US20050205911A1
公开(公告)日：2005-09-22
申请号：US11033224
申请日：2005-01-11
申请人： K. Udayakumar , Theodore Moise , Scott Summerfelt
发明人： K. Udayakumar , Theodore Moise , Scott Summerfelt
IPC分类号： H01L27/105 , H01L21/02 , H01L21/8246 , H01L29/76 , H01L29/94
CPC分类号： H01L27/11507 , H01L28/57
摘要： Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (CFE) from hydrogen diffusion in semiconductor devices (102), wherein nitrided aluminum oxide (N—AlOx) is formed over a ferroelectric capacitor (CFE), and one or more silicon nitride layers (112, 117) are formed over the nitrided aluminum oxide (N—AlOx). Hydrogen barriers are also provided in which an aluminum oxide (AlOx, N—AlOx) is formed over the ferroelectric capacitors (CFE), with two or more silicon nitride layers (112, 117) formed over the aluminum oxide (AlOx, N—AlOx), wherein the second silicon nitride layer (112) comprises a low silicon-hydrogen SiN material.
摘要翻译：提供氢屏障和制造方法用于在半导体器件（102）中保护铁电电容器（C LIMIT）免受氢扩散，其中氮化的氧化铝（N-AlOx）形成在铁电电容器（C < 在氮化的氧化铝（N-AlOx）上形成一个或多个氮化硅层（112,117）。还提供了氢屏障，其中在铁电电容器（CFE）上形成氧化铝（AlOx，N-AlOx），其上形成有两个或更多个氮化硅层（112,117）氧化铝（AlOx，N-AlOx），其中第二氮化硅层（112）包括低硅氢SiN材料。

10. 发明申请

US20050145908A1 High polarization ferroelectric capacitors for integrated circuits 审中-公开
标题翻译：用于集成电路的高极化铁电电容器
公开(公告)号：US20050145908A1
公开(公告)日：2005-07-07
申请号：US10749668
申请日：2003-12-30
申请人： Theodore Moise , Scott Summerfelt , K.R. Udayakumar
发明人： Theodore Moise , Scott Summerfelt , K.R. Udayakumar
IPC分类号： H01L21/02 , H01L21/8246 , H01L27/115 , H01L21/00 , H01L29/76
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55
摘要： One aspect of the invention relates to a method of manufacturing an integrated circuit comprising forming an array of ferroelectric memory cells on a semiconductor substrate, heating the substrate to a temperature near a Curie temperature of the ferroelectric cores, and subjecting the substrate to a temperature program, whereby thermally induced stresses on the ferroelectric cores cause a switched polarization of the cores to increase by at least about 25% as the cores cool to about room temperature. Embodiments of the invention include metal filled vias of expanded cross-section above and below the ferroelectric cores, which increase the thermal stresses on the ferroelectic cores during cooling.
摘要翻译：本发明的一个方面涉及一种制造集成电路的方法，包括在半导体衬底上形成铁电存储器单元的阵列，将衬底加热到铁电芯的居里温度附近的温度，并对衬底进行温度程序，由此当铁芯冷却至约室温时，铁电芯上的热诱导应力使芯的开关极化增加至少约25％。本发明的实施例包括在铁电芯上方和下方的膨胀横截面的金属填充通孔，其在冷却期间增加铁电芯上的热应力。

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