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    • 2. 发明授权
      US08508974B2 Ferroelectric memory with shunt device 有权
    • Ferroelectric memory with shunt device
    • 铁电存储器带分流装置
    • US08508974B2
    • 2013-08-13
    • US13240420
    • 2011-09-22
    • Michael Patrick Clinton , Steven Craig Bartling , Scott Summerfelt , Hugh McAdams
    • Michael Patrick Clinton , Steven Craig Bartling , Scott Summerfelt , Hugh McAdams
    • G11C11/22 , G11C5/06 , G11C7/00
    • G11C11/2253 , G11C11/2275
    • A ferroelectric memory device includes a shunt switch configured to short both sides of the ferroelectric capacitor of the ferroelectric memory device. The shunt switch is configured therefore to remove excess charge from around the ferroelectric capacitor prior to or after reading data from the ferroelectric capacitor. By one approach, the shunt switch is connected to operate in reaction to signals from the same line that controls accessing the ferroelectric capacitor. So configured, the high performance cycle time of the ferroelectric memory device is reduced by eliminating delays used to otherwise drain excess charge from around the ferroelectric capacitor, for example by applying a precharge voltage. The shunt switch also improves reliability of the ferroelectric memory device by ensuring that excess charge does not affect the reading of the ferroelectric capacitor during a read cycle.
    • 铁电存储器件包括分配开关，其被配置为使铁电存储器件的铁电电容器的两侧短路。 因此，分流开关被配置为在从铁电电容器读取数据之前或之后从铁电电容器周围除去多余的电荷。 通过一种方法，分流开关被连接以对来自控制接入铁电电容器的相同线路的信号进行操作。 这样配置，例如通过施加预充电电压，通过消除用于否则从铁电电容器周围排出过量电荷的延迟来降低铁电存储器件的高性能周期时间。 分流开关还通过确保在读取周期期间过量的电荷不影响铁电电容器的读取来提高铁电存储器件的可靠性。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 3. 发明申请
      US20120170349A1 Ferroelectric Memory with Shunt Device 有权
    • Ferroelectric Memory with Shunt Device
    • 带分流装置的铁电存储器
    • US20120170349A1
    • 2012-07-05
    • US13240420
    • 2011-09-22
    • Michael Patrick Clinton , Steven Craig Bartling , Scott Summerfelt , Hugh McAdams
    • Michael Patrick Clinton , Steven Craig Bartling , Scott Summerfelt , Hugh McAdams
    • G11C11/22
    • G11C11/2253 , G11C11/2275
    • A ferroelectric memory device includes a shunt switch configured to short both sides of the ferroelectric capacitor of the ferroelectric memory device. The shunt switch is configured therefore to remove excess charge from around the ferroelectric capacitor prior to or after reading data from the ferroelectric capacitor. By one approach, the shunt switch is connected to operate in reaction to signals from the same line that controls accessing the ferroelectric capacitor. So configured, the high performance cycle time of the ferroelectric memory device is reduced by eliminating delays used to otherwise drain excess charge from around the ferroelectric capacitor, for example by applying a precharge voltage. The shunt switch also improves reliability of the ferroelectric memory device by ensuring that excess charge does not affect the reading of the ferroelectric capacitor during a read cycle.
    • 铁电存储器件包括分配开关，其被配置为使铁电存储器件的铁电电容器的两侧短路。 因此，分流开关被配置为在从铁电电容器读取数据之前或之后从铁电电容器周围除去多余的电荷。 通过一种方法，分流开关被连接以对来自控制接入铁电电容器的相同线路的信号进行操作。 这样配置，例如通过施加预充电电压，通过消除用于否则从铁电电容器周围排出过量电荷的延迟来降低铁电存储器件的高性能周期时间。 分流开关还通过确保在读取周期期间过量的电荷不影响铁电电容器的读取来提高铁电存储器件的可靠性。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 4. 发明申请
      US20120170348A1 Ferroelectric Memory Write-Back 有权
    • Ferroelectric Memory Write-Back
    • 铁电存储器回写
    • US20120170348A1
    • 2012-07-05
    • US13240252
    • 2011-09-22
    • Michael Patrick Clinton , Steven Craig Bartling , Scott Summerfelt , Hugh McAdams
    • Michael Patrick Clinton , Steven Craig Bartling , Scott Summerfelt , Hugh McAdams
    • G11C11/22
    • G11C11/22
    • A self-timed sense amplifier read buffer pulls down a pre-charged high global bit line, which then feeds data into a tri state write back buffer that is connected directly to the bit line. The bit line provides charge to a ferroelectric capacitor to write a logical “one” or “zero” while by-passing an isolator switch disposed between the sense amplifier and the ferroelectric capacitor. Because the sense amplifier uses grounded bit line sensing, the read buffer will not start pulling down the global bit line until after the sense amplifier signal amplification, which makes the timing of the control signal for this read buffer non-critical. The write-back buffer enable timing is also self-timed off of the sense amplifier. Therefore, the read data write-back to a ferroelectric memory cell is locally controlled and begins quickly after reading data from the ferroelectric memory cell, thereby allowing a quick cycle time.
    • 自定时读出放大器读缓冲器拉低预充电的高全局位线，然后将数据馈送到直接连接到位线的三态回写缓冲器。 该位线向强电介质电容器充电以在绕过感测放大器和铁电电容器之间的隔离开关旁路时写入逻辑“1”或“0”。 由于读出放大器使用接地位线检测，所以读缓冲器不会开始下拉全局位线直到读出放大器信号放大，这使得该读缓冲器的控制信号的定时非关键。 回写缓冲器使能定时也是从读出放大器自定时的。 因此，读取到强电介质存储单元的数据被局部控制，并且在从铁电存储单元读取数据之后迅速开始，从而允许快速循环时间。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 8. 发明授权
      US08477522B2 Ferroelectric memory write-back 有权
    • Ferroelectric memory write-back
    • 铁电记忆回写
    • US08477522B2
    • 2013-07-02
    • US13240252
    • 2011-09-22
    • Michael Patrick Clinton , Steven Craig Bartling , Scott Summerfelt , Hugh McAdams
    • Michael Patrick Clinton , Steven Craig Bartling , Scott Summerfelt , Hugh McAdams
    • G11C11/22 , G11C7/00 , G11C7/22
    • G11C11/22
    • A self-timed sense amplifier read buffer pulls down a pre-charged high global bit line, which then feeds data into a tri state write back buffer that is connected directly to the bit line. The bit line provides charge to a ferroelectric capacitor to write a logical “one” or “zero” while by-passing an isolator switch disposed between the sense amplifier and the ferroelectric capacitor. Because the sense amplifier uses grounded bit line sensing, the read buffer will not start pulling down the global bit line until after the sense amplifier signal amplification, which makes the timing of the control signal for this read buffer non-critical. The write-back buffer enable timing is also self-timed off of the sense amplifier. Therefore, the read data write-back to a ferroelectric memory cell is locally controlled and begins quickly after reading data from the ferroelectric memory cell, thereby allowing a quick cycle time.
    • 自定时读出放大器读缓冲器拉低预充电的高全局位线，然后将数据馈送到直接连接到位线的三态回写缓冲器。 该位线向强电介质电容器充电以在绕过感测放大器和铁电电容器之间的隔离开关旁路时写入逻辑“1”或“0”。 由于读出放大器使用接地位线检测，所以读缓冲器不会开始下拉全局位线直到读出放大器信号放大，这使得该读缓冲器的控制信号的定时非关键。 回写缓冲器使能定时也是从读出放大器自定时的。 因此，读取到强电介质存储单元的数据被局部控制，并且在从铁电存储单元读取数据之后迅速开始，从而允许快速循环时间。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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