专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060008965A1 Hardmask for forming ferroelectric capacitors in a semiconductor device and methods for fabricating the same 有权
公开(公告)号：US20060008965A1
公开(公告)日：2006-01-12
申请号：US11220292
申请日：2005-09-06
申请人： Sanjeev Aggarwal , Kelly Taylor , Theodore Moise
发明人： Sanjeev Aggarwal , Kelly Taylor , Theodore Moise
IPC分类号： H01L21/8238
CPC分类号： H01L27/11502 , H01L21/28568 , H01L21/31122 , H01L21/32136 , H01L21/32139 , H01L27/11507 , H01L28/55 , H01L28/65 , H01L28/75
摘要： Hardmasks and fabrication methods are presented for producing ferroelectric capacitors in a semiconductor device, wherein a hardmask comprising aluminum oxide or strontium tantalum oxide is formed above an upper capacitor electrode material, and capacitor electrode and ferroelectric layers are etched to define a ferroelectric capacitor stack.

2. 发明申请

US20050227378A1 Integrated circuit and method 有权
公开(公告)号：US20050227378A1
公开(公告)日：2005-10-13
申请号：US11145663
申请日：2005-06-06
申请人： Theodore Moise , Guoqiang Xing , Mark Visokay , Justin Gaynor , Stephen Gilbert , Francis Celii , Scott Summerfelt , Luigi Colombo
发明人： Theodore Moise , Guoqiang Xing , Mark Visokay , Justin Gaynor , Stephen Gilbert , Francis Celii , Scott Summerfelt , Luigi Colombo
IPC分类号： H01L21/02 , H01L21/311 , H01L21/768 , H01L21/8242 , H01L21/8246 , H01L27/108 , H01L27/115
CPC分类号： H01L27/11502 , H01L21/31116 , H01L21/76895 , H01L27/10811 , H01L27/10814 , H01L27/10852 , H01L27/11507 , H01L28/55
摘要： A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.

3. 发明申请

US20050205911A1 Ferroelectric capacitor hydrogen barriers and methods for fabricating the same 有权
标题翻译：铁电电容器氢屏障及其制造方法
公开(公告)号：US20050205911A1
公开(公告)日：2005-09-22
申请号：US11033224
申请日：2005-01-11
申请人： K. Udayakumar , Theodore Moise , Scott Summerfelt
发明人： K. Udayakumar , Theodore Moise , Scott Summerfelt
IPC分类号： H01L27/105 , H01L21/02 , H01L21/8246 , H01L29/76 , H01L29/94
CPC分类号： H01L27/11507 , H01L28/57
摘要： Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (CFE) from hydrogen diffusion in semiconductor devices (102), wherein nitrided aluminum oxide (N—AlOx) is formed over a ferroelectric capacitor (CFE), and one or more silicon nitride layers (112, 117) are formed over the nitrided aluminum oxide (N—AlOx). Hydrogen barriers are also provided in which an aluminum oxide (AlOx, N—AlOx) is formed over the ferroelectric capacitors (CFE), with two or more silicon nitride layers (112, 117) formed over the aluminum oxide (AlOx, N—AlOx), wherein the second silicon nitride layer (112) comprises a low silicon-hydrogen SiN material.
摘要翻译：提供氢屏障和制造方法用于在半导体器件（102）中保护铁电电容器（C LIMIT）免受氢扩散，其中氮化的氧化铝（N-AlOx）形成在铁电电容器（C < 在氮化的氧化铝（N-AlOx）上形成一个或多个氮化硅层（112,117）。还提供了氢屏障，其中在铁电电容器（CFE）上形成氧化铝（AlOx，N-AlOx），其上形成有两个或更多个氮化硅层（112,117）氧化铝（AlOx，N-AlOx），其中第二氮化硅层（112）包括低硅氢SiN材料。

4. 发明申请

US20050145908A1 High polarization ferroelectric capacitors for integrated circuits 审中-公开
标题翻译：用于集成电路的高极化铁电电容器
公开(公告)号：US20050145908A1
公开(公告)日：2005-07-07
申请号：US10749668
申请日：2003-12-30
申请人： Theodore Moise , Scott Summerfelt , K.R. Udayakumar
发明人： Theodore Moise , Scott Summerfelt , K.R. Udayakumar
IPC分类号： H01L21/02 , H01L21/8246 , H01L27/115 , H01L21/00 , H01L29/76
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55
摘要： One aspect of the invention relates to a method of manufacturing an integrated circuit comprising forming an array of ferroelectric memory cells on a semiconductor substrate, heating the substrate to a temperature near a Curie temperature of the ferroelectric cores, and subjecting the substrate to a temperature program, whereby thermally induced stresses on the ferroelectric cores cause a switched polarization of the cores to increase by at least about 25% as the cores cool to about room temperature. Embodiments of the invention include metal filled vias of expanded cross-section above and below the ferroelectric cores, which increase the thermal stresses on the ferroelectic cores during cooling.
摘要翻译：本发明的一个方面涉及一种制造集成电路的方法，包括在半导体衬底上形成铁电存储器单元的阵列，将衬底加热到铁电芯的居里温度附近的温度，并对衬底进行温度程序，由此当铁芯冷却至约室温时，铁电芯上的热诱导应力使芯的开关极化增加至少约25％。本发明的实施例包括在铁电芯上方和下方的膨胀横截面的金属填充通孔，其在冷却期间增加铁电芯上的热应力。

5. 发明申请

US20050032301A1 Low silicon-hydrogen sin layer to inhibit hydrogen related degradation in semiconductor devices having ferroelectric components 有权
标题翻译：低硅氢层，用于抑制具有铁电元件的半导体器件中的氢相关退化
公开(公告)号：US20050032301A1
公开(公告)日：2005-02-10
申请号：US10635994
申请日：2003-08-07
申请人： K. Udayakumar , Maritin Albrecht , Theodore Moise , Scott Summerfelt , Sarah Hartwig
发明人： K. Udayakumar , Maritin Albrecht , Theodore Moise , Scott Summerfelt , Sarah Hartwig
IPC分类号： H01L21/02 , H01L21/318 , H01L21/768 , H01L21/8246 , H01L27/115 , H01L21/8242 , H01L21/31 , H01L21/00 , H01L21/469
CPC分类号： H01L21/76829 , H01L21/3185 , H01L21/76828 , H01L21/76832 , H01L21/76834 , H01L27/11502 , H01L27/11507 , H01L28/57
摘要： Semiconductor devices and fabrication methods are disclosed, in which one or more low silicon-hydrogen SiN barriers are provided to inhibit hydrogen diffusion into ferroelectric capacitors and into transistor gate dielectric interface areas. The barriers may be used as etch stop layers in various levels of the semiconductor device structure above and/or below the level at which the ferroelectric capacitors are formed so as to reduce the hydrogen related degradation of the switched polarization properties of the ferroelectric capacitors and to reduce negative bias temperature instability in the device transistors.
摘要翻译：公开了半导体器件和制造方法，其中提供一个或多个低硅氢SiN栅极以阻止氢扩散到铁电电容器中并进入晶体管栅极电介质界面区域。可以将阻挡层用作在形成强电介质电容器的电平以上和/或以下的半导体器件结构的各种级别的蚀刻停止层，以便降低铁电电容器的开关极化特性的氢相关劣化，并且降低器件晶体管的负偏压温度不稳定性。

6. 发明授权

US06534809B2 Hardmask designs for dry etching FeRAM capacitor stacks 有权
标题翻译：硬掩模设计用于干蚀刻FeRAM电容器堆叠
公开(公告)号：US06534809B2
公开(公告)日：2003-03-18
申请号：US09741479
申请日：2000-12-19
申请人： Theodore Moise , Stephen R. Gilbert , Scott R. Summerfelt , Guoqiang Xing , Luigi Colombo
发明人： Theodore Moise , Stephen R. Gilbert , Scott R. Summerfelt , Guoqiang Xing , Luigi Colombo
IPC分类号： H01L2994
CPC分类号： H01L28/55 , H01L21/31122 , H01L21/31144 , H01L21/32136 , H01L21/32139
摘要： An embodiment of the instant invention is a ferroelectric capacitor formed over a semiconductor substrate, the ferroelectric capacitor comprising: a bottom electrode formed over the semiconductor substrate, the bottom electrode comprised of a bottom electrode material (304 of FIG. 4a); a top electrode formed over the bottom electrode and comprised of a first electrode material (306and 308 of FIG. 4a); a ferroelectric material (306 of FIG. 4a) situated between the top electrode and the bottom electrode; and a hardmask formed on the top electrode and comprising a bottom hardmask layer (402 of FIG. 4a) and a top hardmask layer (408 of FIG. 4a) formed on the bottom hardmask layer, the top hardmask layer able to with stand etchants used to etch the bottom electrode, the top electrode, and the ferroelectric material to leave the bottom hardmask layer substantially unremoved during the etch and the bottom hardmask layer being comprised of a conductive material which substantially acts as a hydrogen diffusion barrier.
摘要翻译：本发明的一个实施方案是形成在半导体衬底上的铁电电容器，所述铁电电容器包括：形成在所述半导体衬底上的底部电极，所述底部电极由底部电极材料（图4a的304）组成; 形成在底部电极上并由第一电极材料（图4a的306和308）组成的顶部电极; 位于顶部电极和底部电极之间的铁电材料（图4a的306）以及形成在顶部电极上并包括底部硬掩模层（图4a的402）和形成在底部硬掩模层上的顶部硬掩模层（图4a的408）的硬掩模，所述顶部硬掩模层能够使用支架蚀刻剂蚀刻底部电极，顶部电极和铁电材料以使蚀刻期间底部硬掩模层基本上不被去除，并且底部硬掩模层由基本上充当氢扩散阻挡层的导电材料构成。

7. 发明申请

US20050205906A1 FERROELECTRIC CAPACITOR HYDROGEN BARRIERS AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：电磁电容器氢气阻隔器及其制造方法
公开(公告)号：US20050205906A1
公开(公告)日：2005-09-22
申请号：US10803445
申请日：2004-03-18
申请人： K. Udayakumar , Theodore Moise , Scott Summerfelt
发明人： K. Udayakumar , Theodore Moise , Scott Summerfelt
IPC分类号： H01L27/105 , H01L21/02 , H01L21/8246 , H01L29/76 , H01L29/94
CPC分类号： H01L27/11507 , H01L28/57
摘要： Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (CFE) from hydrogen diffusion in semiconductor devices (102), wherein nitrided aluminum oxide (N—AlOx) is formed over a ferroelectric capacitor (CFE), and one or more silicon nitride layers (112, 117) are formed over the nitrided aluminum oxide (N—AlOx). Hydrogen barriers are also provided in which an aluminum oxide (AlOx, N—AlOx) is formed over the ferroelectric capacitors (CFE), with two or more silicon nitride layers (112, 117) formed over the aluminum oxide (AlOx, N—AlOx), wherein the second silicon nitride layer (112) comprises a low silicon-hydrogen SiN material.
摘要翻译：提供氢屏障和制造方法用于在半导体器件（102）中保护铁电电容器（C LIMIT）免受氢扩散，其中氮化的氧化铝（N-AlOx）形成在铁电电容器（C < 在氮化的氧化铝（N-AlOx）上形成一个或多个氮化硅层（112,117）。还提供了氢屏障，其中在铁电电容器（CFE）上形成氧化铝（AlOx，N-AlOx），其上形成有两个或更多个氮化硅层（112,117）氧化铝（AlOx，N-AlOx），其中第二氮化硅层（112）包括低硅氢SiN材料。

8. 发明申请

US20060134808A1 Ferroelectric capacitor stack etch cleaning methods 有权
标题翻译：铁电电容堆栈蚀刻清洗方法
公开(公告)号：US20060134808A1
公开(公告)日：2006-06-22
申请号：US11016400
申请日：2004-12-17
申请人： Scott Summerfelt , Lindsey Hall , K. Udayakumar , Theodore Moise
发明人： Scott Summerfelt , Lindsey Hall , K. Udayakumar , Theodore Moise
IPC分类号： H01L21/00
CPC分类号： H01L21/0206 , H01L21/02071 , H01L28/55 , H01L28/57 , H01L28/65 , H01L28/75
摘要： Methods (100) are provided for fabricating a ferroelectric capacitor structure including methods (128) for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The methods comprise etching (140, 200) portions of an upper electrode, etching (141, 201) ferroelectric material, and etching (142, 202) a lower electrode to define a patterned ferroelectric capacitor structure, and etching (143, 206) a portion of a lower electrode diffusion barrier structure. The methods further comprise ashing (144, 203) the patterned ferroelectric capacitor structure using a first ashing process, performing (145, 204) a wet clean process after the first ashing process, and ashing (146, 205) the patterned ferroelectric capacitor structure using a second ashing process directly after the wet clean process at a high temperature in an oxidizing ambient.
摘要翻译：提供了用于制造铁电电容器结构的方法（100），其包括用于在半导体器件中蚀刻和清洁图案化的铁电电容器结构的方法（128）。所述方法包括：上电极的蚀刻（140,200）部分，蚀刻（141,201）铁电材料和蚀刻（142,202）下电极以限定图案化的铁电电容器结构，以及蚀刻（143,206）a 部分下部电极扩散阻挡结构。所述方法还包括使用第一灰化处理灰化（144,203）所述图案化的铁电电容器结构，在第一灰化过程之后执行（145,204）湿式清洁处理，以及使用所述图案化铁电电容器结构灰化（146,205）在氧化环境中的高温下在湿式清洁工艺之后直接进行第二次灰化处理。

9. 发明申请

US20050101034A1 Hardmask for forming ferroelectric capacitors in a semiconductor device and methods for fabricating the same 有权
标题翻译：用于在半导体器件中形成铁电电容器的硬掩模及其制造方法
公开(公告)号：US20050101034A1
公开(公告)日：2005-05-12
申请号：US10705039
申请日：2003-11-10
申请人： Sanjeev Aggarwal , Kelly Taylor , Theodore Moise
发明人： Sanjeev Aggarwal , Kelly Taylor , Theodore Moise
IPC分类号： H01L21/00 , H01L21/02 , H01L21/285 , H01L21/311 , H01L21/3213 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11502 , H01L21/28568 , H01L21/31122 , H01L21/32136 , H01L21/32139 , H01L27/11507 , H01L28/55 , H01L28/65 , H01L28/75
摘要： Hardmasks and fabrication methods are presented for producing ferroelectric capacitors in a semiconductor device, wherein a hardmask comprising aluminum oxide or strontium tantalum oxide is formed above an upper capacitor electrode material, and capacitor electrode and ferroelectric layers are etched to define a ferroelectric capacitor stack.
摘要翻译：硬掩模和制造方法用于在半导体器件中制造铁电电容器，其中在上部电容器电极材料上方形成包括氧化铝或氧化钽锶的硬掩模，并蚀刻电容器电极和铁电层以限定铁电电容器叠层。

10. 发明申请

US20050012126A1 Hydrogen barrier for protecting ferroelectric capacitors in a semiconductor device and methods for fabricating the same 有权
标题翻译：用于保护半导体器件中的铁电电容器的氢屏障及其制造方法
公开(公告)号：US20050012126A1
公开(公告)日：2005-01-20
申请号：US10620516
申请日：2003-07-16
申请人： K. Udayakumar , Martin Albrecht , Theodore Moise , Scott Summerfelt , Sanjeev Aggarwal , Jeff Large
发明人： K. Udayakumar , Martin Albrecht , Theodore Moise , Scott Summerfelt , Sanjeev Aggarwal , Jeff Large
IPC分类号： H01L21/02 , H01L23/00 , H01L29/06 , H01L21/00 , H01L31/0328 , H01L31/0336 , H01L31/072
CPC分类号： H01L28/57 , H01L23/564 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and fabrication methods are presented, in which a hydrogen barrier is provided above a ferroelectric capacitor to prevent degradation of the ferroelectric material during back-end manufacturing processes employing hydrogen. The hydrogen barrier comprises silicon rich silicon oxide or amorphous silicon, which can be used in combination with an aluminum oxide layer to inhibit diffusion of process-related hydrogen into the ferroelectric capacitor layer.
摘要翻译：提出了半导体器件和制造方法，其中在铁电电容器上方设置氢气阻挡层，以防止在使用氢的后端制造工艺期间铁电材料的劣化。氢势垒包括富硅氧化物或非晶硅，其可以与氧化铝层组合使用以抑制工艺相关氢扩散到铁电电容器层中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式