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    • 1. 发明授权
    • Non-volatile semiconductor memory device
    • 非易失性半导体存储器件
    • US4774556A
    • 1988-09-27
    • US887625
    • 1986-07-21
    • Tetsuo FujiiNobuyoshi SakakibaraToshio SakakibaraHiroshi Iwasaki
    • Tetsuo FujiiNobuyoshi SakakibaraToshio SakakibaraHiroshi Iwasaki
    • H01L21/28H01L21/336H01L21/8246H01L21/8247H01L27/115H01L29/423H01L29/788H01L29/78H01L29/86
    • H01L27/11568H01L21/28273H01L27/11556H01L29/66825H01L29/7881H01L29/7883H01L27/115H01L29/4236
    • A non-volatile semiconductor memory device comprises a semiconductor substrate of a first conduction type, an impurity buried layer of a second conduction type formed at the surface of the semiconductor substrate for constituting either one of a drain region or a source region, an epitaxial layer of a second conduction type formed at the surface of said impurity buried layer, an insulatiang partition wall extended vertically from the surface of the epitaxial layer surrounding operation regions in the impurity buried layer for defining the operation regions therein, at least one electron holding portion extended vertically with a predetermined distance from the operation regions and disposed within the insulating partition wall apart from the operation region, the impurity buried layer or the drain region by an insulation film of such a thickness as causing a tunnel effect, control gates disposed within the insulation partition wall disposed on every electron holding portions on the side opposite to the operation regions and extended vertically with a certain gap from the electron maintaining portions, and a control gate disposed within the insulating partition wall on every electron holding portions on the opposite side to the operation region extended vertically and with a certain gap to the electron holding portions, and an impurity region of a second conduction type formed at the surface of the operation region for constituting the other of the drain region or the source region.
    • 非易失性半导体存储器件包括:第一导电类型的半导体衬底,形成在半导体衬底的表面的第二导电类型的杂质掩埋层,用于构成漏极区域或源极区域中的任一个,外延层 形成在所述杂质掩埋层的表面上的第二导电类型的绝缘分隔壁,包围在所述杂质掩埋层中的围绕所述杂质掩埋层的操作区域的外延层的表面垂直延伸的绝缘隔壁,用于限定其中的操作区域,至少一个电子保持部分延伸 垂直于操作区域预定的距离并且设置在与操作区域隔离的绝缘分隔壁内,通过具有隧道效应的厚度的绝缘膜的杂质掩埋层或漏极区域,设置在绝缘体内的控制栅极 分隔壁设置在侧面上的每个电子保持部分上 e与操作区域相对并且与电子维持部分具有一定间隙垂直延伸;以及控制栅极,设置在绝缘分隔壁内的每个电子保持部分上,与操作区域相对的一侧垂直延伸并且具有一定间隙 电子保持部分和形成在用于构成漏极区域或源极区域中的另一个的操作区域的表面处的第二导电类型的杂质区域。
    • 2. 发明授权
    • Method of making a nonvolatile semiconductor memory apparatus with a
floating gate
    • 制造具有浮动栅极的非易失性半导体存储装置的方法
    • US5017505A
    • 1991-05-21
    • US313898
    • 1989-02-23
    • Tetsuo FujiiToshio SakakibaraNobuyoshi Sakakibara
    • Tetsuo FujiiToshio SakakibaraNobuyoshi Sakakibara
    • H01L29/788
    • H01L29/7883Y10S438/964
    • A first polysilicon film serving as an erase gate is deposited on the major surface of a semiconductor substrate on which a field oxide film is formed, so that the surface of the first polysilicon film is roughened. The surface of the first polysilicon film is thermally oxidized to form a first thermal oxide film thereon. During the oxidation, the roughened surface of the first polysilicon film is flattened, and is duplicated by the surface of the first thermal oxide film. A second polysilicon film is deposited on the roughened surface of the first thermal oxide film. The back surface of the second polysilicon film is roughened by the roughened surface of the first thermal oxide film. In this case, the surface of the second polysilicon film is also roughened. The roughened surface of the second polysilicon film is thermally oxidized in the same manner as described above to flatten its surface and to form a second thermal oxide film, the surface of which is roughened. A third polysilicon film serving as a write gate is formed on the second thermal oxide film.
    • 用作擦除栅极的第一多晶硅膜沉积在其上形成有场氧化膜的半导体衬底的主表面上,使得第一多晶硅膜的表面被粗糙化。 第一多晶硅膜的表面被热氧化以在其上形成第一热氧化膜。 在氧化期间,第一多晶硅膜的粗糙化表面变平,并被第一热氧化膜的表面复制。 在第一热氧化膜的粗糙化表面上沉积第二多晶硅膜。 第二多晶硅膜的背面被第一热氧化膜的粗糙化表面粗糙化。 在这种情况下,第二多晶硅膜的表面也被粗糙化。 第二多晶硅膜的粗糙化表面以与上述相同的方式被热氧化以使其表面变平,并形成第二热氧化膜,其表面被粗糙化。 在第二热氧化膜上形成用作写入栅极的第三多晶硅膜。