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1. 发明申请

US20130134545A1 SELF-LIMITING OXYGEN SEAL FOR HIGH-K DIELECTRIC, RELATED METHOD AND DESIGN STRUCTURE 失效
标题翻译：用于高K电介质的自限制氧气密封件，相关方法和设计结构
公开(公告)号：US20130134545A1
公开(公告)日：2013-05-30
申请号：US13306621
申请日：2011-11-29
申请人： Terence B. Hook , Vijay Narayanan , Jay M. Shah , Melanie J. Sherony , Kenneth J. Stein , Helen H. Wang , Chendong Zhu
发明人： Terence B. Hook , Vijay Narayanan , Jay M. Shah , Melanie J. Sherony , Kenneth J. Stein , Helen H. Wang , Chendong Zhu
IPC分类号： H01L29/06 , H01L21/28
CPC分类号： H01L21/28247 , H01L21/28123 , H01L21/76224
摘要： A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including: a high-K dielectric region; a blocking region disposed against at least one surface of the high-K dielectric region and adapted to form an oxidized layer in response to exposure to oxygen; and an oxygen rich region disposed against the blocking region such that the blocking region is interposed between the oxygen rich region and the high-K dielectric region.
摘要翻译：公开了一种半导体器件。半导体器件包括：半导体衬底，包括：高K电介质区域; 阻挡区域，其设置成抵抗高K电介质区域的至少一个表面，并且适于响应于暴露于氧气而形成氧化层; 以及设置在阻挡区域上的富氧区域，使得阻挡区域介于富氧区域和高K电介质区域之间。

2. 发明授权

US08564074B2 Self-limiting oxygen seal for high-K dielectric and design structure 失效
标题翻译：用于高K电介质和设计结构的自限氧气密封
公开(公告)号：US08564074B2
公开(公告)日：2013-10-22
申请号：US13306621
申请日：2011-11-29
申请人： Terence B. Hook , Vijay Narayanan , Jay M. Shah , Melanie J. Sherony , Kenneth J. Stein , Helen H. Wang , Chendong Zhu
发明人： Terence B. Hook , Vijay Narayanan , Jay M. Shah , Melanie J. Sherony , Kenneth J. Stein , Helen H. Wang , Chendong Zhu
IPC分类号： H01L31/119
CPC分类号： H01L21/28247 , H01L21/28123 , H01L21/76224
摘要： A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including: a high-K dielectric region; a blocking region disposed against at least one surface of the high-K dielectric region and adapted to form an oxidized layer in response to exposure to oxygen; and an oxygen rich region disposed against the blocking region such that the blocking region is interposed between the oxygen rich region and the high-K dielectric region.
摘要翻译：公开了一种半导体器件。半导体器件包括：半导体衬底，包括：高K电介质区域; 阻挡区域，其设置在所述高K电介质区域的至少一个表面上，并适于响应于暴露于氧气而形成氧化层; 以及设置在阻挡区域上的富氧区域，使得阻挡区域介于富氧区域和高K电介质区域之间。

3. 发明申请

US20110169096A1 BALANCING NFET AND PFET PERFORMANCE USING STRAINING LAYERS 失效
标题翻译：使用应变层平衡NFET和PFET性能
公开(公告)号：US20110169096A1
公开(公告)日：2011-07-14
申请号：US12687374
申请日：2010-01-14
申请人： Xiangdong Chen , Weipeng Li , Anda C. Mocuta , Dae-Gyu Park , Melanie J. Sherony , Kenneth J. Stein , Haizhou Yin , Franck Arnaud , Jin-Ping Han , Laegu Kang , Yong Meng Lee , Young Way Teh , Voon-Yew Thean , Da Zhang
发明人： Xiangdong Chen , Weipeng Li , Anda C. Mocuta , Dae-Gyu Park , Melanie J. Sherony , Kenneth J. Stein , Haizhou Yin , Franck Arnaud , Jin-Ping Han , Laegu Kang , Yong Meng Lee , Young Way Teh , Voon-Yew Thean , Da Zhang
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L29/7843
摘要： An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.
摘要翻译：集成电路结构包括衬底和衬底上或衬底中的至少一对互补晶体管。该对互补晶体管包括第一晶体管和第二晶体管。该结构还包括第一晶体管和第二晶体管上的第一应力产生层，以及在第一晶体管和第二晶体管上的第一应力产生层上的第二应力产生层。第一应力产生层在第一晶体管和第二晶体管上施加拉伸应变力。第二应力产生层对第一应力产生层，第一晶体管和第二晶体管施加压缩应变力。

4. 发明授权

US08106462B2 Balancing NFET and PFET performance using straining layers 失效
标题翻译：使用应变层平衡NFET和PFET性能
公开(公告)号：US08106462B2
公开(公告)日：2012-01-31
申请号：US12687374
申请日：2010-01-14
申请人： Xiangdong Chen , Weipeng Li , Anda C. Mocuta , Dae-Gyu Park , Melanie J. Sherony , Kenneth J. Stein , Haizhou Yin , Franck Arnaud , Jin-Ping Han , Laegu Kang , Yong Meng Lee , Young Way Teh , Voon-Yew Thean , Da Zhang
发明人： Xiangdong Chen , Weipeng Li , Anda C. Mocuta , Dae-Gyu Park , Melanie J. Sherony , Kenneth J. Stein , Haizhou Yin , Franck Arnaud , Jin-Ping Han , Laegu Kang , Yong Meng Lee , Young Way Teh , Voon-Yew Thean , Da Zhang
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L29/7843
摘要： An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.
摘要翻译：集成电路结构包括衬底和衬底上或衬底中的至少一对互补晶体管。该对互补晶体管包括第一晶体管和第二晶体管。该结构还包括第一晶体管和第二晶体管上的第一应力产生层，以及在第一晶体管和第二晶体管上的第一应力产生层上的第二应力产生层。第一应力产生层在第一晶体管和第二晶体管上施加拉伸应变力。第二应力产生层对第一应力产生层，第一晶体管和第二晶体管施加压缩应变力。

5. 发明授权

US07893502B2 Threshold voltage improvement employing fluorine implantation and adjustment oxide layer 有权
标题翻译：使用氟注入和调整氧化物层的阈值电压改善
公开(公告)号：US07893502B2
公开(公告)日：2011-02-22
申请号：US12465908
申请日：2009-05-14
申请人： Weipeng Li , Dae-Gyu Park , Melanie J. Sherony , Jin-Ping Han , Yong Meng Lee
发明人： Weipeng Li , Dae-Gyu Park , Melanie J. Sherony , Jin-Ping Han , Yong Meng Lee
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807
摘要： An epitaxial semiconductor layer may be formed in a first area reserved for p-type field effect transistors. An ion implantation mask layer is formed and patterned to provide an opening in the first area, while blocking at least a second area reserved for n-type field effect transistors. Fluorine is implanted into the opening to form an epitaxial fluorine-doped semiconductor layer and an underlying fluorine-doped semiconductor layer in the first area. A composite gate stack including a high-k gate dielectric layer and an adjustment oxide layer is formed in the first and second area. P-type and n-type field effect transistors (FET's) are formed in the first and second areas, respectively. The epitaxial fluorine-doped semiconductor layer and the underlying fluorine-doped semiconductor layer compensate for the reduction of the decrease in the threshold voltage in the p-FET by the adjustment oxide portion directly above.
摘要翻译：可以在为p型场效应晶体管保留的第一区域中形成外延半导体层。形成离子注入掩模层并图案化以在第一区域中提供开口，同时阻挡至少为n型场效应晶体管保留的第二区域。将氟注入到开口中以在第一区域中形成外延氟掺杂半导体层和下面的掺氟半导体层。在第一和第二区域中形成包括高k栅极电介质层和调整氧化物层的复合栅极堆叠。 P型和n型场效应晶体管（FET）分别形成在第一和第二区域中。外延氟掺杂半导体层和下面的掺氟半导体层通过直接在上面的调整氧化物部分来补偿p-FET中阈值电压的降低。

6. 发明申请

US20120273894A1 HIGH PRESSURE DEUTERIUM TREATMENT FOR SEMICONDUCTOR/HIGH-K INSULATOR INTERFACE 有权
标题翻译：用于半导体/高K绝缘体接口的高压电解铜处理
公开(公告)号：US20120273894A1
公开(公告)日：2012-11-01
申请号：US13094873
申请日：2011-04-27
申请人： Xiangdong Chen , Laegu Kang , Weipeng Li , Dae-Gyu Park , Melanie J. Sherony
发明人： Xiangdong Chen , Laegu Kang , Weipeng Li , Dae-Gyu Park , Melanie J. Sherony
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/28176 , H01L21/3003 , H01L21/8258 , H01L29/1054 , H01L29/665 , H01L29/7843
摘要： An integrated circuit structure comprises at least one pair of complementary transistors on a substrate. The pair of complementary transistors includes a first transistor and a second transistor. In addition, only one stress-producing layer is on the first transistor and the second transistor and applies tensile strain force on the first transistor and the second transistor. The first transistor has a first channel region, a gate insulator on the first channel region, and a deuterium region between the first channel region and the gate insulator. The second transistor has a germanium doped channel region, as well as the same gate insulator on the germanium doped channel region, and the same deuterium region between the germanium doped channel region and the gate insulator.
摘要翻译：集成电路结构在衬底上包括至少一对互补晶体管。一对互补晶体管包括第一晶体管和第二晶体管。此外，在第一晶体管和第二晶体管上只有一个应力产生层，并且在第一晶体管和第二晶体管上施加拉伸应变力。第一晶体管具有第一沟道区，第一沟道区上的栅极绝缘体，以及第一沟道区和栅绝缘体之间的氘区。第二晶体管具有锗掺杂沟道区以及锗掺杂沟道区上的相同栅极绝缘体以及锗掺杂沟道区和栅绝缘体之间的相同氘区。

7. 发明授权

US06750109B2 Halo-free non-rectifying contact on chip with halo source/drain diffusion 有权
标题翻译：光环/漏极扩散芯片上的无光非整流接触
公开(公告)号：US06750109B2
公开(公告)日：2004-06-15
申请号：US10064305
申请日：2002-07-01
申请人： James A. Culp , Jawahar P. Nayak , Werner A. Rausch , Melanie J. Sherony , Steven H. Voldman , Noah D. Zamdmer
发明人： James A. Culp , Jawahar P. Nayak , Werner A. Rausch , Melanie J. Sherony , Steven H. Voldman , Noah D. Zamdmer
IPC分类号： H01L21331
CPC分类号： H01L29/4966 , H01L29/1083 , H01L29/7835
摘要： A semiconductor chip includes a semiconductor substrate having a rectifying contact diffusion and a non-rectifying contact diffusion. A halo diffusion is adjacent the rectifying contact diffusion and no halo diffusion is adjacent the non-rectifying contact diffusion. The rectifying contact diffusion can be a source/drain diffusion of an FET to improve resistance to punch-through. The non-rectifying contact diffusion may be an FET body contact, a lateral diode contact, or a resistor or capacitor contact. Avoiding a halo for non-rectifying contacts reduces series resistance and improves device characteristics. In another embodiment on a chip having devices with halos adjacent diffusions, no halo diffusion is adjacent a rectifying contact diffusion of a lateral diode, significantly improving ideality of the diode and increasing breakdown voltage.
摘要翻译：半导体芯片包括具有整流接触扩散和非整流接触扩散的半导体衬底。光晕扩散与整流接触扩散相邻，并且没有晕圈扩散与非整流接触扩散相邻。整流接触扩散可以是FET的源极/漏极扩散，以提高耐穿透性。非整流接触扩散可以是FET体接触，横向二极管接触或电阻或电容器接触。避免使用非整流触点的光圈可以降低串联电阻并提高器件特性。在具有相邻扩散的光晕的器件的芯片的另一实施例中，没有卤素扩散与横向二极管的整流接触扩散相邻，从而显着地提高了二极管的理想性并增加了击穿电压。

8. 发明授权

US08445969B2 High pressure deuterium treatment for semiconductor/high-K insulator interface 有权
标题翻译：用于半导体/高K绝缘子接口的高压氘处理
公开(公告)号：US08445969B2
公开(公告)日：2013-05-21
申请号：US13094873
申请日：2011-04-27
申请人： Xiangdong Chen , Laegu Kang , Weipeng Li , Dae-Gyu Park , Melanie J. Sherony
发明人： Xiangdong Chen , Laegu Kang , Weipeng Li , Dae-Gyu Park , Melanie J. Sherony
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/28176 , H01L21/3003 , H01L21/8258 , H01L29/1054 , H01L29/665 , H01L29/7843
摘要： An integrated circuit structure comprises at least one pair of complementary transistors on a substrate. The pair of complementary transistors includes a first transistor and a second transistor. In addition, only one stress-producing layer is on the first transistor and the second transistor and applies tensile strain force on the first transistor and the second transistor. The first transistor has a first channel region, a gate insulator on the first channel region, and a deuterium region between the first channel region and the gate insulator. The second transistor has a germanium doped channel region, as well as the same gate insulator on the germanium doped channel region, and the same deuterium region between the germanium doped channel region and the gate insulator.
摘要翻译：集成电路结构在衬底上包括至少一对互补晶体管。一对互补晶体管包括第一晶体管和第二晶体管。此外，在第一晶体管和第二晶体管上只有一个应力产生层，并且在第一晶体管和第二晶体管上施加拉伸应变力。第一晶体管具有第一沟道区，第一沟道区上的栅极绝缘体，以及第一沟道区和栅绝缘体之间的氘区。第二晶体管具有锗掺杂沟道区以及锗掺杂沟道区上的相同栅极绝缘体以及锗掺杂沟道区和栅绝缘体之间的相同氘区。

9. 发明申请

US20090166757A1 STRESS ENGINEERING FOR SRAM STABILITY 审中-公开
标题翻译：用于SRAM稳定性的应力工程
公开(公告)号：US20090166757A1
公开(公告)日：2009-07-02
申请号：US11964879
申请日：2007-12-27
申请人： Christopher V. Baiocco , Xiandong Chen , Young G. Ko , Melanie J. Sherony
发明人： Christopher V. Baiocco , Xiandong Chen , Young G. Ko , Melanie J. Sherony
IPC分类号： G06F17/50 , H01L27/11
CPC分类号： H01L27/1104 , G01R31/31816
摘要： A design structure embodied in a machine readable medium is provided for use in the design, manufacturing, and/or testing of Ics that include at least one SRAM cell. In particular, the present invention provides a design structure of an IC embodied in a machine readable medium, the IC including at least one SRAM cell with a gamma ratio of about 1 or greater. In the present invention, the gamma ratio is increased with degraded pFET device performance. Moreover, in the inventive IC, there is no stress liner boundary present in the SRAM region and ion variation for all devices is reduced as compared to that of a conventional SRAM structure. The present invention provides a design structure of an IC embodied in a machine readable medium, the IC comprising at least one static random access memory cell including at least one nFET and at least one pFET; and a continuous relaxed stressed liner located above and adjoining the at least one nFET and the at least one pFET.
摘要翻译：提供体现在机器可读介质中的设计结构用于设计，制造和/或测试包括至少一个SRAM单元的IC。特别地，本发明提供了体现在机器可读介质中的IC的设计结构，该IC包括至少一个具有大约1或更大的伽马比的SRAM单元。在本发明中，γ比随着pFET器件性能的降低而增加。此外，在本发明的IC中，SRAM区域中不存在应力衬垫边界，与常规SRAM结构相比，所有器件的离子变化都降低。本发明提供了体现在机器可读介质中的IC的设计结构，该IC包括至少一个包括至少一个nFET和至少一个pFET的静态随机存取存储器单元; 以及位于所述至少一个nFET和所述至少一个pFET之上并邻接所述至少一个nFET的连续松弛应力衬垫。

10. 发明申请

US20100289088A1 THRESHOLD VOLTAGE IMPROVEMENT EMPLOYING FLUORINE IMPLANTATION AND ADJUSTMENT OXIDE LAYER 有权
标题翻译：使用荧光植入和调整氧化层的阈值电压改进
公开(公告)号：US20100289088A1
公开(公告)日：2010-11-18
申请号：US12465908
申请日：2009-05-14
申请人： Weipeng Li , Dae-Gyu Park , Melanie J. Sherony , Jin-Ping Han , Yong Meng Lee
发明人： Weipeng Li , Dae-Gyu Park , Melanie J. Sherony , Jin-Ping Han , Yong Meng Lee
IPC分类号： H01L27/088 , H01L21/8236
CPC分类号： H01L21/823807
摘要： An epitaxial semiconductor layer may be formed in a first area reserved for p-type field effect transistors. An ion implantation mask layer is formed and patterned to provide an opening in the first area, while blocking at least a second area reserved for n-type field effect transistors. Fluorine is implanted into the opening to form an epitaxial fluorine-doped semiconductor layer and an underlying fluorine-doped semiconductor layer in the first area. A composite gate stack including a high-k gate dielectric layer and an adjustment oxide layer is formed in the first and second area. P-type and n-type field effect transistors (FET's) are formed in the first and second areas, respectively. The epitaxial fluorine-doped semiconductor layer and the underlying fluorine-doped semiconductor layer compensate for the reduction of the decrease in the threshold voltage in the p-FET by the adjustment oxide portion directly above.
摘要翻译：可以在为p型场效应晶体管保留的第一区域中形成外延半导体层。形成离子注入掩模层并图案化以在第一区域中提供开口，同时阻挡至少为n型场效应晶体管保留的第二区域。将氟注入到开口中以在第一区域中形成外延氟掺杂半导体层和下面的掺氟半导体层。在第一和第二区域中形成包括高k栅极电介质层和调整氧化物层的复合栅极堆叠。 P型和n型场效应晶体管（FET）分别形成在第一和第二区域中。外延氟掺杂半导体层和下面的掺氟半导体层通过直接在上面的调整氧化物部分来补偿p-FET中阈值电压的降低。

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