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1. 发明申请

US20090166757A1 STRESS ENGINEERING FOR SRAM STABILITY 审中-公开
标题翻译：用于SRAM稳定性的应力工程
公开(公告)号：US20090166757A1
公开(公告)日：2009-07-02
申请号：US11964879
申请日：2007-12-27
申请人： Christopher V. Baiocco , Xiandong Chen , Young G. Ko , Melanie J. Sherony
发明人： Christopher V. Baiocco , Xiandong Chen , Young G. Ko , Melanie J. Sherony
IPC分类号： G06F17/50 , H01L27/11
CPC分类号： H01L27/1104 , G01R31/31816
摘要： A design structure embodied in a machine readable medium is provided for use in the design, manufacturing, and/or testing of Ics that include at least one SRAM cell. In particular, the present invention provides a design structure of an IC embodied in a machine readable medium, the IC including at least one SRAM cell with a gamma ratio of about 1 or greater. In the present invention, the gamma ratio is increased with degraded pFET device performance. Moreover, in the inventive IC, there is no stress liner boundary present in the SRAM region and ion variation for all devices is reduced as compared to that of a conventional SRAM structure. The present invention provides a design structure of an IC embodied in a machine readable medium, the IC comprising at least one static random access memory cell including at least one nFET and at least one pFET; and a continuous relaxed stressed liner located above and adjoining the at least one nFET and the at least one pFET.
摘要翻译：提供体现在机器可读介质中的设计结构用于设计，制造和/或测试包括至少一个SRAM单元的IC。特别地，本发明提供了体现在机器可读介质中的IC的设计结构，该IC包括至少一个具有大约1或更大的伽马比的SRAM单元。在本发明中，γ比随着pFET器件性能的降低而增加。此外，在本发明的IC中，SRAM区域中不存在应力衬垫边界，与常规SRAM结构相比，所有器件的离子变化都降低。本发明提供了体现在机器可读介质中的IC的设计结构，该IC包括至少一个包括至少一个nFET和至少一个pFET的静态随机存取存储器单元; 以及位于所述至少一个nFET和所述至少一个pFET之上并邻接所述至少一个nFET的连续松弛应力衬垫。

2. 发明授权

US07471548B2 Structure of static random access memory with stress engineering for stability 有权
标题翻译：具有应力工程稳定性的静态随机存取存储器的结构
公开(公告)号：US07471548B2
公开(公告)日：2008-12-30
申请号：US11611569
申请日：2006-12-15
申请人： Christopher V. Baiocco , Xiangdong Chen , Young G. Ko , Melanie J. Sherony
发明人： Christopher V. Baiocco , Xiangdong Chen , Young G. Ko , Melanie J. Sherony
IPC分类号： G11C11/412 , H01L29/78
CPC分类号： H01L27/1104 , H01L27/11 , Y10S257/903
摘要： An integrated circuit (IC) is provided that includes at least one static random access memory (SRAM) cell wherein performance of the SRAM cell is enhanced, yet with good stability and writability. In particular, the present invention provides an IC including at least one SRAM cell wherein the gamma ratio is about 1 or greater. The gamma ratio is increased with degraded pFET device performance. Morever, in the inventive IC there is no stress liner boundary present in the SRAM region and ion variation for all devices is reduced as compared to that of a conventional SRAM structure. The present invention provides an integrated circuit (IC) that comprises at least one SRAM cell including at least one nFET and at least one pFET; and a continuous relaxed stressed liner located above and adjoining the nFET and the pFET.
摘要翻译：提供了一种集成电路（IC），其包括至少一个静态随机存取存储器（SRAM）单元，其中提高了SRAM单元的性能，但具有良好的稳定性和可写性。特别地，本发明提供一种包括至少一个SRAM单元的IC，其中伽马比为约1或更大。 γ比值随着pFET器件性能的降低而增加。更重要的是，在本发明的IC中，在SRAM区域中不存在应力衬垫边界，并且与常规SRAM结构相比，所有器件的离子变化都减小了。本发明提供一种集成电路（IC），其包括至少一个包含至少一个nFET和至少一个pFET的SRAM单元; 以及位于nFET和pFET上方并与其相邻的连续松弛应力衬垫。

3. 发明申请

US20080142895A1 STRESS ENGINEERING FOR SRAM STABILITY 有权
标题翻译：用于SRAM稳定性的应力工程
公开(公告)号：US20080142895A1
公开(公告)日：2008-06-19
申请号：US11611569
申请日：2006-12-15
申请人： Christopher V. Baiocco , Xiangdong Chen , Young G. Ko , Melanie J. Sherony
发明人： Christopher V. Baiocco , Xiangdong Chen , Young G. Ko , Melanie J. Sherony
IPC分类号： H01L27/11
CPC分类号： H01L27/1104 , H01L27/11 , Y10S257/903
摘要： An IC is provided that includes at least one SRAM cell in which the performance of the SRAM cell is enhanced, yet maintaining good stability and writability. In particular, the present invention provides an IC including at least one SRAM cell wherein the gamma ratio is about 1 or greater. In the present invention, the gamma ratio is increased with degraded pFET device performance. Moreover, in the inventive IC there is no stress liner boundary present in the SRAM region and ion variation for all devices is reduced as compared to that of a conventional SRAM structure. The present invention, solves the above by providing an integrated circuit (IC) that comprises at least one static random access memory cell including at least one nFET and at least one pFET; and a continuous relaxed stressed liner located above and adjoining the at least one nFET and the at least one pFET.
摘要翻译：提供了一种IC，其包括至少一个SRAM单元，其中SRAM单元的性能得到增强，同时保持良好的稳定性和可编写性。特别地，本发明提供一种包括至少一个SRAM单元的IC，其中伽马比为约1或更大。在本发明中，γ比随着pFET器件性能的降低而增加。此外，在本发明的IC中，在SRAM区域中不存在应力衬垫边界，并且与常规SRAM结构相比，所有器件的离子变化都减小了。本发明通过提供一种包括至少一个包括至少一个nFET和至少一个pFET的静态随机存取存储器的集成电路（IC）来解决上述问题，以及位于所述至少一个nFET和所述至少一个pFET之上并邻接所述至少一个nFET的连续松弛应力衬垫。

4. 发明申请

US20080142896A1 SELECTIVE STRESS ENGINEERING FOR SRAM STABILITY IMPROVEMENT 失效
标题翻译：用于SRAM稳定性改进的选择性应力工程
公开(公告)号：US20080142896A1
公开(公告)日：2008-06-19
申请号：US11612643
申请日：2006-12-19
申请人： Xiangdong Chen , Young G. Ko , Haining Yang
发明人： Xiangdong Chen , Young G. Ko , Haining Yang
IPC分类号： H01L27/11
CPC分类号： H01L27/11 , H01L29/7847 , Y10S257/903
摘要： An integrated circuit (IC) structure including a SRAM cell is provided in which the performance of the pass-gate transistors is degraded in order to increase the beta ratio of the transistors within the SRAM cell. In particular, the increased beta ratio is obtained in the present invention by intentionally improving only the performance of the pull-down transistors, while degrading the performance of the pass-gate transistors. This result is achieved in the present invention by implementing stress memorization technique on logic complementary metal oxide semiconductor (CMOS) nFETs and SRAM pull-down transistors to improve the nFET performance. The stress memorization technique is not performed at the pFET region to avoid performance degradation as well as at the SRAM pass-gate transistors to avoid the improvement. With performance improvement at the pull-down transistors and no performance improvement at the pass-gate transistors, the beta ratio of the SRAM transistors is improved.
摘要翻译：提供了包括SRAM单元的集成电路（IC）结构，其中栅极晶体管的性能降低，以便增加SRAM单元内的晶体管的β比。特别地，本发明中通过有意地仅改善下拉晶体管的性能，同时降低栅极晶体管的性能来获得增加的β比。通过在逻辑互补金属氧化物半导体（CMOS）nFET和SRAM下拉晶体管上实施应力记忆技术来提高nFET性能，在本发明中实现了该结果。在pFET区域不进行应力记忆技术，以避免性能下降以及在SRAM栅极晶体管中避免改进。随着下拉晶体管的性能改善，传递栅极晶体管的性能得不到改善，SRAM晶体管的β比率得到了改善。

5. 发明授权

US07388267B1 Selective stress engineering for SRAM stability improvement 失效
标题翻译： SRAM稳定性改进的选择性应力工程
公开(公告)号：US07388267B1
公开(公告)日：2008-06-17
申请号：US11612643
申请日：2006-12-19
申请人： Xiangdong Chen , Young G. Ko , Haining Yang
发明人： Xiangdong Chen , Young G. Ko , Haining Yang
IPC分类号： H01L29/78
CPC分类号： H01L27/11 , H01L29/7847 , Y10S257/903
摘要： An integrated circuit (IC) structure including a SRAM cell is provided in which the performance of the pass-gate transistors is degraded in order to increase the beta ratio of the transistors within the SRAM cell. In particular, the increased beta ratio is obtained in the present invention by intentionally improving only the performance of the pull-down transistors, while degrading the performance of the pass-gate transistors. This result is achieved in the present invention by implementing stress memorization technique on logic complementary metal oxide semiconductor (CMOS) nFETs and SRAM pull-down transistors to improve the nFET performance. The stress memorization technique is not performed at the pFET region to avoid performance degradation as well as at the SRAM pass-gate transistors to avoid the improvement. With performance improvement at the pull-down transistors and no performance improvement at the pass-gate transistors, the beta ratio of the SRAM transistors is improved.
摘要翻译：提供了包括SRAM单元的集成电路（IC）结构，其中栅极晶体管的性能降低，以便增加SRAM单元内的晶体管的β比。特别地，本发明中通过有意地仅改善下拉晶体管的性能，同时降低栅极晶体管的性能来获得增加的β比。通过在逻辑互补金属氧化物半导体（CMOS）nFET和SRAM下拉晶体管上实施应力记忆技术来提高nFET性能，在本发明中实现了该结果。在pFET区域不进行应力记忆技术，以避免性能下降以及在SRAM栅极晶体管中避免改进。随着下拉晶体管的性能改善，传递栅极晶体管的性能得不到改善，SRAM晶体管的β比率得到了改善。

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