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1. 发明授权

US08716081B2 Capacitor top plate over source/drain to form a 1T memory device 有权
标题翻译：源极/漏极上的电容器顶板形成1T存储器件
公开(公告)号：US08716081B2
公开(公告)日：2014-05-06
申请号：US11686475
申请日：2007-03-15
申请人： Lee Wee Teo , Yong Meng Lee , Zhao Lun , Chung Woh Lai , Shyue Seng Tan , Jeffrey Chee , Shailendra Mishra , Johnny Widodo
发明人： Lee Wee Teo , Yong Meng Lee , Zhao Lun , Chung Woh Lai , Shyue Seng Tan , Jeffrey Chee , Shailendra Mishra , Johnny Widodo
IPC分类号： H01L29/76
CPC分类号： H01L29/94 , H01L27/10805 , H01L27/1085 , H01L27/11
摘要： A method and structure for a memory device, such as a 1T-SRAM, having a capacitor top plate directly over a doped bottom plate region. An example device comprises the following. An isolation film formed as to surround an active area on a substrate. A gate dielectric and gate electrode formed over a portion of the active area. A source element and a drain element in the substrate adjacent to the gate electrode. The drain element is comprised of a drain region and a bottom plate region. The drain region is between the bottom plate region and the gate structure. A capacitor dielectric and a capacitor top plate are over at least portions of the bottom plate region.
摘要翻译：用于诸如1T-SRAM的存储器件的方法和结构，其具有直接在掺杂底板区域上方的电容器顶板。示例设备包括以下。形成为围绕衬底上的有源区域的隔离膜。形成在有源区域的一部分上的栅极电介质和栅电极。与栅电极相邻的衬底中的源极元件和漏极元件。漏极元件由漏区和底板区组成。漏极区域位于底板区域和栅极结构之间。电容器电介质和电容器顶板在底板区域的至少部分上方。

2. 发明授权

US07977185B2 Method and apparatus for post silicide spacer removal 有权
标题翻译：后硅化物间隔物去除的方法和装置
公开(公告)号：US07977185B2
公开(公告)日：2011-07-12
申请号：US11164417
申请日：2005-11-22
申请人： Brian J. Greene , Chung Woh Lai , Yong Meng Lee , Wenhe Lin , Siddhartha Panda , Kern Rim , Young Way Teh
发明人： Brian J. Greene , Chung Woh Lai , Yong Meng Lee , Wenhe Lin , Siddhartha Panda , Kern Rim , Young Way Teh
IPC分类号： H01L21/33
CPC分类号： H01L21/31116 , H01L21/31144 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： A method (and apparatus) of post silicide spacer removal includes preventing damage to the silicide spacer through the use of at least one of an oxide layer and a nitride layer.
摘要翻译：后硅化物间隔物去除的方法（和装置）包括通过使用氧化物层和氮化物层中的至少一种来防止对硅化物间隔物的损害。

3. 发明授权

US07737009B2 Method of implanting a non-dopant atom into a semiconductor device 有权
标题翻译：将非掺杂剂原子注入到半导体器件中的方法
公开(公告)号：US07737009B2
公开(公告)日：2010-06-15
申请号：US11836008
申请日：2007-08-08
申请人： Richard Lindsay , Yong Meng Lee , Manfred Eller
发明人： Richard Lindsay , Yong Meng Lee , Manfred Eller
IPC分类号： H01L21/265
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/26566 , H01L21/2658 , H01L21/26586 , H01L21/76237 , H01L29/1083 , H01L29/6659 , H01L29/7833
摘要： A method of forming an isolation trench structure is disclosed, the method includes forming an isolation trench in a semiconductor body associated with an isolation region, and implanting a non-dopant atom into the isolation trench, thereby forming a region to modify the halo profile in the semiconductor body. Subsequently, the isolation trench is filled with a dielectric material.
摘要翻译：公开了一种形成隔离沟槽结构的方法，该方法包括在与隔离区相关联的半导体本体中形成隔离沟槽，并将非掺杂剂原子注入到隔离沟槽中，从而形成一个区域以修改光刻轮廓半导体体。随后，隔离沟槽填充有电介质材料。

4. 发明申请

US20100102393A1 METAL GATE TRANSISTORS 审中-公开
标题翻译：金属栅极晶体管
公开(公告)号：US20100102393A1
公开(公告)日：2010-04-29
申请号：US12260095
申请日：2008-10-29
申请人： James Yong Meng LEE , Jin-Ping HAN , Voon-Yew THEAN
发明人： James Yong Meng LEE , Jin-Ping HAN , Voon-Yew THEAN
IPC分类号： H01L27/092 , H01L21/4763
CPC分类号： H01L21/823807 , H01L29/1054 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： An integrated circuit that includes a substrate having first and second active regions is disclosed. A first transistor of a first type and a second transistor of a second type are disposed in the first and second active regions respectively. Each transistor includes a gate stack having a metal gate electrode over a gate dielectric layer. First and second gate threshold voltage adjusting (GTVA) layers contacting first and second gate dielectric layer of the first and second transistors are provided. The first GTVA layer tunes a gate threshold voltage of the first transistor. A channel of the second transistor includes dopants to tune the gate threshold voltage of the second transistor.
摘要翻译：公开了一种包括具有第一和第二有源区的衬底的集成电路。第一类型的第一晶体管和第二类型的第二晶体管分别设置在第一和第二有源区中。每个晶体管包括在栅极介电层上方具有金属栅电极的栅极堆叠。提供了接触第一和第二晶体管的第一和第二栅极介电层的第一和第二栅极阈值电压调节（GTVA）层。第一GTVA层调谐第一晶体管的栅极阈值电压。第二晶体管的沟道包括用于调谐第二晶体管的栅极阈值电压的掺杂剂。

5. 发明授权

US07615427B2 Spacer-less low-k dielectric processes 有权
标题翻译：无隔离低k介电过程
公开(公告)号：US07615427B2
公开(公告)日：2009-11-10
申请号：US11447565
申请日：2006-06-05
申请人： Yong Meng Lee , Young Way Teh , Chung Woh Lai , Wenhe Lin , Khee Yong Lim , Wee Leng Tan , Hui Peng Koh , John Sudijono , Liang Choo Hsia
发明人： Yong Meng Lee , Young Way Teh , Chung Woh Lai , Wenhe Lin , Khee Yong Lim , Wee Leng Tan , Hui Peng Koh , John Sudijono , Liang Choo Hsia
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/823864 , H01L21/823871 , H01L29/6653 , H01L29/6659 , H01L29/7833
摘要： A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.
摘要翻译：第一示例性实施例提供了从栅极去除第一间隔物并将低k材料并入到ILD层中以提高器件性能的方法。第二示例性实施例包括用低k间隔物硅化后替换第一间隔物。这用于减小寄生电容。此外，通过仅在硅化后实现低k间隔物，实施方案的低k间隔物不受多次高剂量离子注入和抗蚀剂剥离步骤的影响。示例性实施例可以提高设备性能，例如边缘振荡器的性能。

6. 发明申请

US20090261448A1 METHOD OF FORMING SHALLOW TRENCH ISOLATION STRUCTURES FOR INTEGRATED CIRCUITS 有权
标题翻译：形成集成电路的浅层隔离结构的方法
公开(公告)号：US20090261448A1
公开(公告)日：2009-10-22
申请号：US12107751
申请日：2008-04-22
申请人： Shailendra MISHRA , James Yong Meng LEE , Zhao LUN , Wen Zhi GAO , Chung Woh LAI , Huang LIU , Johnny WIDODO , Liang Choo HSIA
发明人： Shailendra MISHRA , James Yong Meng LEE , Zhao LUN , Wen Zhi GAO , Chung Woh LAI , Huang LIU , Johnny WIDODO , Liang Choo HSIA
IPC分类号： H01L21/762 , H01L23/58
CPC分类号： H01L21/76229
摘要： A method of forming shallow trench isolation (STI) structures using a multi-step etch process is disclosed. The first etch step is performed by selectively etching the substrate at a substantially higher etching rate than the mask layer to form preliminary openings having steep taper angles. The second etch step is performed by non-selectively etching the substrate to deepen the preliminary openings to form STI gaps with substantially flat bottoms.
摘要翻译：公开了一种使用多步蚀刻工艺形成浅沟槽隔离（STI）结构的方法。通过以比掩模层更高的蚀刻速率选择性地蚀刻衬底来进行第一蚀刻步骤，以形成具有陡峭锥角的预备开口。第二蚀刻步骤是通过非选择性蚀刻衬底来加深初步开口以形成具有基本平坦底部的STI间隙。

7. 发明申请

US20090206408A1 NESTED AND ISOLATED TRANSISTORS WITH REDUCED IMPEDANCE DIFFERENCE 有权
标题翻译：具有降低阻抗差的绝缘和隔离晶体管
公开(公告)号：US20090206408A1
公开(公告)日：2009-08-20
申请号：US12031693
申请日：2008-02-14
申请人： Johnny WIDODO , Liang Choo HSIA , James Yong Meng LEE , Wen Zhi GAO , Zhao LUN , Huang LIU , Chung Woh LAI , Shailendra MISHRA , Yew Tuck CHOW , Fang CHEN , Shiang Yang ONG
发明人： Johnny WIDODO , Liang Choo HSIA , James Yong Meng LEE , Wen Zhi GAO , Zhao LUN , Huang LIU , Chung Woh LAI , Shailendra MISHRA , Yew Tuck CHOW , Fang CHEN , Shiang Yang ONG
IPC分类号： H01L29/00 , H01L21/44
CPC分类号： H01L29/41783 , H01L21/28518 , H01L21/823418 , H01L21/823425 , H01L21/823443 , H01L29/41725 , H01L29/665 , H01L29/7833
摘要： A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rs of transistors in iso and nested regions can be matched.
摘要翻译：在金属硅化物接触之后形成金属层，例如硅的处理层。对硅和金属层进行退火以增加金属硅化物接触的厚度。通过选择性地增加硅化物接触的厚度，可以匹配异和嵌套区域中的晶体管的Rs。

8. 发明申请

US20080315317A1 SEMICONDUCTOR SYSTEM HAVING COMPLEMENTARY STRAINED CHANNELS 审中-公开
标题翻译：具有补充应变通道的半导体系统
公开(公告)号：US20080315317A1
公开(公告)日：2008-12-25
申请号：US11767449
申请日：2007-06-22
申请人： Chung Woh Lai , Yong Meng Lee , Wenhe Lin , Khee Yong Lim , Young Way Teh , Wee Leng Tan , Hui Peng Koh , John Sudijono , Liang-Choo Hsia
发明人： Chung Woh Lai , Yong Meng Lee , Wenhe Lin , Khee Yong Lim , Young Way Teh , Wee Leng Tan , Hui Peng Koh , John Sudijono , Liang-Choo Hsia
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/31155 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/66606 , H01L29/7843
摘要： A semiconductor system is provided including providing a semiconductor substrate; forming PMOS and NMOS transistors in and on the semiconductor substrate; forming a tensile strained layer on the semiconductor substrate; and relaxing the tensile strained layer around the PMOS transistor.
摘要翻译：提供一种半导体系统，包括提供半导体衬底; 在半导体衬底中形成PMOS和NMOS晶体管; 在半导体衬底上形成拉伸应变层; 并放宽PMOS晶体管周围的拉伸应变层。

9. 发明申请

US20080048269A1 METHOD OF FABRICATING STRUCTURE FOR INTEGRATED CIRCUIT INCORPORATING HYBRID ORIENTATION TECHNOLOGY AND TRENCH ISOLATION REGIONS 审中-公开
标题翻译：整合电路结合混合方向技术与热分解区域的方法
公开(公告)号：US20080048269A1
公开(公告)日：2008-02-28
申请号：US11467325
申请日：2006-08-25
申请人： Xiangdong Chen , Yong Meng Lee
发明人： Xiangdong Chen , Yong Meng Lee
IPC分类号： H01L29/94
CPC分类号： H01L21/823807 , H01L21/823878 , H01L27/0922
摘要： An embodiment of the present invention discloses a method of fabricating a structure for an integrated circuit incorporating hybrid orientation technology (HOT) and trench isolation regions. The structure of the integrated circuit comprising: a substrate with a first silicon layer of a first crystalline orientation and a second silicon layer, of a second crystalline orientation different from the first crystalline orientation, disposed on the first silicon layer; a dielectric layer on the substrate; a first silicon active trench region, having first crystalline orientation, extending to the first silicon layer; a second silicon active trench region, having the second crystalline orientation, extending to the second silicon layer, the first silicon active region electrically isolated from the second silicon active region by a portion of the dielectric layer; a first transistor on the first silicon active region; and a second transistor on the second silicon active region.
摘要翻译：本发明的实施例公开了一种制造用于集成混合取向技术（HOT）和沟槽隔离区域的集成电路的结构的方法。所述集成电路的结构包括：设置在所述第一硅层上的具有第一晶体取向的第一硅层和与所述第一晶体取向不同的第二晶体取向的第二硅层的衬底; 基底上的电介质层; 具有第一晶体取向的第一硅有源沟槽区，延伸到第一硅层; 具有第二晶体取向的第二硅有源沟槽区延伸到第二硅层，第一硅有源区通过介电层的一部分与第二硅有源区电隔离; 在第一硅有源区上的第一晶体管; 以及在第二硅有源区上的第二晶体管。

10. 发明授权

US07256084B2 Composite stress spacer 有权
标题翻译：复合应力间隔
公开(公告)号：US07256084B2
公开(公告)日：2007-08-14
申请号：US11122667
申请日：2005-05-04
申请人： Khee Yong Lim , Wenhe Lin , Chung Woh Lai , Yong Meng Lee , Liang Choo Hsia , Young Way Teh , John Sudijono , Wee Leng Tan , Hui Peng Koh
发明人： Khee Yong Lim , Wenhe Lin , Chung Woh Lai , Yong Meng Lee , Liang Choo Hsia , Young Way Teh , John Sudijono , Wee Leng Tan , Hui Peng Koh
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823864
摘要： An example method embodiment forms spacers that create tensile stress on the substrate on both the PFET and NFET regions. We form PFET and NFET gates and form tensile spacers on the PFET and NFET gates. We implant first ions into the tensile PFET spacers to form neutralized stress PFET spacers. The neutralized stress PFET spacers relieve the tensile stress created by the tensile stress spacers on the substrate. This improves device performance.
摘要翻译：示例性方法实施例形成在PFET和NFET区域上在衬底上产生拉伸应力的间隔物。我们形成PFET和NFET栅极，并在PFET和NFET栅极上形成拉伸间隔物。我们将第一离子注入拉伸的PFET间隔物中以形成中和的应力PFET间隔物。中和的应力PFET间隔物减轻了由衬底上的拉伸应力间隔物产生的拉伸应力。这提高了设备性能。

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