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1. 发明申请

US20120273894A1 HIGH PRESSURE DEUTERIUM TREATMENT FOR SEMICONDUCTOR/HIGH-K INSULATOR INTERFACE 有权
标题翻译：用于半导体/高K绝缘体接口的高压电解铜处理
公开(公告)号：US20120273894A1
公开(公告)日：2012-11-01
申请号：US13094873
申请日：2011-04-27
申请人： Xiangdong Chen , Laegu Kang , Weipeng Li , Dae-Gyu Park , Melanie J. Sherony
发明人： Xiangdong Chen , Laegu Kang , Weipeng Li , Dae-Gyu Park , Melanie J. Sherony
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/28176 , H01L21/3003 , H01L21/8258 , H01L29/1054 , H01L29/665 , H01L29/7843
摘要： An integrated circuit structure comprises at least one pair of complementary transistors on a substrate. The pair of complementary transistors includes a first transistor and a second transistor. In addition, only one stress-producing layer is on the first transistor and the second transistor and applies tensile strain force on the first transistor and the second transistor. The first transistor has a first channel region, a gate insulator on the first channel region, and a deuterium region between the first channel region and the gate insulator. The second transistor has a germanium doped channel region, as well as the same gate insulator on the germanium doped channel region, and the same deuterium region between the germanium doped channel region and the gate insulator.
摘要翻译：集成电路结构在衬底上包括至少一对互补晶体管。一对互补晶体管包括第一晶体管和第二晶体管。此外，在第一晶体管和第二晶体管上只有一个应力产生层，并且在第一晶体管和第二晶体管上施加拉伸应变力。第一晶体管具有第一沟道区，第一沟道区上的栅极绝缘体，以及第一沟道区和栅绝缘体之间的氘区。第二晶体管具有锗掺杂沟道区以及锗掺杂沟道区上的相同栅极绝缘体以及锗掺杂沟道区和栅绝缘体之间的相同氘区。

2. 发明授权

US08106462B2 Balancing NFET and PFET performance using straining layers 失效
标题翻译：使用应变层平衡NFET和PFET性能
公开(公告)号：US08106462B2
公开(公告)日：2012-01-31
申请号：US12687374
申请日：2010-01-14
申请人： Xiangdong Chen , Weipeng Li , Anda C. Mocuta , Dae-Gyu Park , Melanie J. Sherony , Kenneth J. Stein , Haizhou Yin , Franck Arnaud , Jin-Ping Han , Laegu Kang , Yong Meng Lee , Young Way Teh , Voon-Yew Thean , Da Zhang
发明人： Xiangdong Chen , Weipeng Li , Anda C. Mocuta , Dae-Gyu Park , Melanie J. Sherony , Kenneth J. Stein , Haizhou Yin , Franck Arnaud , Jin-Ping Han , Laegu Kang , Yong Meng Lee , Young Way Teh , Voon-Yew Thean , Da Zhang
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L29/7843
摘要： An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.
摘要翻译：集成电路结构包括衬底和衬底上或衬底中的至少一对互补晶体管。该对互补晶体管包括第一晶体管和第二晶体管。该结构还包括第一晶体管和第二晶体管上的第一应力产生层，以及在第一晶体管和第二晶体管上的第一应力产生层上的第二应力产生层。第一应力产生层在第一晶体管和第二晶体管上施加拉伸应变力。第二应力产生层对第一应力产生层，第一晶体管和第二晶体管施加压缩应变力。

3. 发明授权

US08445969B2 High pressure deuterium treatment for semiconductor/high-K insulator interface 有权
标题翻译：用于半导体/高K绝缘子接口的高压氘处理
公开(公告)号：US08445969B2
公开(公告)日：2013-05-21
申请号：US13094873
申请日：2011-04-27
申请人： Xiangdong Chen , Laegu Kang , Weipeng Li , Dae-Gyu Park , Melanie J. Sherony
发明人： Xiangdong Chen , Laegu Kang , Weipeng Li , Dae-Gyu Park , Melanie J. Sherony
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/28176 , H01L21/3003 , H01L21/8258 , H01L29/1054 , H01L29/665 , H01L29/7843
摘要： An integrated circuit structure comprises at least one pair of complementary transistors on a substrate. The pair of complementary transistors includes a first transistor and a second transistor. In addition, only one stress-producing layer is on the first transistor and the second transistor and applies tensile strain force on the first transistor and the second transistor. The first transistor has a first channel region, a gate insulator on the first channel region, and a deuterium region between the first channel region and the gate insulator. The second transistor has a germanium doped channel region, as well as the same gate insulator on the germanium doped channel region, and the same deuterium region between the germanium doped channel region and the gate insulator.
摘要翻译：集成电路结构在衬底上包括至少一对互补晶体管。一对互补晶体管包括第一晶体管和第二晶体管。此外，在第一晶体管和第二晶体管上只有一个应力产生层，并且在第一晶体管和第二晶体管上施加拉伸应变力。第一晶体管具有第一沟道区，第一沟道区上的栅极绝缘体，以及第一沟道区和栅绝缘体之间的氘区。第二晶体管具有锗掺杂沟道区以及锗掺杂沟道区上的相同栅极绝缘体以及锗掺杂沟道区和栅绝缘体之间的相同氘区。

4. 发明申请

US20110169096A1 BALANCING NFET AND PFET PERFORMANCE USING STRAINING LAYERS 失效
标题翻译：使用应变层平衡NFET和PFET性能
公开(公告)号：US20110169096A1
公开(公告)日：2011-07-14
申请号：US12687374
申请日：2010-01-14
申请人： Xiangdong Chen , Weipeng Li , Anda C. Mocuta , Dae-Gyu Park , Melanie J. Sherony , Kenneth J. Stein , Haizhou Yin , Franck Arnaud , Jin-Ping Han , Laegu Kang , Yong Meng Lee , Young Way Teh , Voon-Yew Thean , Da Zhang
发明人： Xiangdong Chen , Weipeng Li , Anda C. Mocuta , Dae-Gyu Park , Melanie J. Sherony , Kenneth J. Stein , Haizhou Yin , Franck Arnaud , Jin-Ping Han , Laegu Kang , Yong Meng Lee , Young Way Teh , Voon-Yew Thean , Da Zhang
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L29/7843
摘要： An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.
摘要翻译：集成电路结构包括衬底和衬底上或衬底中的至少一对互补晶体管。该对互补晶体管包括第一晶体管和第二晶体管。该结构还包括第一晶体管和第二晶体管上的第一应力产生层，以及在第一晶体管和第二晶体管上的第一应力产生层上的第二应力产生层。第一应力产生层在第一晶体管和第二晶体管上施加拉伸应变力。第二应力产生层对第一应力产生层，第一晶体管和第二晶体管施加压缩应变力。

5. 发明授权

US07893502B2 Threshold voltage improvement employing fluorine implantation and adjustment oxide layer 有权
标题翻译：使用氟注入和调整氧化物层的阈值电压改善
公开(公告)号：US07893502B2
公开(公告)日：2011-02-22
申请号：US12465908
申请日：2009-05-14
申请人： Weipeng Li , Dae-Gyu Park , Melanie J. Sherony , Jin-Ping Han , Yong Meng Lee
发明人： Weipeng Li , Dae-Gyu Park , Melanie J. Sherony , Jin-Ping Han , Yong Meng Lee
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807
摘要： An epitaxial semiconductor layer may be formed in a first area reserved for p-type field effect transistors. An ion implantation mask layer is formed and patterned to provide an opening in the first area, while blocking at least a second area reserved for n-type field effect transistors. Fluorine is implanted into the opening to form an epitaxial fluorine-doped semiconductor layer and an underlying fluorine-doped semiconductor layer in the first area. A composite gate stack including a high-k gate dielectric layer and an adjustment oxide layer is formed in the first and second area. P-type and n-type field effect transistors (FET's) are formed in the first and second areas, respectively. The epitaxial fluorine-doped semiconductor layer and the underlying fluorine-doped semiconductor layer compensate for the reduction of the decrease in the threshold voltage in the p-FET by the adjustment oxide portion directly above.
摘要翻译：可以在为p型场效应晶体管保留的第一区域中形成外延半导体层。形成离子注入掩模层并图案化以在第一区域中提供开口，同时阻挡至少为n型场效应晶体管保留的第二区域。将氟注入到开口中以在第一区域中形成外延氟掺杂半导体层和下面的掺氟半导体层。在第一和第二区域中形成包括高k栅极电介质层和调整氧化物层的复合栅极堆叠。 P型和n型场效应晶体管（FET）分别形成在第一和第二区域中。外延氟掺杂半导体层和下面的掺氟半导体层通过直接在上面的调整氧化物部分来补偿p-FET中阈值电压的降低。

6. 发明申请

US20100289088A1 THRESHOLD VOLTAGE IMPROVEMENT EMPLOYING FLUORINE IMPLANTATION AND ADJUSTMENT OXIDE LAYER 有权
标题翻译：使用荧光植入和调整氧化层的阈值电压改进
公开(公告)号：US20100289088A1
公开(公告)日：2010-11-18
申请号：US12465908
申请日：2009-05-14
申请人： Weipeng Li , Dae-Gyu Park , Melanie J. Sherony , Jin-Ping Han , Yong Meng Lee
发明人： Weipeng Li , Dae-Gyu Park , Melanie J. Sherony , Jin-Ping Han , Yong Meng Lee
IPC分类号： H01L27/088 , H01L21/8236
CPC分类号： H01L21/823807
摘要： An epitaxial semiconductor layer may be formed in a first area reserved for p-type field effect transistors. An ion implantation mask layer is formed and patterned to provide an opening in the first area, while blocking at least a second area reserved for n-type field effect transistors. Fluorine is implanted into the opening to form an epitaxial fluorine-doped semiconductor layer and an underlying fluorine-doped semiconductor layer in the first area. A composite gate stack including a high-k gate dielectric layer and an adjustment oxide layer is formed in the first and second area. P-type and n-type field effect transistors (FET's) are formed in the first and second areas, respectively. The epitaxial fluorine-doped semiconductor layer and the underlying fluorine-doped semiconductor layer compensate for the reduction of the decrease in the threshold voltage in the p-FET by the adjustment oxide portion directly above.
摘要翻译：可以在为p型场效应晶体管保留的第一区域中形成外延半导体层。形成离子注入掩模层并图案化以在第一区域中提供开口，同时阻挡至少为n型场效应晶体管保留的第二区域。将氟注入到开口中以在第一区域中形成外延氟掺杂半导体层和下面的掺氟半导体层。在第一和第二区域中形成包括高k栅极电介质层和调整氧化物层的复合栅极堆叠。 P型和n型场效应晶体管（FET）分别形成在第一和第二区域中。外延氟掺杂半导体层和下面的掺氟半导体层通过直接在上面的调整氧化物部分来补偿p-FET中阈值电压的降低。

7. 发明授权

US07867839B2 Method to reduce threshold voltage (Vt) in silicon germanium (SiGe), high-k dielectric-metal gate, p-type metal oxide semiconductor field effect transistors 有权
标题翻译：降低硅锗（SiGe），高k电介质金属栅极，p型金属氧化物半导体场效应晶体管中的阈值电压（Vt）的方法
公开(公告)号：US07867839B2
公开(公告)日：2011-01-11
申请号：US12176634
申请日：2008-07-21
申请人： Xiangdong Chen , Jong Ho Lee , Weipeng Li , Dae-Gyu Park , Kenneth J. Stein , Voon-Yew Thean
发明人： Xiangdong Chen , Jong Ho Lee , Weipeng Li , Dae-Gyu Park , Kenneth J. Stein , Voon-Yew Thean
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/2652 , H01L21/823807 , H01L29/1054
摘要： Disclosed are embodiments of a p-type, silicon germanium (SiGe), high-k dielectric-metal gate, metal oxide semiconductor field effect transistor (PFET) having an optimal threshold voltage (Vt), a complementary metal oxide semiconductor (CMOS) device that includes the PFET and methods of forming both the PFET alone and the CMOS device. The embodiments incorporate negatively charged ions (e.g., fluorine (F), chlorine (Cl), bromine (Br), iodine (I), etc.) into the high-k gate dielectric material of the PFET only so as to selectively adjust the negative Vt of the PFET (i.e., so as to reduce the negative Vt of the PFET).
摘要翻译：公开了具有最佳阈值电压（Vt）的p型硅锗（SiGe），高k电介质金属栅极，金属氧化物半导体场效应晶体管（PFET），互补金属氧化物半导体（CMOS）器件其包括PFET和形成PFET单独和CMOS器件的方法。实施例将带负电荷的离子（例如，氟（F），氯（Cl），溴（Br），碘（I）等）并入PFET的高k栅介质材料中，以便选择性地调节 PFET的负Vt（即，以减小PFET的负Vt）。

8. 发明申请

US20100013021A1 METHOD TO REDUCE THRESHOLD VOLTAGE (Vt) IN SILICON GERMANIUM (SIGE), HIGH-K DIELECTRIC-METAL GATE, P-TYPE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS 有权
标题翻译：降低硅锗（SIGE），高K介电金属栅，P型金属氧化物半导体场效应晶体管的阈值电压（Vt）的方法
公开(公告)号：US20100013021A1
公开(公告)日：2010-01-21
申请号：US12176634
申请日：2008-07-21
申请人： Xiangdong Chen , Jong Ho Lee , Weipeng Li , Dae-Gyu Park , Kenneth J. Stein , Voon-Yew Thean
发明人： Xiangdong Chen , Jong Ho Lee , Weipeng Li , Dae-Gyu Park , Kenneth J. Stein , Voon-Yew Thean
IPC分类号： H01L29/78 , H01L27/092 , H01L21/336 , H01L21/8238
CPC分类号： H01L21/823857 , H01L21/2652 , H01L21/823807 , H01L29/1054
摘要： Disclosed are embodiments of a p-type, silicon germanium (SiGe), high-k dielectric-metal gate, metal oxide semiconductor field effect transistor (PFET) having an optimal threshold voltage (Vt), a complementary metal oxide semiconductor (CMOS) device that includes the PFET and methods of forming both the PFET alone and the CMOS device. The embodiments incorporate negatively charged ions (e.g., fluorine (F), chlorine (Cl), bromine (Br), iodine (I), etc.) into the high-k gate dielectric material of the PFET only so as to selectively adjust the negative Vt of the PFET (i.e., so as to reduce the negative Vt of the PFET).
摘要翻译：公开了具有最佳阈值电压（Vt）的p型硅锗（SiGe），高k电介质金属栅极，金属氧化物半导体场效应晶体管（PFET），互补金属氧化物半导体（CMOS）器件其包括PFET和形成PFET单独和CMOS器件的方法。实施例将带负电荷的离子（例如，氟（F），氯（Cl），溴（Br），碘（I）等）并入PFET的高k栅介质材料中，以便选择性地调节 PFET的负Vt（即，以减小PFET的负Vt）。

9. 发明授权

US08298897B2 Asymmetric channel MOSFET 失效
公开(公告)号：US08298897B2
公开(公告)日：2012-10-30
申请号：US13428061
申请日：2012-03-23
申请人： Xiangdong Chen , Jie Deng , Weipeng Li , Deleep R. Nair , Jae-Eun Park , Daniel Tekleab , Xiaobin Yuan , Nam Sung Kim
发明人： Xiangdong Chen , Jie Deng , Weipeng Li , Deleep R. Nair , Jae-Eun Park , Daniel Tekleab , Xiaobin Yuan , Nam Sung Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/823412 , H01L21/28202 , H01L21/823807 , H01L29/1054 , H01L29/165 , H01L29/518 , H01L29/665 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/7833 , H01L29/7834 , H01L29/7835
摘要： A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.

10. 发明授权

US08237197B2 Asymmetric channel MOSFET 失效
标题翻译：非对称沟道MOSFET
公开(公告)号：US08237197B2
公开(公告)日：2012-08-07
申请号：US12831310
申请日：2010-07-07
申请人： Xiangdong Chen , Jie Deng , Weipeng Li , Deleep R. Nair , Jae-Eun Park , Daniel Tekleab , Xiaobin Yuan , Nam Sung Kim
发明人： Xiangdong Chen , Jie Deng , Weipeng Li , Deleep R. Nair , Jae-Eun Park , Daniel Tekleab , Xiaobin Yuan , Nam Sung Kim
IPC分类号： H01L29/66
CPC分类号： H01L21/823412 , H01L21/28202 , H01L21/823807 , H01L29/1054 , H01L29/165 , H01L29/518 , H01L29/665 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/7833 , H01L29/7834 , H01L29/7835
摘要： A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.
摘要翻译：场效应晶体管包括部分SiGe沟道，即包括位于栅极下方的SiGe沟道部分的沟道部分，以及位于漏极区域附近的位于栅电极的边缘下方的Si沟道部分。 SiGe沟道部分可以位于栅极电介质的正下方，或者可以位于位于栅极电介质正下方的Si沟道层下方。 Si沟道部分位于与SiGe沟道部分相同的深度处，并与晶体管的漏极区域接触。通过在漏极区附近提供Si沟道部分，晶体管的GIDL电流仅在断开状态下保持在与具有硅沟道的晶体管的GIDL电流相同的水平上。

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