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1. 发明授权

US06174779B1 Method for manufacturing a lateral bipolar transistor 失效
标题翻译：横向双极晶体管的制造方法
公开(公告)号：US06174779B1
公开(公告)日：2001-01-16
申请号：US09267775
申请日：1999-03-15
申请人： Tomoaki Shino , Takashi Yamada , Makoto Yoshimi , Shigeru Kawanaka , Hideaki Nii , Kazumi Inoh , Tsuneaki Fuse , Sadayuki Yoshitomi , Mamoru Terauchi
发明人： Tomoaki Shino , Takashi Yamada , Makoto Yoshimi , Shigeru Kawanaka , Hideaki Nii , Kazumi Inoh , Tsuneaki Fuse , Sadayuki Yoshitomi , Mamoru Terauchi
IPC分类号： H01L218228
CPC分类号： H01L29/66265 , H01L21/84 , H01L27/1203 , H01L29/7317
摘要： In a lateral bipolar transistor, its emitter region, base region, link base region, and so forth, are made in self alignment with side walls of masks by using partly overlapping two mask patterns. Therefore, not relying on the mask alignment accuracy, these regions are made in a precisely controlled positional relation. Thus, the lateral bipolar transistor, thus obtained, is reduced in parasitic resistance of the base and parasitic junction capacitance between the emitter and the base, and alleviated in variance of characteristics caused by fluctuation of the length of a link base region, length of the emitter-base junction and relative positions of the emitter and the collector, and can be manufactured with a high reproducibility.
摘要翻译：在横向双极晶体管中，通过使用部分重叠的两个掩模图案，其发射极区域，基极区域，链路基极区域等与掩模的侧壁自对准。因此，不依赖于掩模对准精度，这些区域被精确控制位置关系。因此，如此获得的横向双极晶体管的基极的寄生电阻和发射极与基极之间的寄生结电容减小，并且由于链路基极区域的长度的波动引起的特性的变化减轻，发射极 - 基极结和发射极和集电极的相对位置，并且可以以高再现性制造。

2. 发明授权

US06376897B2 Lateral bipolar transistor formed on an insulating layer 失效
标题翻译：形成在绝缘层上的侧面双极晶体管
公开(公告)号：US06376897B2
公开(公告)日：2002-04-23
申请号：US09314114
申请日：1999-05-19
申请人： Takashi Yamada , Hideaki Nii , Makoto Yoshimi , Tomoaki Shino , Kazumi Inoh , Shigeru Kawanaka , Tsuneaki Fuse , Sadayuki Yoshitomi
发明人： Takashi Yamada , Hideaki Nii , Makoto Yoshimi , Tomoaki Shino , Kazumi Inoh , Shigeru Kawanaka , Tsuneaki Fuse , Sadayuki Yoshitomi
IPC分类号： H01L2900
CPC分类号： H01L29/1008 , H01L29/7317
摘要： In a bipolar transistor improved to exhibit an excellent high-frequency property by decreasing the width of the intrinsic base with without increasing the base resistance, an emitter region, intrinsic base region and collector region are closely aligned on an insulating layer, and the intrinsic base region and the collector region make a protrusion projecting upward from the substrate surface. The protrusion has a width wider than the width of the intrinsic base region.
摘要翻译：在通过在不增加基极电阻的情况下减小本征基极的宽度而改善为显示优异的高频特性的双极晶体管中，发射极区域，本征基极区域和集电极区域在绝缘层上紧密对准，并且本征基极区域和集电区域形成从基板表面向上突出的突起。突起的宽度比本征基区宽度宽。

3. 发明授权

US08067963B2 Sense-amplifier control circuit and controlling method of sense amplifier 有权
标题翻译：感应放大器控制电路及读出放大器的控制方法
公开(公告)号：US08067963B2
公开(公告)日：2011-11-29
申请号：US12565478
申请日：2009-09-23
申请人： Seiro Imai , Tsuneaki Fuse
发明人： Seiro Imai , Tsuneaki Fuse
IPC分类号： G01R19/00
CPC分类号： H03F3/45179
摘要： A sense amplifier control circuit includes an initial-voltage setting circuit configured to set a control signal to an initial voltage, the control signal controlling a sensing operation of a sense amplifier, and a control-signal-level adjusting circuit configured to first change a voltage level of the control signal from the initial voltage to a voltage level at which the sense amplifier can execute a current sensing, and is configured to second change, after a predetermined time elapses, the voltage level at which the sense amplifier can execute the current sensing to a voltage level at which the sense amplifier can execute a voltage sensing.
摘要翻译：读出放大器控制电路包括初始电压设定电路，其被配置为将控制信号设定为初始电压，控制信号控制感测放大器的感测操作，以及控制信号电平调整电路，其被配置为首先改变电压控制信号的电平从初始电压到读出放大器可以执行电流检测的电压电平，并且被配置为在预定时间过去之后进行第二次改变，读出放大器可以执行电流感测的电压电平到感测放大器可以执行电压感测的电压电平。

4. 发明授权

US06466054B2 Level converter circuit 失效
标题翻译：电平转换电路
公开(公告)号：US06466054B2
公开(公告)日：2002-10-15
申请号：US09811699
申请日：2001-03-20
申请人： Atsushi Kameyama , Tsuneaki Fuse , Kazunori Ohuchi , Masako Yoshida
发明人： Atsushi Kameyama , Tsuneaki Fuse , Kazunori Ohuchi , Masako Yoshida
IPC分类号： H03K190175
CPC分类号： H03K19/018521
摘要： A level converter circuit includes two p-channel MOSFETs and two n-channel MOSFETs of gate-grounded type which receive complementary signals from a logic circuit, p-channel cross-coupled FETs, and n-channel cross-coupled FETs. The two FETs constructing each cross-coupled FETs can be driven by complementary inputs by supplying an output of the logic circuit operated on a low voltage and a logically inverted output thereof to each cross-coupled FETs via the gate-grounded FETs, and as a result, the gain characteristic of the cross-coupled FETs can be enhanced. The level converter circuit with low power consumption which has large tolerance for the element characteristic and converts a logic level which is as low as approximately 0.5V to approximately 1V to 3V which is a normal logic level.
摘要翻译：电平转换器电路包括两个p沟道MOSFET和栅极接地型的两个n沟道MOSFET，其接收来自逻辑电路，p沟道交叉耦合FET和n沟道交叉耦合FET的互补信号。构成每个交叉耦合FET的两个FET可以通过互补输入来驱动，该逻辑电路通过栅极接地的FET将低电压和逻辑反相输出的输出提供给每个交叉耦合的FET，并且作为结果，可以提高交叉耦合FET的增益特性。具有低功耗的电平转换器电路，其具有对元件特性的较大容差，并将低至约0.5V至大约1V至3V的逻辑电平转换为大约1V至3V，这是正常逻辑电平。

5. 发明授权

US6087893A Semiconductor integrated circuit having suppressed leakage currents 失效
标题翻译：具有抑制泄漏电流的半导体集成电路
公开(公告)号：US6087893A
公开(公告)日：2000-07-11
申请号：US956956
申请日：1997-10-23
申请人： Yukihito Oowaki , Tsuneaki Fuse
发明人： Yukihito Oowaki , Tsuneaki Fuse
IPC分类号： H01L27/092 , G05F1/46 , G05F3/02 , H01L21/8238 , H01L29/786 , H03K17/687 , H03K19/0175 , H03K19/0948
CPC分类号： G05F1/46
摘要： A stable high-speed integrated circuit driven by a wide range of low voltages and consuming low power. A MOSFET is used wherein signals are applied to its gate and body for forming a circuit block which comprises a transistor network and at least one buffer circuit. Each buffer circuit has at least two configurations. A plurality of circuit blocks are formed on the same IC chip. Any of the configurations of the buffer circuit may be selected according to the magnitude of the capacitance of the load driven by the circuit block.
摘要翻译：稳定的高速集成电路，由各种低电压驱动并消耗低功耗。使用MOSFET，其中向其栅极和主体施加信号以形成包括晶体管网络和至少一个缓冲电路的电路块。每个缓冲电路具有至少两种配置。在同一IC芯片上形成多个电路块。可以根据由电路块驱动的负载的电容的大小来选择缓冲电路的任何配置。

6. 发明授权

US5867040A Integrated circuit with stacked sub-circuits between Vcc and ground so as to conserve power and reduce the voltage across any one transistor 失效
标题翻译：集成电路，具有Vcc和地之间的堆叠子电路，以节省功率并降低任何一个晶体管的电压
公开(公告)号：US5867040A
公开(公告)日：1999-02-02
申请号：US593275
申请日：1996-01-29
申请人： Tsuneaki Fuse , Yukihito Oowaki
发明人： Tsuneaki Fuse , Yukihito Oowaki
IPC分类号： G11C11/407 , G11C5/14 , H01L21/822 , H01L27/04 , H03K19/00 , H01L25/00
CPC分类号： G11C5/147 , H03K19/0016 , Y10T307/352
摘要： The semiconductor integrated circuit device of the present invention includes a plurality of integrated circuits. The scheduling circuit selects an arbitrary number of integrated circuit from the plurality of integrated circuits, and connects the selected integrated circuits between the power line and the ground line such that the selected integrated circuits are arranged in series or in series-parallel. The scheduling circuit sets a combination of connection of the selected integrated circuits such that the consumption power of the total of the selected integrated circuits becomes minimum. The voltage control circuit sets a potential of a serial connecting portion of the selected integrated circuits. The data control circuit has an input output circuit for inputting and outputting data between the selected integrated circuits, and the outside, and a level conversion circuit for converting a level of data between certain integrated circuits.
摘要翻译：本发明的半导体集成电路器件包括多个集成电路。调度电路从多个集成电路中选择任意数量的集成电路，并且将所选择的集成电路在电力线和接地线之间连接，使得所选择的集成电路串联或并联布置。调度电路设置所选择的集成电路的连接的组合，使得所选择的集成电路的总体的消耗功率变得最小。电压控制电路设定所选择的集成电路的串联连接部分的电位。数据控制电路具有用于在所选择的集成电路之间输入和输出数据的输入输出电路和外部，以及用于转换某些集成电路之间的数据电平的电平转换电路。

7. 发明授权

US06232822B1 Semiconductor device including a bipolar transistor biased to produce a negative base current by the impact ionization mechanism 失效
标题翻译：半导体器件包括被偏置以通过冲击电离机制产生负的基极电流的双极晶体管
公开(公告)号：US06232822B1
公开(公告)日：2001-05-15
申请号：US08268728
申请日：1994-06-30
申请人： Koji Sakui , Takehiro Hasegawa , Shigeyoshi Watanabe , Fujio Masuoka , Tsuneaki Fuse , Toshiki Seshita , Seiichi Aritome , Akihiro Nitayama , Fumio Horiguchi
发明人： Koji Sakui , Takehiro Hasegawa , Shigeyoshi Watanabe , Fujio Masuoka , Tsuneaki Fuse , Toshiki Seshita , Seiichi Aritome , Akihiro Nitayama , Fumio Horiguchi
IPC分类号： H03K17687
CPC分类号： H01L27/1025 , G11C11/39 , H01L29/36 , H01L29/42304 , H01L29/456 , H01L29/73 , H01L29/7322 , H01L29/885 , H03F3/04 , H03K3/021 , H03K17/567
摘要： A semiconductor device includes a bipolar transistor whose emitter-collector voltage is set to satisfy a condition IBE
摘要翻译：半导体器件包括双极晶体管，其发射极 - 集电极电压被设置为满足条件IBE

8. 发明授权

US6084453A Clock converting circuit 失效
标题翻译：时钟转换电路
公开(公告)号：US6084453A
公开(公告)日：2000-07-04
申请号：US105959
申请日：1998-06-29
申请人： Tsuneaki Fuse , Masahiro Kamoshida , Haruki Toda , Yukihito Oowaki
发明人： Tsuneaki Fuse , Masahiro Kamoshida , Haruki Toda , Yukihito Oowaki
IPC分类号： H03K5/04 , G06F1/06 , G11C11/407 , G11C11/4076 , H03K5/13 , H03K5/156 , H03K7/08
CPC分类号： H03K5/1565 , H03K5/133
摘要： A cycle measuring circuit 3 measures a cycle of an external clock signal, which is approximately m times a unit time. A number converting circuit 5 and a time converting circuit 7 cooperate, generating a pulse signal delayed by m/2.sup.K times the unit time, or by 1/2.sup.K times the cycle of the external clock signal. A logic circuit 8 generates an internal clock signal which rises in synchronism with the external clock signal and falls in synchronism with the pulse signal thus delayed. Hence, the internal clock signal has the same cycle as the external clock signal and has a desired duty ratio of (1/2.sup.K).times.100%.
摘要翻译：周期测量电路3测量大约是单位时间的m倍的外部时钟信号的周期。数字转换电路5和时间转换电路7协调，产生延迟了单位时间的m / 2K倍的脉冲信号，或者是外部时钟信号的周期的1 / 2K倍。逻辑电路8产生与外部时钟信号同步上升的内部时钟信号，并且与延迟的脉冲信号同步地下降。因此，内部时钟信号具有与外部时钟信号相同的周期，并且具有（1 / 2K）×100％的期望占空比。

9. 发明授权

US5060194A Semiconductor memory device having a BICMOS memory cell 失效
标题翻译：具有BICMOS存储器单元的半导体存储器件
公开(公告)号：US5060194A
公开(公告)日：1991-10-22
申请号：US501865
申请日：1990-03-28
申请人： Koji Sakui , Tsuneaki Fuse , Takehiro Hasegawa , Shigeyoshi Watanabe , Fujio Masuoka
发明人： Koji Sakui , Tsuneaki Fuse , Takehiro Hasegawa , Shigeyoshi Watanabe , Fujio Masuoka
IPC分类号： G11C11/404 , G11C11/411 , G11C11/412 , H01L27/108
CPC分类号： H01L27/108 , G11C11/404 , G11C11/4113 , G11C11/412
摘要： A semiconductor memory device includes a plurality of memory cells each having a bipolar transistor whose collector-emitter voltage V.sub.CE is controlled according to the base potential to satisfy the condition of I.sub.BE

10. 发明授权

US4943944A Semiconductor memory using dynamic ram cells 失效
标题翻译：半导体存储器使用动态RAM单元
公开(公告)号：US4943944A
公开(公告)日：1990-07-24
申请号：US275501
申请日：1988-11-23
申请人： Koji Sakui , Tsuneaki Fuse , Fujio Masuoka
发明人： Koji Sakui , Tsuneaki Fuse , Fujio Masuoka
IPC分类号： G11C7/10 , G11C11/4091 , G11C11/4094 , G11C11/4096
CPC分类号： G11C11/4091 , G11C11/4094 , G11C11/4096 , G11C7/1006 , G11C7/1051
摘要： Bit-line pairs and word lines are disposed perpendicular to one another and dRAM cells are placed at their intersections. A dummy cell is connected to each of the bit-line pairs. A bit-line sense amplifier and an equalizer are connected to one end of the bit-line pair. The other end of the bit-line pair is connected to a latch type memory cell via a first transfer gate. The latch type memory cell are further connected to input/output line pair via a second transfer gate controlled by a column select line. During a RAS active period in a read cycle a word line is selected so that data is read from a dRAM cell and the dummy cell connected to the selected word line onto the bit-line pairs. The bit-line sense amplifiers are activated so that the levels of the bit lines become determinate. The first transfer gates are subsequently turned on to transfer the data on the bit-line pairs to the latch type cells. After the memory cells are rewritten into, the selected word line is reset and the latch type memory cells are electrically disconnected from the bit-line pairs. The equalizers operate to precharge the bit-line pairs. When CAS is rendered active and a column is selected, a corresponging second transfer gate is turned on so that data in the latch type memory cell is read out onto the input/output line pairs.
摘要翻译：位线对和字线彼此垂直设置，并且dRAM单元被放置在它们的相交处。虚拟单元连接到每个位线对。位线读出放大器和均衡器连接到位线对的一端。位线对的另一端通过第一传输门连接到锁存型存储单元。闩锁型存储单元还经由由列选择线控制的第二传输门连接到输入/输出线对。在读周期的RAS活动期间，选择字线，使得从dRAM单元读取数据，将连接到选定字线的虚拟单元读取到位线对上。位线读出放大器被激活，使得位线的电平变得确定。随后接通第一传输门，将位线对上的数据传送到锁存型单元。在重写存储器单元之后，所选择的字线被复位，闩锁型存储单元与位线对电连接。均衡器用于对位线对进行预充电。当CAS被激活并选择列时，相应的第二传输门被导通，使得锁存型存储单元中的数据被读出到输入/输出线对上。

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