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1. 发明授权

US08737131B2 Programming memory cells using smaller step voltages for higher program levels 有权
标题翻译：使用更小的步进电压编程存储器单元以实现更高的程序级
公开(公告)号：US08737131B2
公开(公告)日：2014-05-27
申请号：US13305795
申请日：2011-11-29
申请人： Koji Sakui
发明人： Koji Sakui
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3427
摘要： Memory devices and methods are disclosed. An embodiment of one such method includes programming a first memory cell to a first program level by applying a first series of programming pulses to a control gate of the first memory cell, where the programming pulses of the first series have voltages that sequentially increase by a certain first voltage; and programming a second memory cell to a second program level that is higher than the first program level by applying a second series of programming pulses to a control gate of the second memory cell, where the programming pulses of the second series have voltages that sequentially increase by a certain second voltage less than the certain first voltage.
摘要翻译：公开了存储器件和方法。一种这样的方法的实施例包括通过将第一系列编程脉冲施加到第一存储器单元的控制栅极来将第一存储器单元编程为第一程序级，其中第一系列的编程脉冲具有依次增加的电压一定的第一电压; 以及通过将第二系列编程脉冲施加到所述第二存储器单元的控制栅极来将第二存储器单元编程为高于所述第一编程电平的第二编程电平，其中所述第二系列的编程脉冲具有顺序增加的电压通过一定的第二电压小于一定的第一电压。

2. 发明申请

US20140036590A1 PARTIAL BLOCK MEMORY OPERATIONS 审中-公开
标题翻译：部分块存储器操作
公开(公告)号：US20140036590A1
公开(公告)日：2014-02-06
申请号：US13564458
申请日：2012-08-01
申请人： Peter Sean Feeley , Koji Sakui , Akira Goda
发明人： Peter Sean Feeley , Koji Sakui , Akira Goda
IPC分类号： G11C16/04
摘要： Methods and apparatuses are disclosed, such as those including a block of memory cells that includes strings of charge storage devices. Each of the strings may comprise a plurality of charge storage devices formed in a plurality of tiers. The apparatus may comprise a plurality of access lines shared by the strings. Each of the plurality of access lines may be coupled to the charge storage devices corresponding to a respective tier of the plurality of tiers. The apparatus may comprise a plurality of sub-sources associated with the strings. Each of the plurality of sub-sources may be coupled to a source select gate of each string of a respective subset of a plurality of subsets of the strings, and each sub-source may be independently selectable from other sub-sources to select the strings of its respective subset independently of other strings corresponding to other subsets.
摘要翻译：公开了诸如包括包含电荷存储装置串的存储器单元块的方法和装置。每个串可以包括以多层形成的多个电荷存储装置。该装置可以包括由串共享的多个接入线。多个接入线路中的每一个可以耦合到与多个层级的相应层对应的电荷存储装置。该装置可以包括与弦相关联的多个子源。多个子源中的每一个可以耦合到字符串的多个子集的相应子集的每个串的源选择门，并且每个子源可以独立地从其他子源中选择以选择字符串独立于对应于其他子集的其他字符串。

3. 发明申请

US20130336070A1 APPARATUSES AND METHODS TO MODIFY PILLAR POTENTIAL 有权
标题翻译：修改支柱潜力的装置和方法
公开(公告)号：US20130336070A1
公开(公告)日：2013-12-19
申请号：US13525035
申请日：2012-06-15
申请人： Koji Sakui , Peter Sean Feeley
发明人： Koji Sakui , Peter Sean Feeley
IPC分类号： G11C16/10 , H01L29/788
CPC分类号： G11C16/10 , G11C16/02 , G11C16/0466 , G11C16/0483
摘要： Apparatus are disclosed, such as a block including a number of strings of charge storage devices, each string including a number of charge storage devices associated with a pillar, and each pillar including semiconductor material. Methods are disclosed, such as a method that includes performing a first operation on a first charge storage device associated with a pillar in the block, modifying an electrical potential of the pillar, and performing a second operation on a second charge storage device in the block. Additional apparatus and methods are described.
摘要翻译：公开了诸如包括多个电荷存储装置串的块的每个串，包括与柱相关联的多个电荷存储装置，并且每个支柱包括半导体材料。公开了一种方法，例如包括在与块中的柱相关联的第一电荷存储装置上执行第一操作的方法，修改支柱的电位，以及对块中的第二电荷存储装置执行第二操作。描述附加的装置和方法。

4. 发明授权

US08537623B2 Devices and methods of programming memory cells 有权
标题翻译：编程存储单元的设备和方法
公开(公告)号：US08537623B2
公开(公告)日：2013-09-17
申请号：US13178217
申请日：2011-07-07
申请人： Koichi Kawai , Koji Sakui , Peter Feeley
发明人： Koichi Kawai , Koji Sakui , Peter Feeley
IPC分类号： G11C11/34
CPC分类号： G11C16/3404 , G11C11/5628 , G11C16/10 , G11C16/3427 , G11C16/3459
摘要： Devices and methods of programming memory cells, both SLC and MLC, such as to reduce charge-storage structure to charge-storage structure coupling, are shown and described. Programming of memory cells can include comparing a first page of data to a second page of data, and further programming cells corresponding to the first page of data that will not likely be affected by coupling from programming the second page of data.
摘要翻译：显示和描述了将存储器单元（SLC和MLC）编程的设备和方法，例如将电荷存储结构减少到电荷存储结构耦合。存储器单元的编程可以包括将数据的第一页与第二页数据进行比较，以及进一步对与第一页数据相对应的编程单元，该第一页数据不会受编程第二页数据的耦合的影响。

5. 发明申请

US20130135937A1 PROGRAMMING MEMORY CELLS USING SMALLER STEP VOLTAGES FOR HIGHER PROGRAM LEVELS 有权
标题翻译：使用较小程序级电压编程存储器电池
公开(公告)号：US20130135937A1
公开(公告)日：2013-05-30
申请号：US13305795
申请日：2011-11-29
申请人： Koji Sakui
发明人： Koji Sakui
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3427
摘要： Memory devices and methods are disclosed. An embodiment of one such method includes programming a first memory cell to a first program level by applying a first series of programming pulses to a control gate of the first memory cell, where the programming pulses of the first series have voltages that sequentially increase by a certain first voltage; and programming a second memory cell to a second program level that is higher than the first program level by applying a second series of programming pulses to a control gate of the second memory cell, where the programming pulses of the second series have voltages that sequentially increase by a certain second voltage less than the certain first voltage.
摘要翻译：公开了存储装置和方法。一种这样的方法的实施例包括通过将第一系列编程脉冲施加到第一存储器单元的控制栅极来将第一存储器单元编程为第一程序级，其中第一系列的编程脉冲具有依次增加的电压一定的第一电压; 以及通过将第二系列编程脉冲施加到所述第二存储器单元的控制栅极来将第二存储器单元编程为高于所述第一编程电平的第二编程电平，其中所述第二系列的编程脉冲具有顺序增加的电压通过一定的第二电压小于一定的第一电压。

6. 发明申请

US20080212373A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH A STACKED GATE INCLUDING A FLOATING GATE AND A CONTROL GATE 失效
标题翻译：具有包括浮动门和控制门的堆叠门的半导体集成电路装置
公开(公告)号：US20080212373A1
公开(公告)日：2008-09-04
申请号：US12027744
申请日：2008-02-07
申请人： Takehiro HASEGAWA , Akira Umezawa , Koji Sakui , Fumitaka Arai , Ryo Mitani
发明人： Takehiro HASEGAWA , Akira Umezawa , Koji Sakui , Fumitaka Arai , Ryo Mitani
IPC分类号： G11C16/04 , H01L29/788
CPC分类号： H01L27/11524 , G11C11/005 , G11C16/0433 , G11C16/0483 , G11C16/08 , G11C16/20 , H01L27/105 , H01L27/115 , H01L27/11517 , H01L27/11521 , H01L27/11526 , H01L27/11546
摘要： A semiconductor integrated circuit device includes first and second nonvolatile semiconductor memories. The first memory has first and second select transistors and first memory cell transistors. The first memory cell transistor has a first floating gate on a first gate insulating film and a first control gate on a first inter-gate insulating film. The second memory has a third select transistor and a second memory cell transistor. The second memory cell transistor has a second floating gate on a second gate insulating film and a second control gate on a second inter-gate insulating film. The first and second gate insulating films have the same film thickness. The first and second floating gates have the same film thickness. The first and second inter-gate insulating films have the same film thickness. The first and second control gates have the same film thickness.
摘要翻译：半导体集成电路器件包括第一和第二非易失性半导体存储器。第一存储器具有第一和第二选择晶体管和第一存储单元晶体管。第一存储单元晶体管在第一栅极绝缘膜上具有第一浮置栅极，在第一栅极间绝缘膜上具有第一控制栅极。第二存储器具有第三选择晶体管和第二存储单元晶体管。第二存储单元晶体管在第二栅极绝缘膜上具有第二浮置栅极，在第二栅极绝缘膜上具有第二控制栅极。第一和第二栅极绝缘膜具有相同的膜厚度。第一和第二浮栅具有相同的膜厚度。第一和第二栅极间绝缘膜具有相同的膜厚度。第一和第二控制栅具有相同的膜厚度。

7. 发明申请

US20080192549A1 Nonvolatile Semiconductor Storage Device and Operation Method Thereof 有权
标题翻译：非易失性半导体存储器件及其操作方法
公开(公告)号：US20080192549A1
公开(公告)日：2008-08-14
申请号：US11815387
申请日：2006-02-03
申请人： Michio Nakagawa , Koji Sakui
发明人： Michio Nakagawa , Koji Sakui
IPC分类号： G11C16/12
CPC分类号： G11C16/12 , G11C16/3468
摘要： To provide a nonvolatile semiconductor storage device and a drive method thereof capable of preventing lowering efficiency of write or erase operation and reducing the write time and the erase time. [MEANS FOR SOLVING PROBLEMS] A nonvolatile semiconductor storage device includes an electrically rewritable memory cell formed by a floating gate and a control gate layered on a semiconductor layer. The nonvolatile semiconductor storage device applies a plurality of threshold value fluctuation pulses having a stepwise high potential to the memory cell and then detects a threshold value of the memory cell. When the threshold value of the memory cell is not a predetermined value, a plurality of threshold value fluctuation pulses having stepwise high potential are applied to the memory cell from a potential of the lastly applied threshold value fluctuation pulse, among the plurality of threshold value fluctuation pulses, to which a certain potential is added.
摘要翻译：提供一种能够防止写入或擦除操作的降低效率并减少写入时间和擦除时间的非易失性半导体存储器件及其驱动方法。解决问题的手段非易失性半导体存储装置包括由浮置栅极和层叠在半导体层上的控制栅极形成的电可重写存储单元。非易失性半导体存储装置向存储单元施加具有逐级高电位的多个阈值波动脉冲，然后检测存储单元的阈值。当存储单元的阈值不是预定值时，具有逐步高电位的多个阈值波动脉冲从最近施加的阈值波动脉冲的电位在多个阈值波动之中被施加到存储单元脉冲，添加一定的电位。

8. 发明授权

US07362614B2 Non-volatile semiconductor storage apparatus 失效
标题翻译：非易失性半导体存储装置
公开(公告)号：US07362614B2
公开(公告)日：2008-04-22
申请号：US11529272
申请日：2006-09-29
申请人： Koji Sakui , Kazuhiro Suzuki
发明人： Koji Sakui , Kazuhiro Suzuki
IPC分类号： G11C11/34
CPC分类号： G11C16/0483
摘要： A non-volatile semiconductor storage apparatus includes a memory cell array including at least one memory cell unit in which multiple electrically rewritable non-volatile memory cells are serially connected, multiple control gate lines connecting to a control terminal for the multiple memory cells, a bit line connecting to the memory cell unit, means for selecting the control gate line, means for selecting the bit line, an externally input single power supply terminal, and an externally input ground potential terminal. In this case, the voltage equal to or lower than the voltage of the externally input single power supply is applied to the control gate line in reading out stored data in the memory cells.
摘要翻译：非易失性半导体存储装置包括存储单元阵列，其包括至少一个存储单元单元，其中多个电可重写非易失性存储单元串联连接，连接到多个存储器单元的控制端的多个控制栅极线，连接到存储单元单元的线路，用于选择控制栅极线的装置，用于选择位线的装置，外部输入的单个电源端子和外部输入的接地电位端子。在这种情况下，等于或低于外部输入单个电源的电压的电压在读出存储单元中存储的数据时被施加到控制栅极线。

9. 发明授权

US07061786B2 Semiconductor memory device and memory system 失效
公开(公告)号：US07061786B2
公开(公告)日：2006-06-13
申请号：US11042200
申请日：2005-01-26
申请人： Koji Sakui
发明人： Koji Sakui
IPC分类号： G11C7/00
CPC分类号： G11C5/025 , G06F13/4234 , Y02D10/14 , Y02D10/151
摘要： The present invention provides a semiconductor memory device and memory system comprising a first semiconductor memory having a first peripheral circuit for transmitting and receiving memory data to/from a first memory cell array, a second semiconductor memory having a second peripheral circuit for transmitting and receiving the memory data to/from a second memory cell array, and a part of the peripheral circuit of the first semiconductor memory formed adjacent to the second memory cell array by a design rule of the second peripheral circuit.

10. 发明申请

US20050041476A1 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US20050041476A1
公开(公告)日：2005-02-24
申请号：US10929014
申请日：2004-08-30
申请人： Koji Sakui , Junichi Miyamodo
发明人： Koji Sakui , Junichi Miyamodo
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/10 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C16/10 , G11C16/0433
摘要： A memory cell array has a unit formed from one memory cell and two select transistors sandwiching the memory cell. One block has one control gate line. Memory cells connected to one control gate line form one page. A sense amplifier having a latch function is connected to a bit line. In a data change operation, data of memory cells of one page are read to the sense amplifiers. After data are superscribed on data in the sense amplifiers, and a page erase is performed, data in the sense amplifiers are programmed in the memory cells of one page. Superscription of data in the sense amplifiers allows a data change operation for byte data or page data.
摘要翻译：存储单元阵列具有由一个存储单元形成的单元和夹着该存储单元的两个选择晶体管。一个块有一个控制栅极线。连接到一个控制门线的存储单元形成一页。具有锁存功能的读出放大器连接到位线。在数据更改操作中，一页的存储单元的数据被读取到读出放大器。在对读出放大器中的数据进行数据更新之后，执行页擦除，读出放大器中的数据被编程在一页的存储单元中。在读出放大器中的数据的替换允许对字节数据或页数据进行数据改变操作。

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