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1. 发明授权

US5641705A Device isolation method of semiconductor device 失效
标题翻译：半导体器件的器件隔离方法
公开(公告)号：US5641705A
公开(公告)日：1997-06-24
申请号：US470914
申请日：1995-06-06
申请人： Dong-ho Ahn , Seong-joon Ahn , Yu-gyun Shin , Yun-gi Kim
发明人： Dong-ho Ahn , Seong-joon Ahn , Yu-gyun Shin , Yun-gi Kim
IPC分类号： H01L21/316 , H01L21/32 , H01L21/76 , H01L21/762
CPC分类号： H01L21/76205 , H01L21/32
摘要： In a device isolation method for a semiconductor device, after a pad oxide layer and a nitride layer are formed on a semiconductor substrate, the nitride layer located above the device isolation region is removed. An undercut is formed under the nitride by partially etching the pad oxide layer. After a first oxide layer is formed on the exposed substrate and a polysilicon spacer is formed on the sidewalls of the nitride layer, a void is formed in the oxide layer under the nitride layer which is formed on the active region by oxidizing the resultant structure in which the polysilicon spacer is formed at a temperature above 950.degree. C. Thus, good cell definition and stable device isolation can be realized, while solving the typical problem of conventional LOCOS methods by forming the void intentionally in the pad oxide layer thickened by bird's beak punch through.
摘要翻译：在半导体器件的器件隔离方法中，在衬底氧化物层和氮化物层形成在半导体衬底上之后，去除位于器件隔离区上方的氮化物层。通过部分蚀刻衬垫氧化物层，在氮化物之下形成底切。在暴露的基板上形成第一氧化物层并在氮化物层的侧壁上形成多晶硅间隔物之后，在形成于有源区上的氮化物层下面的氧化物层中形成空穴，其中多晶硅间隔物在高于950℃的温度下形成。因此，通过在通过鸟喙加厚的垫氧化物层中有意地形成空穴来解决常规LOCOS方法的典型问题，可以实现良好的电池定义和稳定的器件隔离穿透

2. 发明授权

US6093622A Isolation method of semiconductor device using second pad oxide layer formed through chemical vapor deposition (CVD) 失效
标题翻译：使用通过化学气相沉积（CVD）形成的第二衬垫氧化物层的半导体器件的隔离方法
公开(公告)号：US6093622A
公开(公告)日：2000-07-25
申请号：US148060
申请日：1998-09-04
申请人： Dong-ho Ahn , Sung-eui Kim , Yu-gyun Shin
发明人： Dong-ho Ahn , Sung-eui Kim , Yu-gyun Shin
IPC分类号： H01L21/285 , H01L21/316 , H01L21/76 , H01L21/762
CPC分类号： H01L21/76202
摘要： An isolation method in the fabrication process of a semiconductor device is provided. The method forms an oxide layer as a buffer layer for reducing stress through chemical vapor deposition (CVD). By the method, a first pad oxide layer and a silicon nitride layer are formed on a semiconductor substrate, and then an silicon nitride layer pattern is formed by patterning, and undercuts are formed in the first pad oxide layer pattern. Subsequently, a second pad oxide layer is formed on the entire surface of the semiconductor substrate through CVD, and then spacers are formed on the sidewalls of both the patterned first pad oxide layer and silicon nitride layer and a field oxide layer is formed through thermal oxidation. Alternatively, a silicon layer is deposited without the spacers to form the field oxide layer. The second pad oxide layer is a buffer layer for buffering stress during formation of the field oxide layer.
摘要翻译：提供了半导体器件的制造工艺中的隔离方法。该方法形成通过化学气相沉积（CVD）来减少应力的缓冲层的氧化物层。通过该方法，在半导体衬底上形成第一衬垫氧化物层和氮化硅层，然后通过图案形成氮化硅层图案，并且在第一衬垫氧化物层图案中形成底切。随后，通过CVD在半导体衬底的整个表面上形成第二焊盘氧化物层，然后在图案化的第一焊盘氧化物层和氮化硅层的侧壁上形成间隔物，并且通过热氧化形成场氧化物层。或者，沉积硅层而没有间隔物以形成场氧化物层。第二衬垫氧化物层是用于在形成场氧化物层期间缓冲应力的缓冲层。

3. 发明授权

US06717231B2 Trench isolation regions having recess-inhibiting layers therein that protect against overetching 失效
标题翻译：沟槽隔离区域在其中具有防止过蚀刻的凹陷抑制层
公开(公告)号：US06717231B2
公开(公告)日：2004-04-06
申请号：US10224017
申请日：2002-08-20
申请人： Sung-eui Kim , Keum-joo Lee , In-seak Hwang , Young-sun Koh , Dong-ho Ahn , Moon-han Park , Tai-su Park
发明人： Sung-eui Kim , Keum-joo Lee , In-seak Hwang , Young-sun Koh , Dong-ho Ahn , Moon-han Park , Tai-su Park
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： Methods of forming trench isolation regions include the steps of forming a semiconductor substrate having a trench therein and a masking layer thereon extending adjacent the trench. The masking layer may comprise silicon nitride. A recess-inhibiting layer is then formed on a sidewall of the trench and on a sidewall of the masking layer. Next, a stress-relief layer is formed on the recess-inhibiting layer. This stress-relief layer extends opposite the sidewall of the trench and opposite the sidewall of the masking layer and may comprise silicon nitride. The trench is then filled with a trench isolation layer. A sequence of planarization or etch-back steps are then performed to remove the masking layer and also align an upper surface of the trench isolation layer with a surface of the substrate. At least a portion of the masking layer is removed using a first etchant (e.g., phosphoric acid) that selectively etches the masking layer and the stress-relief layer at faster rates than the first recess-inhibiting layer. The recess-inhibiting layer is formed directly on a sidewall of the masking layer in order to limit the extent to which the outer surfaces of the stress-relief layer are exposed to the first etchant. In this manner, recession of the stress-relief layer and the voids that may subsequently develop as a result of the recession can be reduced. Multiple thin stress-relief layers may also be provided and these multiple layers provide a degree of stress-relief that is comparable with a single much thicker stress-relief layer.
摘要翻译：形成沟槽隔离区域的方法包括以下步骤：在其中形成具有沟槽的半导体衬底和其上邻近沟槽延伸的掩模层。掩模层可以包括氮化硅。然后在沟槽的侧壁和掩模层的侧壁上形成凹陷抑制层。接下来，在凹陷抑制层上形成应力消除层。该应力消除层与沟槽的侧壁相对并且与掩模层的侧壁相对延伸并且可以包括氮化硅。然后用沟槽隔离层填充沟槽。然后执行一系列平面化或蚀刻步骤以去除掩模层，并且还使沟槽隔离层的上表面与衬底的表面对准。使用第一蚀刻剂（例如磷酸）去除掩模层的至少一部分，其以比第一凹陷抑制层更快的速率选择性地蚀刻掩模层和应力消除层。凹陷抑制层直接形成在掩模层的侧壁上，以限制应力消除层的外表面暴露于第一蚀刻剂的程度。以这种方式，可以减少应力消除层的凹陷和随后可能由于凹陷而形成的空隙。还可以提供多个薄的应力消除层，并且这些多层提供与单个更厚的应力消除层相当的应力消除程度。

4. 发明授权

US06482715B2 Method of forming shallow trench isolation layer in semiconductor device 有权
公开(公告)号：US06482715B2
公开(公告)日：2002-11-19
申请号：US09927340
申请日：2001-08-13
申请人： Tai-su Park , Ho-kyu Kang , Dong-ho Ahn , Moon-han Park
发明人： Tai-su Park , Ho-kyu Kang , Dong-ho Ahn , Moon-han Park
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： A method of forming a shallow trench isolation layer in a semiconductor device is provided, wherein a first trench and a second trench are formed in an area selected from a semiconductor substrate and a sidewall oxide layer, an anti-oxidation liner, and a mask layer are formed on the semiconductor substrate including the inner surfaces of the first and second trenches, in the same order. Using photoresist lithography, the mask layer and the anti-oxidation layer are etched in the second trench. An isolation layer is formed in the first and second trenches by depositing and then chemically and mechanically polishing the dielectric material and the layers underneath until the semiconductor substrate surface is exposed. The first trench provides isolation between N-FETs, an N-FET and a P-FET, an N-FET and other circuit devices, a P-FET and other circuit devices, and other circuit devices and the second trench provides isolation between P-FETs.

5. 发明授权

US5804491A Combined field/trench isolation region fabrication methods 失效
标题翻译：组合场/沟隔离区制造方法
公开(公告)号：US5804491A
公开(公告)日：1998-09-08
申请号：US744436
申请日：1996-11-08
申请人： Dong-ho Ahn
发明人： Dong-ho Ahn
IPC分类号： H01L21/316 , H01L21/762 , H01L21/76
CPC分类号： H01L21/76202 , H01L21/76232
摘要： Isolation regions are fabricated on a substrate by forming a pattern region on the substrate, exposing spaced apart first and second areas of the substrate. The second area is then covered, preferably using sidewall spacers formed adjacent sidewall portions of the pattern region, while a portion of the first area is left exposed. A first insulation region is then formed on the exposed portion of the first area. The second area is then exposed and a trench isolation region is formed at the second area. Preferably, the pattern region is formed by forming a masking layer on the substrate and patterning the masking layer using a single photolithographic mask. The first insulation layer preferably is formed by thermally oxidizing the exposed portion of the first area. Preferably, the first area is wider than the second area.
摘要翻译：通过在衬底上形成图案区域，暴露衬底的间隔开的第一和第二区域，在衬底上制造隔离区域。然后覆盖第二区域，优选地使用与图案区域的侧壁部分相邻形成的侧壁间隔，同时第一区域的一部分被暴露。然后在第一区域的暴露部分上形成第一绝缘区域。然后暴露第二区域，并在第二区域形成沟槽隔离区域。优选地，通过在衬底上形成掩模层并使用单个光刻掩模对掩模层进行构图来形成图案区域。第一绝缘层优选地通过热氧化第一区域的暴露部分而形成。优选地，第一区域比第二区域宽。

6. 发明申请

US20120088347A1 Methods Of Manufacturing Non-Volatile Phase-Change Memory Devices 有权
标题翻译：制造非易失性相变存储器件的方法
公开(公告)号：US20120088347A1
公开(公告)日：2012-04-12
申请号：US13160761
申请日：2011-06-15
申请人： Byoung-deog Choi , Dong-ho Ahn , Man-sug Kang , Young-kuk Kim , Jin-ho Oh
发明人： Byoung-deog Choi , Dong-ho Ahn , Man-sug Kang , Young-kuk Kim , Jin-ho Oh
IPC分类号： H01L21/62
CPC分类号： H01L45/06 , H01L27/2436 , H01L27/2463 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： Methods of manufacturing non-volatile memory devices may include separating first phase-change material groups and second phase-change material groups, which have different sizes, from a target including phase-change materials and faulting a phase-change material layer on an object by using the first phase-change material groups and the second phase-change material groups.
摘要翻译：制造非易失性存储器件的方法可以包括从包括相变材料的靶分离具有不同尺寸的第一相变材料组和第二相变材料组，并且通过以下方式将对象上的相变材料层断层使用第一相变材料组和第二相变材料组。

7. 发明申请

US20110284815A1 PHASE-CHANGE MEMORY DEVICES HAVING STRESS RELIEF BUFFERS 审中-公开
标题翻译：具有应力消除缓冲器的相变存储器件
公开(公告)号：US20110284815A1
公开(公告)日：2011-11-24
申请号：US13070648
申请日：2011-03-24
申请人： Ik-soo Kim , Soon-oh Park , Dong-ho Ahn , Sung-lae Cho , Dae-hong Ko , Hyun-chul Sohn , Ki-hoon Do , Mann-ho Cho
发明人： Ik-soo Kim , Soon-oh Park , Dong-ho Ahn , Sung-lae Cho , Dae-hong Ko , Hyun-chul Sohn , Ki-hoon Do , Mann-ho Cho
IPC分类号： H01L47/00
CPC分类号： H01L45/12 , H01L45/06 , H01L45/144
摘要： A memory device includes a substrate and a memory cell including a first electrode on the substrate, a phase-change material region on the first electrode and a second electrode on the phase-change material region opposite the first electrode. The memory device further includes a stress relief buffer adjacent a sidewall of the phase-change material region between the first and second electrodes. In some embodiments, the stress relief buffer includes a stress relief region contacting the sidewall of the phase-change material region. In further embodiments, the stress relief buffer includes a void adjacent the sidewall of the phase-change material region.
摘要翻译：存储器件包括衬底和存储单元，该存储单元包括衬底上的第一电极，第一电极上的相变材料区域和与第一电极相对的相变材料区域上的第二电极。存储器件还包括与第一和第二电极之间的相变材料区域的侧壁相邻的应力释放缓冲器。在一些实施例中，应力消除缓冲器包括接触相变材料区域的侧壁的应力消除区域。在另外的实施例中，应力消除缓冲器包括邻近相变材料区域的侧壁的空隙。

8. 发明授权

US5926721A Isolation method for semiconductor device using selective epitaxial growth 失效
标题翻译：使用选择性外延生长的半导体器件的隔离方法
公开(公告)号：US5926721A
公开(公告)日：1999-07-20
申请号：US924467
申请日：1997-08-21
申请人： Sug-hun Hong , Dong-ho Ahn
发明人： Sug-hun Hong , Dong-ho Ahn
IPC分类号： H01L21/764 , H01L21/76 , H01L21/762
CPC分类号： H01L21/76248 , H01L21/76294
摘要： An isolation method for a highly-integrated semiconductor device includes growing an epitaxial layer on the entire surface of a semiconductor substrate including over a trench on which an oxide layer is formed, thereby leaving the inside of the trench empty. A portion of the epitaxial layer which is located over the trench is then oxidized to form an isolation region.
摘要翻译：用于高度集成的半导体器件的隔离方法包括在半导体衬底的整个表面上生长外延层，该半导体衬底包括在其上形成有氧化物层的沟槽上，从而使沟槽内部留空。然后将位于沟槽上方的外延层的一部分氧化形成隔离区。

9. 发明授权

US08222625B2 Non-volatile memory device including phase-change material 有权
标题翻译：包括相变材料的非易失性存储器件
公开(公告)号：US08222625B2
公开(公告)日：2012-07-17
申请号：US12657715
申请日：2010-01-26
申请人： Dong-ho Ahn , Hideki Horii , Soon-oh Park , Young-hyun Kim , Hee-ju Shin , Jin-ho Oh , Carl H. Schell , Jonathan D. Maimon , Stephen J. Hudgens
发明人： Dong-ho Ahn , Hideki Horii , Soon-oh Park , Young-hyun Kim , Hee-ju Shin , Jin-ho Oh , Carl H. Schell , Jonathan D. Maimon , Stephen J. Hudgens
IPC分类号： H01L45/00
CPC分类号： H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/124 , H01L45/141 , H01L45/144
摘要： A non-volatile memory device including a phase-change material, which has a low operating voltage and low power consumption, includes a lower electrode; a phase-change material layer formed on the lower electrode so as to be electrically connected to the lower electrode, wherein the phase-change material layer includes a phase-change material having a composition represented by SnXSbYTeZ or, alternatively with substitutions, in whole or in part, of silicon and/or indium for tin, arsenic and/or bismuth for antimony, and selenium for tellurium; and an upper electrode formed on the phase-change material layer so as to be electrically connected to the phase-change material layer. Here, 0.001≦X≦0.3, 0.001≦Y≦0.8, 0.1≦Z≦0.8, and X+Y+Z=1.
摘要翻译：包括具有低工作电压和低功耗的相变材料的非易失性存储器件包括下电极; 相变材料层，形成在下电极上，以与下电极电连接，其中相变材料层包括具有由SnXSbYTeZ表示的组成的相变材料，或者替代地，全部或部分由硅和/或铟制成的锡，砷和/或锑的铋，以及碲的硒; 以及形成在所述相变材料层上以与所述相变材料层电连接的上电极。这里，0.001＆nlE; X＆lt; NE; 0.3，0.001＆nlE; Y＆nlE; 0.8,0.1＆nlE; Z＆nlE; 0.8和X + Y + Z = 1。

10. 发明申请

US20110049459A1 NON-VOLATILE MEMORY DEVICE INCLUDING PHASE-CHANGE MATERIAL 有权
标题翻译：非易失性存储器件，包括相变材料
公开(公告)号：US20110049459A1
公开(公告)日：2011-03-03
申请号：US12697667
申请日：2010-02-01
申请人： Dong-ho Ahn , Hideki Horii , Soon-oh Park , Young-hyun Kim , Heo-ju Shin , Jin-ho Oh
发明人： Dong-ho Ahn , Hideki Horii , Soon-oh Park , Young-hyun Kim , Heo-ju Shin , Jin-ho Oh
IPC分类号： H01L45/00 , G06F12/00
CPC分类号： H01L45/124 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/144
摘要： A non-volatile memory device includes a lower electrode, a phase-change material layer formed on the lower electrode so as to be electrically connected to the lower electrode, and an upper electrode formed on the phase-change material layer so as to be electrically connected to the phase-change material layer. The phase-change material layer includes a phase-change material including a composition represented by the formula (I)A(IIXIIYIVZ)(1-A), where I is at least one of As and Se, II is at least one of Ge, Si and Sn, III is at least one of Sb and Bi, and IV is at least one of Te and Se, and where 0.001≦A≦0.3, 0.001≦X≦0.3, 0.001≦Y≦0.8, 0.1≦Z≦0.8, and X+Y+Z=1.
摘要翻译：非易失性存储器件包括下电极，形成在下电极上的相变材料层以与下电极电连接;以及上电极，形成在相变材料层上，以便电连接到相变材料层。相变材料层包括含有由式（I）A（IIXIIYIVZ）（1-A）表示的组合物的相变材料，其中I为As和Se中的至少一种，II为Ge中的至少一种，Si和Sn，III是Sb和Bi中的至少一种，IV是Te和Se中的至少一种，并且其中0.001和nlE; A和nlE; 0.3,0.001和nlE; X和nlE; 0.3,0.001和nlE; Y和nlE; 0.8,0.1 ＆nlE; Z＆nlE; 0.8和X + Y + Z = 1。

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