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1. 发明授权

US06316803B1 Integrated circuit memory devices having self-aligned contact 有权
标题翻译：具有自对准接触的集成电路存储器件
公开(公告)号：US06316803B1
公开(公告)日：2001-11-13
申请号：US09536216
申请日：2000-03-27
申请人： Hyo-dong Ban , Hyun-cheol Choe , Chang-sik Choi
发明人： Hyo-dong Ban , Hyun-cheol Choe , Chang-sik Choi
IPC分类号： H01L27108
CPC分类号： H01L27/10888 , H01L27/105 , H01L27/10814 , H01L27/10852 , H01L27/10855 , H01L27/10894
摘要： A method for manufacturing a semiconductor memory device in which a bit line and a storage electrode of a capacitor are connected to an active area of a semiconductor substrate, respectively, via a contact pad formed in a self-aligning manner. The method includes the steps of forming gate electrodes on the semiconductor substrate, the gate electrodes being covered with a nitride spacer. Then, a thermal oxide layer is formed on the exposed surface of the semiconductor substrate between the gate electrodes. Then, an etch stop layer is formed on the entire surface of the resultant structure having the thermal oxide layer to an appropriate thickness such that the space between the gate electrodes is not buried. Then, a first interlayer dielectric (ILD) film covering the space between the gate electrodes and the top of the gate electrodes is formed, and the first ILD film is then patterned to form a landing pad hole which exposes the spacer and the etch stop layer. Then, the etch stop layer and the thermal oxide layer are removed to expose the surface of the semiconductor substrate, and the landing pad hole is then filled with a conductive material to form landing pads.
摘要翻译：一种半导体存储器件的制造方法，其中电容器的位线和存储电极分别通过以自对准方式形成的接触焊盘连接到半导体衬底的有源区。该方法包括以下步骤：在半导体衬底上形成栅电极，栅电极被氮化物衬垫覆盖。然后，在栅电极之间的半导体衬底的暴露表面上形成热氧化层。然后，在具有热氧化物层的所得结构的整个表面上形成适当厚度的蚀刻停止层，使得栅电极之间的空间不被埋入。然后，形成覆盖栅电极和栅电极顶部之间的空间的第一层间电介质（ILD）膜，然后对第一ILD膜进行图案化以形成使衬垫和蚀刻停止层露出的着色焊盘孔。然后，去除蚀刻停止层和热氧化物层以暴露半导体衬底的表面，然后用导电材料填充着陆焊盘孔，以形成着陆焊盘。

2. 发明授权

US5583357A Semiconductor device and a method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5583357A
公开(公告)日：1996-12-10
申请号：US281641
申请日：1994-07-28
申请人： Hyun-cheol Choe
发明人： Hyun-cheol Choe
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/105 , H01L27/108
CPC分类号： H01L27/10844 , H01L27/105 , H01L27/10805 , H01L27/10808 , H01L27/10852
摘要： A semiconductor device using a self-aligned contact and a method for manufacturing the same is disclosed. A gate electrode having a first spacer formed on the sidewalls thereof is formed on a semiconductor substrate. Active regions which are spaced apart from each other by the gate electrode are formed in the semiconductor substrate. A bitline having a second spacer formed on the sidewalls thereof is formed on the gate electrode and the active regions. A self-aligned contact is formed on the active regions and a first pad electrode connected with the active region through the contact is formed between the bitlines. A bitline contact is formed on the bitline, and second and third pad electrodes, which are respectively connected with the bitline and the first pad electrode through the bitline contact, are formed on the bitline. Thus, the alignment tolerances of the bitline contact and the storage-node contact are maximized, so that a reliable semiconductor device can be realized.
摘要翻译：公开了一种使用自对准接触的半导体器件及其制造方法。在半导体衬底上形成具有形成在其侧壁上的第一间隔物的栅电极。在半导体衬底中形成有被栅电极彼此间隔开的有源区。在栅电极和有源区上形成具有形成在其侧壁上的第二间隔物的位线。在有源区上形成自对准接触，并且在位线之间形成通过接触与有源区连接的第一焊盘电极。在位线上形成位线接触，并且在位线上形成分别与位线和第一焊盘电极通过位线接触连接的第二和第三焊盘电极。因此，位线接触和存储 - 节点接触的对准公差最大化，从而可以实现可靠的半导体器件。

3. 发明授权

US6121110A Trench isolation method for semiconductor device 失效
标题翻译：半导体器件的沟槽隔离方法
公开(公告)号：US6121110A
公开(公告)日：2000-09-19
申请号：US124093
申请日：1998-07-29
申请人： Soo-jin Hong , Yu-gyun Shin , Han-sin Lee , Hyun-cheol Choe
发明人： Soo-jin Hong , Yu-gyun Shin , Han-sin Lee , Hyun-cheol Choe
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76224
摘要： A trench isolation method is provided. In the trench isolation method, a pad oxide film, an oxidative film and an etching mask film are formed on a semiconductor substrate in sequence, and then a trench is formed in a field region of the semiconductor substrate. A oxide film is formed at the inner wall of the trench and the side walls of the oxidative film by oxidizing the semiconductor substrate. After filling the trench with a dielectric material, the pad oxide film, oxidative film and etching mask film formed in the active region are removed.
摘要翻译：提供沟槽隔离方法。在沟槽隔离方法中，顺序地在半导体衬底上形成衬垫氧化膜，氧化膜和蚀刻掩模膜，然后在半导体衬底的场区域中形成沟槽。通过氧化半导体衬底，在沟槽的内壁和氧化膜的侧壁上形成氧化膜。在用电介质材料填充沟槽之后，去除在活性区域中形成的衬垫氧化膜，氧化膜和蚀刻掩模膜。

4. 发明授权

US6071802A Method for manufacturing semiconductor device having self-aligned contact 失效
标题翻译：具有自对准接触的半导体器件的制造方法
公开(公告)号：US6071802A
公开(公告)日：2000-06-06
申请号：US961453
申请日：1997-10-30
申请人： Hyo-dong Ban , Hyun-cheol Choe , Chang-sik Choi
发明人： Hyo-dong Ban , Hyun-cheol Choe , Chang-sik Choi
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8242 , H01L27/105 , H01L27/108 , H01L21/4763
CPC分类号： H01L27/10888 , H01L27/10852 , H01L27/10855 , H01L27/10894 , H01L27/105 , H01L27/10814
摘要： A method for manufacturing a semiconductor memory device in which a bit line and a storage electrode of a capacitor are connected to an active area of a semiconductor substrate, respectively, via a contact pad formed in a self-aligning manner. The method includes the steps of forming gate electrodes on the semiconductor substrate, the gate electrodes being covered with a nitride spacer. Then, a thermal oxide layer is formed on the exposed surface of the semiconductor substrate between the gate electrodes. Then, an etch stop layer is formed on the entire surface of the resultant structure having the thermal oxide layer to an appropriate thickness such that the space between the gate electrodes is not buried. Then, a first interlayer dielectric (ILD) film covering the space between the gate electrodes and the top of the gate electrodes is formed, and the first ILD film is then patterned to form a landing pad hole which exposes the spacer and the etch stop layer. Then, the etch stop layer and the thermal oxide layer are removed to expose the surface of the semiconductor substrate, and the landing pad hole is then filled with a conductive material to form landing pads.
摘要翻译：一种半导体存储器件的制造方法，其中电容器的位线和存储电极分别通过以自对准方式形成的接触焊盘连接到半导体衬底的有源区。该方法包括以下步骤：在半导体衬底上形成栅电极，栅电极被氮化物衬垫覆盖。然后，在栅电极之间的半导体衬底的暴露表面上形成热氧化层。然后，在具有热氧化层的所得结构的整个表面上形成适当厚度的蚀刻停止层，使得栅电极之间的空间不被埋入。然后，形成覆盖栅电极和栅电极顶部之间的空间的第一层间电介质（ILD）膜，然后对第一ILD膜进行图案化以形成使衬垫和蚀刻停止层露出的着色焊盘孔。然后，去除蚀刻停止层和热氧化物层以暴露半导体衬底的表面，然后用导电材料填充着陆焊盘孔，以形成着陆焊盘。

5. 发明授权

US5639682A Method of forming a semiconductor device using a self-aligned contact 失效
标题翻译：使用自对准接触形成半导体器件的方法
公开(公告)号：US5639682A
公开(公告)日：1997-06-17
申请号：US552535
申请日：1995-11-03
申请人： Hyun-cheol Choe
发明人： Hyun-cheol Choe
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/105 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10844 , H01L27/105 , H01L27/10805 , H01L27/10808 , H01L27/10852
摘要： A semiconductor device using a self-aligned contact and a method for manufacturing the same is disclosed. A gate electrode having a first spacer formed on the sidewalls thereof is formed on a semiconductor substrate. Active regions which are spaced apart from each other by the gate electrode are formed in the semiconductor substrate. A bitline having a second spacer formed on the sidewalls thereof is formed on the gate electrode and the active regions. A self-aligned contact is formed on the active regions and a first pad electrode connected with the active region through the contact is formed between the bitlines. A bitline contact is formed on the bitline, and second and third pad electrodes, which are respectively connected with the bitline and the first pad electrode through the bitline contact, are formed on the bitline. Thus, the alignment tolerances of the bitline contact and the storage-node contact are maximized, so that a reliable semiconductor device can be realized.
摘要翻译：公开了一种使用自对准接触的半导体器件及其制造方法。在半导体衬底上形成具有形成在其侧壁上的第一间隔物的栅电极。在半导体衬底中形成由栅电极彼此间隔开的有源区。在栅电极和有源区上形成具有形成在其侧壁上的第二间隔物的位线。在有源区上形成自对准接触，并且在位线之间形成通过接触与有源区连接的第一焊盘电极。在位线上形成位线接触，并且在位线上形成分别与位线和第一焊盘电极通过位线接触连接的第二和第三焊盘电极。因此，位线接触和存储 - 节点接触的对准公差最大化，从而可以实现可靠的半导体器件。

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