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1. 发明授权

US6114253A Via patterning for poly(arylene ether) used as an inter-metal dielectric 有权
标题翻译：通过用作金属间电介质的聚（亚芳基醚）图案化
公开(公告)号：US6114253A
公开(公告)日：2000-09-05
申请号：US268542
申请日：1999-03-15
申请人： Syun-Ming Jang , Ming-Hsin Huang , Chen-Hua Yu
发明人： Syun-Ming Jang , Ming-Hsin Huang , Chen-Hua Yu
IPC分类号： H01L21/3105 , H01L21/768 , H01L21/302
CPC分类号： H01L21/76802 , H01L21/31055
摘要： A process for removal of residual silicon oxide hardmask used to etch vias in low-k organic polymer dielectric layers is described. The hardmask deteriorates by developing an angular aspect or faceting along the pattern edges when used to etch organic polymer layers in an oxygen/inert gas plasma in a high density plasma etcher. In addition the deterioration of the hardmask during organic polymer etching causes a significant degradation of surface planarity which would result in via-to-via shorts when a second metal layer is patterned over it if the hardmask were left in place. The residual hardmask is selectively removed immediately after the via etch by a soft plasma etch which restores surface planarity and removes via edge facets. The plasma etch has a high selectivity of oxide-to-organic polymer so that the surface irregularities are not transferred to the polymer surface and the exposed metal surface at the base of the via is also unscathed.
摘要翻译：描述了用于去除用于蚀刻低k有机聚合物介电层中的通孔的残余氧化硅硬掩模的工艺。当用于在高密度等离子体蚀刻机中在氧气/惰性气体等离子体中蚀刻有机聚合物层时，通过沿着图案边缘开发角度方面或刻面，硬掩模劣化。此外，在有机聚合物蚀刻期间硬掩模的劣化导致表面平面度的显着降低，这会在将硬掩模留在原位时在其上形成第二金属层时导致通孔到通孔短路。在通过等离子体蚀刻的通孔蚀刻之后立即选择性地去除残余硬掩模，该等离子体蚀刻恢复表面平面度并且经由边缘面移除。等离子体蚀刻具有高的氧化物对有机聚合物的选择性，使得表面不规则性不会转移到聚合物表面，并且通孔底部的暴露的金属表面也是无损的。

2. 发明申请

US20060027932A1 Interconnect with composite barrier layers and method for fabricating the same 有权
标题翻译：与复合阻挡层互连及其制造方法
公开(公告)号：US20060027932A1
公开(公告)日：2006-02-09
申请号：US11240216
申请日：2005-09-30
申请人： Chen-Hua Yu , Horng-Huei Tseng , Syun-Ming Jang , Chenming Hu
发明人： Chen-Hua Yu , Horng-Huei Tseng , Syun-Ming Jang , Chenming Hu
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L21/76846
摘要： Composite ALD-formed diffusion barrier layers. In a preferred embodiment, a composite conductive layer is composed of a diffusion barrier layer and/or a low-resistivity metal layer formed by atomic layer deposition (ALD) lining a damascene opening in dielectrics, serving as diffusion blocking and/or adhesion improvement. The preferred composite diffusion barrier layers are dual titanium nitride layers or dual tantalum nitride layers, triply laminar of tantalum, tantalum nitride and tantalum-rich nitride, or tantalum, tantalum nitride and tantalum, formed sequentially on the opening by way of ALD.
摘要翻译：复合ALD形成的扩散阻挡层。在优选实施例中，复合导电层由扩散阻挡层和/或由电介质中的镶嵌开口衬底的原子层沉积（ALD）形成的低电阻金属层组成，用作扩散阻挡和/或粘附改善。优选的复合扩散阻挡层是通过ALD在开口上依次形成的双氮化钛层或双氮化钽层，三层层状的钽，氮化钽和富钽的氮化物，或钽，氮化钽和钽。

3. 发明授权

US06559040B1 Process for polishing the top surface of a polysilicon gate 有权
标题翻译：抛光多晶硅栅极顶表面的工艺
公开(公告)号：US06559040B1
公开(公告)日：2003-05-06
申请号：US09421517
申请日：1999-10-20
申请人： Chen-Hua Yu , Chung-Long Chang , Syun-Ming Jang
发明人： Chen-Hua Yu , Chung-Long Chang , Syun-Ming Jang
IPC分类号： H01L21302
CPC分类号： H01L21/3212 , H01L21/28035
摘要： The process of polishing the top surface of a polysilicon gate electrode often results in significant loss of material before adequate smoothness is achieved. This problem is overcome in the present invention by laying down a thin layer of a dielectric on the surface of the polysilicon prior to the application of CMP. This provides a sacrificial layer that facilitates the polishing operation and results in a polysilicon surface that is both very smooth and achievable with minimum loss of polysilicon.
摘要翻译：抛光多晶硅栅电极的顶表面的过程通常在达到足够的平滑度之前导致材料的显着损失。在本发明中通过在施加CMP之前在多晶硅的表面上放置介电层的薄层来克服该问题。这提供了促进抛光操作的牺牲层，并且导致多晶硅表面非常平滑并且可以以最小的多晶硅损失实现。

4. 发明授权

US06500753B2 Method to reduce the damages of copper lines 有权
标题翻译：减少铜线损坏的方法
公开(公告)号：US06500753B2
公开(公告)日：2002-12-31
申请号：US09838209
申请日：2001-04-20
申请人： Syun-Ming Jang , Ying-Ho Chen , Jih-Churng Twu , Chen-Hua Yu
发明人： Syun-Ming Jang , Ying-Ho Chen , Jih-Churng Twu , Chen-Hua Yu
IPC分类号： H01L218238
CPC分类号： H01L21/7684 , H01L21/76838 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： The invention teaches the addition of copper lines, these copper lines to be added to isolated copper lines or to selected copper lines within a collection of copper lines. The invention also teaches the addition of copper end caps to isolated copper lines or to selected copper lines within a collection of copper lines. The invention further teaches the widening of copper lines for isolated copper lines or selected copper lines within a collection of copper lines.
摘要翻译：本发明教导了铜线的添加，这些铜线被添加到隔离铜线或铜线集合内的选定铜线。本发明还教导了将铜端盖添加到铜线集合中的隔离铜线或铜线。本发明进一步教导了铜线集合中用于隔离铜线或选定铜线的铜线的扩大。

5. 发明授权

US06458689B2 Use of PE-SiON or PE-Oxide for contact or via photo and for defect reduction with oxide and w chemical-mechanical polish 有权
标题翻译：使用PE-SiON或PE氧化物进行接触或通过照相和氧化物和化学机械抛光剂进行缺陷还原
公开(公告)号：US06458689B2
公开(公告)日：2002-10-01
申请号：US09818714
申请日：2001-03-28
申请人： Chen-Hua Yu , Syun-Ming Jang , Tsu Shih , Anthony Yen , Jih-Chuyng Twu
发明人： Chen-Hua Yu , Syun-Ming Jang , Tsu Shih , Anthony Yen , Jih-Chuyng Twu
IPC分类号： H01L214763
CPC分类号： H01L21/0276 , H01L21/31144 , H01L21/3144 , H01L21/3145 , H01L21/7684 , Y10S438/97
摘要： A method forming a protective (SiON or PE-Ox) dielectric anti-reflective coating (DARC) over a dielectric layer after a chemical-mechanical polish dielectric layer planarization process and before a chemical-mechanical polish of a conductive layer used in a contact or via plug formation. A dielectric layer is chemical-mechanical polished thereby creating microscratches in the dielectric layer. The invention's protective SiON or PE-OX DARC layer is formed over the dielectric layer whereby the protective SiON or PE-OX DARC layer fills in the microscratches. A first opening is etched in he protective layer and the dielectric layer. A conductive layer is formed over the protective layer and fills the first opening. The conductive layer is chemical-mechanical polished to remove the conductive layer from over the protective layer and to form an interconnect filling the first opening. The protective SiON or PE-OX DARC layer is used as a CMP stop thereby preventing microscratches in the dielectric layer.
摘要翻译：在化学机械抛光介质层平坦化工艺之后和用于接触的导电层的化学机械抛光之前，在电介质层上形成保护性（SiON或PE-Ox）电介质抗反射涂层（DARC）的方法或通过插塞形成。电介质层被化学机械抛光，从而在电介质层中形成微细结构。本发明的保护性SiON或PE-OX DARC层形成在电介质层上，由此保护性SiON或PE-OX DARC层填充在微细凹槽中。在其保护层和电介质层中蚀刻第一开口。导电层形成在保护层上并填充第一开口。导电层被化学机械抛光以从保护层上方移除导电层并形成填充第一开口的互连。使用保护性SiON或PE-OX DARC层作为CMP阻挡层，从而防止电介质层中的微细纹。

6. 发明授权

US06245691B1 Ozone-teos method for forming with attenuated surface sensitivity a silicon oxide dielectric layer upon a thermally oxidized silicon substrate layer 失效
标题翻译：用于在热氧化硅衬底层上形成具有衰减表面灵敏度的氧化硅介电层的臭氧陶瓷方法
公开(公告)号：US06245691B1
公开(公告)日：2001-06-12
申请号：US09086770
申请日：1998-05-29
申请人： Syun-Ming Jang , Chen-Hua Yu
发明人： Syun-Ming Jang , Chen-Hua Yu
IPC分类号： H01L2131
CPC分类号： H01L21/02164 , C23C16/0218 , C23C16/0272 , C23C16/402 , H01L21/02271 , H01L21/02304 , H01L21/31612 , H01L21/31662
摘要： A method for forming a silicon oxide dielectric layer within a microelectronics fabrication. There is first provided a silicon substrate layer employed within a microelectronics fabrication. There is then formed employing the silicon substrate a thermal silicon oxide layer through thermal oxidation of the silicon substrate layer. There is then formed upon the thermal silicon oxide layer a second silicon oxide layer formed through use of a thermal chemical vapor deposition (CVD) method employing ozone as an oxidant and tetraethylorthosilicate (TEOS) as a silicon source material. The thermal chemical vapor deposition (CVD) method also employs a reactor chamber pressure of from about 40 to about 80 torr. The second silicon oxide layer is formed with an attenuated surface sensitivity of the second silicon oxide layer with respect to the thermal silicon oxide layer. The method is particularly desirable when forming trench isolation regions within isolation trenches within silicon semiconductor substrates employed within integrated circuit microelectronics fabrications.
摘要翻译：一种在微电子制造中形成氧化硅介电层的方法。首先提供在微电子制造中使用的硅衬底层。然后通过硅衬底层的热氧化形成硅衬底热硅氧化物层。然后在热氧化硅层上形成第二氧化硅层，该第二氧化硅层通过使用以臭氧作为氧化剂的热化学气相沉积（CVD）方法和作为硅源材料的原硅酸四乙酯（TEOS）形成。热化学气相沉积（CVD）方法也采用约40至约80托的反应室压力。第二氧化硅层形成有相对于热氧化硅层的第二氧化硅层的衰减的表面灵敏度。当在集成电路微电子学制造中使用的硅半导体衬底内的隔离沟槽内形成沟槽隔离区域时，该方法是特别需要的。

7. 发明授权

US6010948A Shallow trench isolation process employing a BPSG trench fill 有权
标题翻译：采用BPSG沟槽填充的浅沟槽隔离工艺
公开(公告)号：US6010948A
公开(公告)日：2000-01-04
申请号：US244879
申请日：1999-02-05
申请人： Chen-Hua Yu , Syun-Ming Jang
发明人： Chen-Hua Yu , Syun-Ming Jang
IPC分类号： H01L21/762
CPC分类号： H01L21/76224
摘要： A process for creating BPSG filled, shallow trench isolation regions, in a semiconductor substrate, has been developed. The process features the use of a BPSG layer with about 4 to 4.5 weight percent B.sub.2 O.sub.3, and about 4 to 4.5 weight percent P.sub.2 O.sub.5, in silicon oxide. This BPSG composition, when subjected to a high temperature anneal procedure, results in softening, or reflowing, of the BPSG layer, eliminating seams or voids, in the BPSG layer, that may have been present after BPSG deposition. The removal rate of BPSG, is lower than the removal rate of silicon oxide layer, in buffered HF solutions, thus allowing several buffered HF procedures to be performed without recessing of BPSG in the shallow trench. In addition this composition of BPSG performs as a gettering material for mobile ions, thus contributing to yield and reliability improvements, when used at the isolation region for MOSFET devices.
摘要翻译：已经开发了用于在半导体衬底中产生BPSG填充的浅沟槽隔离区的工艺。该方法的特征在于在氧化硅中使用具有约4至4.5重量％的B 2 O 3和约4至4.5重量％的P 2 O 5的BPSG层。当经过高温退火过程时，该BPSG组合物导致BPSG层的软化或回流，消除了在BPSG沉积后可能存在的BPSG层中的接缝或空隙。 BPSG的去除率低于缓冲HF溶液中氧化硅层的去除率，从而允许在浅沟槽中不进行BPSG的凹陷而执行几个缓冲的HF程序。此外，BPSG的这种组合作为移动离子的吸气材料，当在MOSFET器件的隔离区域使用时，有助于提高产量和可靠性。

8. 发明授权

US07187084B2 Damascene method employing composite etch stop layer 有权
标题翻译：使用复合蚀刻停止层的镶嵌方法
公开(公告)号：US07187084B2
公开(公告)日：2007-03-06
申请号：US10760905
申请日：2004-01-20
申请人： Syun-Ming Jang , Chung-Shi Liu , Chen-Hua Yu
发明人： Syun-Ming Jang , Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76832 , H01L21/0214 , H01L21/02164 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/31105 , H01L21/31116 , H01L21/31127 , H01L21/31138 , H01L21/3144 , H01L21/3145 , H01L21/31612 , H01L21/76807
摘要： A damascene structure is provided comprising a substrate, a lower intermetal dielectric layer over the substrate, an exposed conductive structure within the lower intermetal dielectric layer, a composite etch stop layer over the lower intermetal dielectric layer and the exposed conductive structure; the composite etch stop layer comprising a first lower sub-layer and a second upper sub-layer, an upper intermetal dielectric layer over the composite etch stop layer, a trench interconnection opening forming within the upper intermetal dielectric layer and the composite etch stop layer, the trench interconnection opening exposing the conductive structure, a barrier metal layer at least lining the trench interconnection opening. and a conductor plug within the trench interconnection opening, contacting the conductive structure. The upper surface of the barrier metal layer is coplanar with the upper surface of the conductor plug.
摘要翻译：提供一种镶嵌结构，其包括基底，在该基底上的下部金属间电介质层，该下部金属间电介质层内的暴露的导电结构，该下部金属间介电层上的复合蚀刻停止层和该暴露的导电结构; 所述复合蚀刻停止层包括第一下部子层和第二上部子层，复合蚀刻停止层上方的上部金属间介电层，在上部金属间介电层和复合蚀刻停止层中形成的沟槽互连开口，所述沟槽互连开口暴露所述导电结构，至少衬垫所述沟槽互连开口的阻挡金属层。以及沟槽互连开口内的导体插头，与导电结构接触。阻挡金属层的上表面与导体插塞的上表面共面。

9. 发明授权

US06958291B2 Interconnect with composite barrier layers and method for fabricating the same 有权
标题翻译：与复合阻挡层互连及其制造方法
公开(公告)号：US06958291B2
公开(公告)日：2005-10-25
申请号：US10654757
申请日：2003-09-04
申请人： Chen-Hua Yu , Horng-Huei Tseng , Syun-Ming Jang , Chenming Hu
发明人： Chen-Hua Yu , Horng-Huei Tseng , Syun-Ming Jang , Chenming Hu
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76846
摘要： Composite ALD-formed diffusion barrier layers. In a preferred embodiment, a composite conductive layer is composed of a diffusion barrier layer and/or a low-resistivity metal layer formed by atomic layer deposition (ALD) lining a damascene opening in dielectrics, serving as diffusion blocking and/or adhesion improvement. The preferred composite diffusion barrier layers are dual titanium nitride layers or dual tantalum nitride layers, triply laminar of tantalum, tantalum nitride and tantalum-rich nitride, or tantalum, tantalum nitride and tantalum, formed sequentially on the opening by way of ALD.
摘要翻译：复合ALD形成的扩散阻挡层。在优选实施例中，复合导电层由扩散阻挡层和/或由电介质中的镶嵌开口衬底的原子层沉积（ALD）形成的低电阻金属层组成，用作扩散阻挡和/或粘附改善。优选的复合扩散阻挡层是通过ALD在开口上依次形成的双氮化钛层或双氮化钽层，三层层状的钽，氮化钽和富钽的氮化物，或钽，氮化钽和钽。

10. 发明授权

US06706577B1 Formation of dual gate oxide by two-step wet oxidation 失效
标题翻译：通过两步湿氧化形成双栅氧化物
公开(公告)号：US06706577B1
公开(公告)日：2004-03-16
申请号：US09298879
申请日：1999-04-26
申请人： Jih-Churng Twu , Syun-Ming Jang , Chen-Hua Yu
发明人： Jih-Churng Twu , Syun-Ming Jang , Chen-Hua Yu
IPC分类号： H01L218238
CPC分类号： H01L21/823857 , H01L27/10894
摘要： A method of simultaneously forming differential gate oxide for both high and low voltage transistors using a two-step wet oxidation process is described. A semiconductor substrate is provided wherein active areas of the substrate are isolated from other active areas and wherein there is at least one low voltage area in which a low voltage transistor will be formed and at least one high voltage area in which a high voltage transistor will be formed. The surface of the semiconductor substrate is wet oxidized to form a first layer of gate oxide on the surface of the semiconductor substrate in the active areas. The low voltage active area is covered with a mask. The surface of the semiconductor substrate is wet oxidized again where it is not covered by the mask to form a second layer of gate oxide under the first gate oxide layer in the high voltage active area. The mask is removed. A layer of polysilicon is deposited overlying the first gate oxide layer in the low voltage active area and overlying the second gate oxide layer in the high voltage active area and patterned to form gate electrodes for the low voltage and high voltage transistors in the fabrication of an integrated circuit.
摘要翻译：描述了使用两步湿氧化工艺同时形成用于高压和低压晶体管的差分栅极氧化物的方法。提供一种半导体衬底，其中衬底的有源区域与其他有源区域隔离，并且其中存在将形成低压晶体管的至少一个低电压区域和至少一个高电压区域，其中高压晶体管将形成。半导体衬底的表面被湿式氧化以在有源区域中在半导体衬底的表面上形成第一层栅极氧化物层。低电压有源区域用掩模覆盖。半导体衬底的表面被再次湿式氧化，其中未被掩模覆盖，以在高电压有源区的第一栅氧化层下形成第二层栅氧化层。去除面具。一层多晶硅被沉积在低电压有源区中的第一栅极氧化物层上并覆盖在高电压有源区中的第二栅极氧化物层上并被图案化以在制造中形成低电压和高压晶体管的栅电极集成电路。

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