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1. 发明授权

US06458689B2 Use of PE-SiON or PE-Oxide for contact or via photo and for defect reduction with oxide and w chemical-mechanical polish 有权
标题翻译：使用PE-SiON或PE氧化物进行接触或通过照相和氧化物和化学机械抛光剂进行缺陷还原
公开(公告)号：US06458689B2
公开(公告)日：2002-10-01
申请号：US09818714
申请日：2001-03-28
申请人： Chen-Hua Yu , Syun-Ming Jang , Tsu Shih , Anthony Yen , Jih-Chuyng Twu
发明人： Chen-Hua Yu , Syun-Ming Jang , Tsu Shih , Anthony Yen , Jih-Chuyng Twu
IPC分类号： H01L214763
CPC分类号： H01L21/0276 , H01L21/31144 , H01L21/3144 , H01L21/3145 , H01L21/7684 , Y10S438/97
摘要： A method forming a protective (SiON or PE-Ox) dielectric anti-reflective coating (DARC) over a dielectric layer after a chemical-mechanical polish dielectric layer planarization process and before a chemical-mechanical polish of a conductive layer used in a contact or via plug formation. A dielectric layer is chemical-mechanical polished thereby creating microscratches in the dielectric layer. The invention's protective SiON or PE-OX DARC layer is formed over the dielectric layer whereby the protective SiON or PE-OX DARC layer fills in the microscratches. A first opening is etched in he protective layer and the dielectric layer. A conductive layer is formed over the protective layer and fills the first opening. The conductive layer is chemical-mechanical polished to remove the conductive layer from over the protective layer and to form an interconnect filling the first opening. The protective SiON or PE-OX DARC layer is used as a CMP stop thereby preventing microscratches in the dielectric layer.
摘要翻译：在化学机械抛光介质层平坦化工艺之后和用于接触的导电层的化学机械抛光之前，在电介质层上形成保护性（SiON或PE-Ox）电介质抗反射涂层（DARC）的方法或通过插塞形成。电介质层被化学机械抛光，从而在电介质层中形成微细结构。本发明的保护性SiON或PE-OX DARC层形成在电介质层上，由此保护性SiON或PE-OX DARC层填充在微细凹槽中。在其保护层和电介质层中蚀刻第一开口。导电层形成在保护层上并填充第一开口。导电层被化学机械抛光以从保护层上方移除导电层并形成填充第一开口的互连。使用保护性SiON或PE-OX DARC层作为CMP阻挡层，从而防止电介质层中的微细纹。

2. 发明授权

US06228760B1 Use of PE-SiON or PE-OXIDE for contact or via photo and for defect reduction with oxide and W chemical-mechanical polish 有权
标题翻译：使用PE-SiON或PE-OXIDE进行接触或通过照相和氧化物和W化学机械抛光的缺陷还原
公开(公告)号：US06228760B1
公开(公告)日：2001-05-08
申请号：US09263563
申请日：1999-03-08
申请人： Chen-Hua Yu , Syun-Ming Jang , Tsu Shih , Anthony Yen , Jih-Churng Twu
发明人： Chen-Hua Yu , Syun-Ming Jang , Tsu Shih , Anthony Yen , Jih-Churng Twu
IPC分类号： H01L214763
CPC分类号： H01L21/0276 , H01L21/31144 , H01L21/3144 , H01L21/3145 , H01L21/7684 , Y10S438/97
摘要： A method forming a protective (SiON or PE-Ox) dielectric anti-reflective coating (DARC) over a di electric layer after a chemical-mechanical polish dielectric layer planarization process and before a chemical-mechanical polish of a conductive layer used in a contact or via plug formation. A dielectric layer is chemical-mechanical polished thereby creating microscratches in the dielectric layer. The invention's protective SiON or PE-OX DARC layer is formed over the dielectric layer whereby the protective SiON or PE-OX DARC layer fills in the microscratches. A first opening is etched in he protective layer and the dielectric layer. A conductive layer is formed over the protective layer and fills the first opening. The conductive layer is chemical-mechanical polished to remove the conductive layer from over the protective layer and to form an interconnect filling the first opening. The protective SiON or PE-OX DARC layer is used as a CMP stop thereby preventing microscratches in the dielectric layer.
摘要翻译：在化学机械抛光介电层平坦化工艺之后和用于接触的导电层的化学机械抛光之前，在二电层上形成保护性（SiON或PE-Ox）电介质抗反射涂层（DARC）的方法或通过插塞形成。电介质层被化学机械抛光，从而在电介质层中形成微细结构。本发明的保护性SiON或PE-OX DARC层形成在电介质层上，由此保护性SiON或PE-OX DARC层填充在微细凹槽中。在其保护层和电介质层中蚀刻第一开口。导电层形成在保护层上并填充第一开口。导电层被化学机械抛光以从保护层上方移除导电层并形成填充第一开口的互连。使用保护性SiON或PE-OX DARC层作为CMP阻挡层，从而防止电介质层中的微细纹。

3. 发明授权

US06362093B1 Dual damascene method employing sacrificial via fill layer 有权
公开(公告)号：US06362093B1
公开(公告)日：2002-03-26
申请号：US09378459
申请日：1999-08-20
申请人： Syun-Ming Jang , Anthony Yen , Hung-Chang Hsieh
发明人： Syun-Ming Jang , Anthony Yen , Hung-Chang Hsieh
IPC分类号： H01L214763
CPC分类号： H01L21/76808
摘要： A method for forming through a microelectronic layer a via contiguous with a trench. There is first provided a substrate. There is then formed over the substrate a first microelectronic layer. There is then formed upon the first microelectronic layer an etch stop layer. There is then formed upon the etch stop layer a second microelectronic layer. There is then formed over the second microelectronic layer a first patterned photoresist layer which defines the location of a via to be formed through the second microelectronic layer, the etch stop layer and the first microelectronic layer. There is then etched, while employing a first etch method which employs the first patterned photoresist layer as a first etch mask layer, the second microelectronic layer, the etch stop layer and the first microelectronic layer to form a corresponding patterned second microelectronic layer, patterned etch stop layer and patterned first microelectronic layer which define the via. There is then formed into at least a lower portion of the via a sacrificial via fill layer. There is then formed over the patterned second microelectronic layer a patterned second photoresist layer which defines the location of a trench to be formed through the patterned second microelectronic layer, where a first areal dimension of the via is smaller than and contained within a second areal dimension of the trench. There is then etched, while employing a second etch method which employs the second patterned photoresist layer as a second etch mask layer, the patterned second microelectronic layer to form a twice patterned second microelectronic layer which defines the trench, while not completely etching the sacrificial via fill layer within the via to form a no greater than partially etched sacrificial via fill layer within the via. Finally, there is then stripped the no greater than partially etched sacrificial via fill layer from the via to form the reduced height via contiguous with the trench.

4. 发明授权

US08785084B2 Method for mask fabrication and repair 有权
标题翻译：掩模制造和修理方法
公开(公告)号：US08785084B2
公开(公告)日：2014-07-22
申请号：US13602916
申请日：2012-09-04
申请人： Yen-Cheng Lu , Shinn-Sheng Yu , Anthony Yen
发明人： Yen-Cheng Lu , Shinn-Sheng Yu , Anthony Yen
IPC分类号： G03F1/72 , G03F1/84 , G03F1/24
CPC分类号： G03F1/24 , G03F1/72
摘要： A method for repairing phase defects for an extreme ultraviolet (EUV) mask is disclosed. The method includes receiving a patterned EUV mask with at least one phase-defect region, determining location and size of the phase-defect region, depositing an absorber material to cover the phase-defect region and removing a portion of the patterned absorption layer near the phase-defect region in the patterned EUV mask to form an absorber-absent region.
摘要翻译：公开了用于修复极紫外（EUV）掩模的相缺陷的方法。该方法包括接收具有至少一个相位缺陷区域的图案化EUV掩模，确定相缺陷区域的位置和尺寸，沉积吸收材料以覆盖相缺陷区域并且去除图案化吸收层附近的一部分图案化的EUV掩模中的相缺陷区域以形成不存在吸收体的区域。

5. 发明申请

US20140065521A1 METHOD FOR MASK FABRICATION AND REPAIR 有权
标题翻译：面膜制作和修复方法
公开(公告)号：US20140065521A1
公开(公告)日：2014-03-06
申请号：US13602916
申请日：2012-09-04
申请人： Yen-Cheng Lu , Shinn-Sheng Yu , Anthony Yen
发明人： Yen-Cheng Lu , Shinn-Sheng Yu , Anthony Yen
IPC分类号： G03F1/24
CPC分类号： G03F1/24 , G03F1/72
摘要： A method for repairing phase defects for an extreme ultraviolet (EUV) mask is disclosed. The method includes receiving a patterned EUV mask with at least one phase-defect region, determining location and size of the phase-defect region, depositing an absorber material to cover the phase-defect region and removing a portion of the patterned absorption layer near the phase-defect region in the patterned EUV mask to form an absorber-absent region.
摘要翻译：公开了用于修复极紫外（EUV）掩模的相缺陷的方法。该方法包括接收具有至少一个相位缺陷区域的图案化EUV掩模，确定相缺陷区域的位置和尺寸，沉积吸收材料以覆盖相缺陷区域并且去除图案化吸收层附近的一部分图案化的EUV掩模中的相缺陷区域以形成不存在吸收体的区域。

6. 发明授权

US08656318B2 System and method for combined intraoverlay metrology and defect inspection 有权
标题翻译：组合内部测量和缺陷检查的系统和方法
公开(公告)号：US08656318B2
公开(公告)日：2014-02-18
申请号：US13464116
申请日：2012-05-04
申请人： Hsin-Chang Lee , Chia-Jen Chen , Yeh Lee-Chih , Sheng-Chi Chin , Ting-Hao Hsu , Anthony Yen
发明人： Hsin-Chang Lee , Chia-Jen Chen , Yeh Lee-Chih , Sheng-Chi Chin , Ting-Hao Hsu , Anthony Yen
IPC分类号： G06F17/50
CPC分类号： G03F1/84 , G03F1/72
摘要： A method and system for measuring layer overlay and for inspecting a mask for defects unrelated to overlay utilizing a singe comprehensive tool is disclosed. An exemplary method includes receiving a mask design database that corresponds to a mask and has a die area with a mask database feature. A mask image of the mask is received, and a comprehensive inspection system compares the mask image to the mask design database in order to detect mask defects that are not related to layer alignment. The system produces mask defect information corresponding to the mask defects. The comprehensive inspection system also compares the mask image to the mask design database to determine a database-to-mask offset. From the database-to-mask offset, a mask overlay characteristic is determined.
摘要翻译：公开了一种用于测量层叠覆盖层的方法和系统，并且用于使用单个综合工具来检查与覆盖无关的缺陷的掩模。一种示例性方法包括接收对应于掩模并且具有掩模数据库特征的管芯区域的掩模设计数据库。接收掩模的掩模图像，并且综合检查系统将掩模图像与掩模设计数据库进行比较，以便检测与层对齐无关的掩模缺陷。系统产生对应于掩模缺陷的掩模缺陷信息。综合检查系统还将掩模图像与掩模设计数据库进行比较，以确定数据库对掩模偏移量。从数据库到掩码偏移，确定掩模覆盖特性。

7. 发明申请

US20130260289A1 METHOD OF MAKING A LITHOGRAPHY MASK 审中-公开
标题翻译：制作光刻面膜的方法
公开(公告)号：US20130260289A1
公开(公告)日：2013-10-03
申请号：US13437565
申请日：2012-04-02
申请人： Yun-Yue Lin , Hsin-Chang Lee , Chia-Jen Chen , Ta-Cheng Lien , Anthony Yen
发明人： Yun-Yue Lin , Hsin-Chang Lee , Chia-Jen Chen , Ta-Cheng Lien , Anthony Yen
IPC分类号： G03F1/78 , B82Y40/00
CPC分类号： B82Y10/00 , B82Y40/00 , G03F1/50 , G03F1/68 , G03F1/78
摘要： A method of fabricating a lithography mask with carbon-based-charging-dissipation (CBCD) layer is disclosed. The method includes providing a substrate, depositing an opaque layer on the substrate, coating a photoresist and depositing a charging dissipation layer on the photoresist. The photoresist is patterned by an electron-beam writing. The CBCD layer is removed during developing the photoresist.
摘要翻译：公开了一种制造具有碳基带电耗散（CBCD）层的光刻掩模的方法。该方法包括提供衬底，在衬底上沉积不透明层，涂覆光致抗蚀剂并在光致抗蚀剂上沉积充电耗散层。光刻胶通过电子束写入进行图案化。在显影光致抗蚀剂期间去除CBCD层。

8. 发明授权

US08492054B2 Mechanisms for patterning fine features 有权
标题翻译：图案精细特征的机制
公开(公告)号：US08492054B2
公开(公告)日：2013-07-23
申请号：US13072169
申请日：2011-03-25
申请人： Shinn-Sheng Yu , Anthony Yen
发明人： Shinn-Sheng Yu , Anthony Yen
IPC分类号： G03F1/22 , G03F1/24
CPC分类号： G03F1/24 , B82Y10/00 , B82Y40/00 , G03F1/76
摘要： The embodiments described provide mechanisms for patterning features for advanced technology nodes with extreme ultraviolet lithography (EUVL) tools. One or more EUV pre-masks are generated by using a mask writer to form an EUV mask with an EUV scanner. The wafers are then patterned by using the EUV mask. The demagnification factor of the EUV scanner(s) used in preparing the EUV mask by exposing the EUV pre-mask(s) enable the wafers prepared by such mechanisms to meet the requirements for the advanced technology nodes.
摘要翻译：所描述的实施例提供了用于使用极紫外光刻（EUVL）工具对高级技术节点进行图形化特征的机制。通过使用掩模写入器与EUV扫描器形成EUV掩模来生成一个或多个EUV预掩模。然后通过使用EUV掩模对晶片进行构图。通过暴露EUV预掩模来制备EUV掩模所使用的EUV扫描仪的缩小因子使得由这些机构制备的晶片能够满足先进技术节点的要求。

9. 发明授权

US08241823B2 Method of fabrication of a semiconductor device having reduced pitch 有权
标题翻译：具有减小的间距的半导体器件的制造方法
公开(公告)号：US08241823B2
公开(公告)日：2012-08-14
申请号：US13248932
申请日：2011-09-29
申请人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Shao-Ming Yu , Chang-Yun Chang , Jeff J. Xu , Clement Hsingjen Wann
发明人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Shao-Ming Yu , Chang-Yun Chang , Jeff J. Xu , Clement Hsingjen Wann
IPC分类号： G03G5/00 , H01L21/302 , H01L21/461
CPC分类号： H01L27/0203 , G03F1/00 , G03F1/36 , H01L21/3086 , H01L21/823431 , H01L29/66795
摘要： Provided is a photolithography apparatus including a photomask. The photomask includes a pattern having a plurality of features, in an example, dummy line features. The pattern includes a first region being in the form of a localized on-grid array and a second region where at least one of the features has an increased width. The apparatus may include a second photomask which may define an active region. The feature with an increased width may be adjacent, and outside, the defined active region.
摘要翻译：提供了一种包括光掩模的光刻设备。光掩模包括具有多个特征的图案，在示例中为虚线特征。该图案包括呈局部网格阵列形式的第一区域和其中至少一个特征具有增加的宽度的第二区域。该装置可以包括可以限定有源区域的第二光掩模。具有增加的宽度的特征可以与所定义的有效区域相邻并且在外部。

10. 发明授权

US08039179B2 Integrated circuit layout design 有权
标题翻译：集成电路布局设计
公开(公告)号：US08039179B2
公开(公告)日：2011-10-18
申请号：US12980764
申请日：2010-12-29
申请人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Shao-Ming Yu , Chang-Yun Chang , Jeff J. Xu , Clement Hsingjen Wann
发明人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Shao-Ming Yu , Chang-Yun Chang , Jeff J. Xu , Clement Hsingjen Wann
IPC分类号： G03C5/00 , G03F9/00
CPC分类号： H01L27/0203 , G03F1/00 , G03F1/36 , H01L21/3086 , H01L21/823431 , H01L29/66795
摘要： Provided is a photolithography apparatus including a photomask. The photomask includes a pattern having a plurality, of features, in an example, dummy line features. The pattern includes a first region being in the form of a localized on-grid array and a second region where at least one of the features has an increased width. The apparatus may include a second photomask which may define an active region. The feature with an increased width may be adjacent, and outside, the defined active region.
摘要翻译：提供了一种包括光掩模的光刻设备。光掩模包括具有多个特征的图案，在示例中为假线特征。该图案包括呈局部网格阵列形式的第一区域和其中至少一个特征具有增加的宽度的第二区域。该装置可以包括可以限定有源区域的第二光掩模。具有增加的宽度的特征可以与所定义的有效区域相邻并且在外部。

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