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1. 发明授权

US06265294B1 Integrated circuit having double bottom anti-reflective coating layer 有权
标题翻译：具有双层防反射涂层的集成电路
公开(公告)号：US06265294B1
公开(公告)日：2001-07-24
申请号：US09373084
申请日：1999-08-12
申请人： Stephen Keetai Park , Guarionex Morales , Bharath Rangarajan , Jeff Shields
发明人： Stephen Keetai Park , Guarionex Morales , Bharath Rangarajan , Jeff Shields
IPC分类号： H01L21425
CPC分类号： H01L23/5329 , H01L21/0276 , H01L21/31144 , H01L21/3144 , H01L21/76829 , H01L21/76897 , H01L2924/0002 , H01L2924/00
摘要： A fabrication method reduces the amount of discoloration on interlevel dielectric layers due to anti-reflective coatings (ARC). The invention utilizes a barrier layer, such as, silicon nitride (SiN) that prevents the anti-reflective coating from contacting the interlevel dielectric layer (ILD0). The anti-reflective coating can be silicon oxynitride (SiON) deposited by LPCVD or PECVD.
摘要翻译：制造方法减少了由于抗反射涂层（ARC）引起的层间电介质层上的变色量。本发明利用阻挡层，例如防止抗反射涂层与层间介质层（ILD0）接触的氮化硅（SiN）。抗反射涂层可以是通过LPCVD或PECVD沉积的氮氧化硅（SiON）。

2. 发明授权

US06420104B1 Method of reducing contact size by spacer filling 失效
标题翻译：通过间隔物填充减小接触尺寸的方法
公开(公告)号：US06420104B1
公开(公告)日：2002-07-16
申请号：US09705941
申请日：2000-11-03
申请人： Bharath Rangarajan , Stephen Keetai Park , Guarionex Morales
发明人： Bharath Rangarajan , Stephen Keetai Park , Guarionex Morales
IPC分类号： H01L214763
CPC分类号： H01L21/76831 , H01L21/76816 , H01L21/76832
摘要： A method of reducing contact size in an integrated circuit includes providing an insulating layer over a semiconductor substrate including a plurality of gate structures, creating an aperture extending through the insulating layer and having side walls, providing a spacer on the side walls of the aperture, and providing a contact in the aperture. The lateral sides of the contact abut the spacer. A contact structure is also disclosed in which a spacer separates a contact from a gate structure to avoid charge gain or loss between the contact and gate structure.
摘要翻译：减小集成电路中的接触尺寸的方法包括在包括多个栅极结构的半导体衬底之上提供绝缘层，形成延伸穿过绝缘层并具有侧壁的孔，在孔的侧壁上提供间隔物，并在孔中提供接触。接触件的侧面靠垫片。还公开了一种接触结构，其中隔离物将接触与栅极结构分离以避免接触和栅极结构之间的电荷增益或损耗。

3. 发明授权

US06265273B1 Method of forming rectangular shaped spacers 有权
标题翻译：形成矩形隔片的方法
公开(公告)号：US06265273B1
公开(公告)日：2001-07-24
申请号：US09359502
申请日：1999-07-23
申请人： Steven C. Avanzino , Stephen Keetai Park , Bharath Rangarajan , Jeffrey A. Shields , Larry Yu Wang , Guarionex Morales
发明人： Steven C. Avanzino , Stephen Keetai Park , Bharath Rangarajan , Jeffrey A. Shields , Larry Yu Wang , Guarionex Morales
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/31116
摘要： A method of forming spacers in an integrated circuit is disclosed herein. The method includes providing a gate structure over a semiconductor substrate, depositing a spacer material adjacent lateral sides of the gate structure, and etching the spacer material to form spacers. The spacers have minimal surface area exposed to direct sputter.
摘要翻译：本文公开了一种在集成电路中形成间隔物的方法。该方法包括在半导体衬底上提供栅极结构，在栅极结构的侧面附近沉积间隔物材料，并蚀刻间隔物材料以形成间隔物。间隔物具有暴露于直接溅射的最小表面积。

4. 发明授权

US06287917B1 Process for fabricating an MNOS flash memory device 有权
标题翻译：制造MNOS闪存设备的过程
公开(公告)号：US06287917B1
公开(公告)日：2001-09-11
申请号：US09392675
申请日：1999-09-08
申请人： Stephen Keetai Park , Tim Thurgate , Bharath Rangarajan
发明人： Stephen Keetai Park , Tim Thurgate , Bharath Rangarajan
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/115
摘要： A process for fabricating an MNOS device includes the steps of forming a hardmask containing at least first and second openings over a core array area of a semiconductor substrate. An angle doping process is carried out to form halo regions in precise locations within the substrate at the edges of the first and second openings in the hardmask. Another doping process is carried out to form buried bit-lines in the substrate using the hardmask as a doping mask. Once the halo regions and the buried bit-lines are formed, the hardmask is removed and a composite dielectric layer is formed overlying the substrate. A gate layer is deposited to overlie the composite dielectric layer, and an etching process is carried out to form a control gate electrode and a charge storage electrode in the MNOS device
摘要翻译：制造MNOS器件的方法包括以下步骤：在半导体衬底的芯阵列区域上形成至少包含第一和第二开口的硬掩模。进行角度掺杂处理以在硬掩模中的第一和第二开口的边缘处在衬底内的精确位置中形成晕圈。进行另一种掺杂工艺以使用硬掩模作为掺杂掩模在衬底中形成掩埋位线。一旦形成了光晕区域和掩埋位线，就去除了硬掩模，并且在衬底上形成复合介电层。沉积栅极层以覆盖复合介电层，并且进行蚀刻处理以在MNOS器件中形成控制栅电极和电荷存储电极

5. 发明授权

US07065427B1 Optical monitoring and control of two layers of liquid immersion media 失效
标题翻译：两层液浸介质的光学监测与控制
公开(公告)号：US07065427B1
公开(公告)日：2006-06-20
申请号：US10979367
申请日：2004-11-01
申请人： Srikanteswara Dakshina-Murthy , Bhanwar Singh , Ramkumar Subramanian , Bharath Rangarajan , Khoi A. Phan
发明人： Srikanteswara Dakshina-Murthy , Bhanwar Singh , Ramkumar Subramanian , Bharath Rangarajan , Khoi A. Phan
IPC分类号： G06F19/00 , G02B7/00 , H01L21/00
CPC分类号： G03F7/7085 , G03F7/70341 , G03F7/70591
摘要： A multi-layer immersion medium monitoring system for a lithographic process monitors characteristics of an immersion medium of a semiconductor manufacturing process. The multi-layer immersion medium includes at least a first liquid of a first density (or viscosity) and a second liquid of a lower density (or viscosity), both of which are interspersed between a final optical component and a semiconductor layer. The higher density layer is provided to reduce turbulence in the immersion medium during the lithographic processes. A scatterometry system monitors optical characteristics of the multi-layer immersion medium to effectuate control of a lithographic process.
摘要翻译：用于光刻工艺的多层浸渍介质监测系统监测半导体制造工艺的浸渍介质的特性。多层浸渍介质至少包括第一密度（或粘度）的第一液体和较低密度（或粘度）的第二液体，它们都分散在最终的光学部件和半导体层之间。提供更高密度的层以在光刻过程中减少浸没介质中的湍流。散射测量系统监测多层浸没介质的光学特性，以实现光刻工艺的控制。

6. 发明授权

US06982043B1 Scatterometry with grating to observe resist removal rate during etch 有权
标题翻译：用光栅进行散射测量以观察蚀刻期间的抗蚀剂去除率
公开(公告)号：US06982043B1
公开(公告)日：2006-01-03
申请号：US10382181
申请日：2003-03-05
申请人： Ramkumar Subramanian , Bharath Rangarajan , Catherine B. Labelle , Bhanwar Singh , Christopher F. Lyons
发明人： Ramkumar Subramanian , Bharath Rangarajan , Catherine B. Labelle , Bhanwar Singh , Christopher F. Lyons
IPC分类号： B44C1/22
CPC分类号： H01L22/12 , H01L22/26
摘要： Disclosed are a system and method for monitoring a patterned photoresist clad-wafer structure undergoing an etch process. The system includes a semiconductor wafer structure comprising a substrate, one or more intermediate layers overlying the substrate, and a first patterned photoresist layer overlying the intermediate layers, the semiconductor wafer structure being etched through one or more openings in the photoresist layer; a wafer-etch photoresist monitoring system programmed to obtain data relating to the photoresist layer as the etch process progresses; a pattern-specific grating aligned with the wafer structure and employed in conjunction with the monitoring system, the grating having at least one of a pitch and a critical dimension identical to the first patterned photoresist layer; and a wafer processing controller operatively connected to the monitoring system and adapted to receive data from the monitoring system in order to determine adjustments to a subsequent wafer clean process.
摘要翻译：公开了用于监测经历蚀刻工艺的图案化光致抗蚀剂包覆晶片结构的系统和方法。该系统包括半导体晶片结构，其包括衬底，覆盖衬底的一个或多个中间层和覆盖中间层的第一图案化光致抗蚀剂层，半导体晶片结构通过光致抗蚀剂层中的一个或多个开口进行蚀刻; 晶片蚀刻光刻胶监测系统被编程为随着蚀刻工艺的进行获得与光致抗蚀剂层有关的数据; 与晶片结构对准并与监视系统结合使用的图案特定光栅，光栅具有与第一图案化光致抗蚀剂层相同的间距和临界尺寸中的至少一个; 以及晶片处理控制器，可操作地连接到所述监控系统并且适于从所述监控系统接收数据，以便确定随后的晶片清洁过程的调整。

7. 发明授权

US06954678B1 Artificial intelligence system for track defect problem solving 失效
标题翻译：用于轨道缺陷问题解决的人工智能系统
公开(公告)号：US06954678B1
公开(公告)日：2005-10-11
申请号：US10261650
申请日：2002-09-30
申请人： Khoi A. Phan , Bhanwar Singh , Bharath Rangarajan , Ramkumar Subramanian
发明人： Khoi A. Phan , Bhanwar Singh , Bharath Rangarajan , Ramkumar Subramanian
IPC分类号： G01R31/26 , G05B23/02 , G06F19/00 , H01L21/66
CPC分类号： H01L22/26 , G05B23/0286
摘要： A system and method facilitating lithography defect solution generation is provided. The invention includes a defect solution component and a defect alert component. The defect solution component provides potential solution(s) to a defect within the lithography process utilizing artificial intelligence technique(s) (e.g., Bayesian learning methods that perform analysis over alternative dependent structures and apply a score, Bayesian classifiers and other statistical classifiers, including decision tree learning methods, support vector machines, linear and non-linear regression and/or neural network).
摘要翻译：提供了一种促进光刻缺陷解决方案生成的系统和方法。本发明包括缺陷解决方案组件和缺陷警报组件。缺陷解决方案组件使用人工智能技术（例如，贝叶斯学习方法对替代依赖结构进行分析并应用分数贝叶斯分类器和其他统计分类器，包括决策树学习方法，支持向量机，线性和非线性回归和/或神经网络）。

8. 发明授权

US06905950B2 Growing copper vias or lines within a patterned resist using a copper seed layer 有权
标题翻译：使用铜种子层在图案化抗蚀剂中生长铜通孔或线
公开(公告)号：US06905950B2
公开(公告)日：2005-06-14
申请号：US09893198
申请日：2001-06-27
申请人： Ramkumar Subramanian , Michael K. Templeton , Bhanwar Singh , Bharath Rangarajan
发明人： Ramkumar Subramanian , Michael K. Templeton , Bhanwar Singh , Bharath Rangarajan
IPC分类号： H01L21/768 , H01L21/3205
CPC分类号： H01L21/76885 , H01L21/76879
摘要： The present invention involves a method for fabricating interconnecting lines and vias. According to the invention, copper is grown within the openings in a patterned coating. The patterned coating can be a resist coating or a dielectric coating. Either type of coating can be formed over a copper seed layer, whereby the seed layer is exposed within the pattern gaps. The copper seed layer can also be provided within the pattern gaps after patterning. Copper features are grown within the pattern gaps by plating. Where the patterned coating is a resist, the resist is stripped leaving the copper features in the inverse pattern image. The copper features can be coated with a diffusion barrier layer and a dielectric. The dielectric is polished to leave the dielectric filling the spaces between copper features. The invention provides copper lines and vias without the need for a dielectric or metal etching step. Another benefit of the invention is that lines widths can be increased by trimming the patterned coating prior to growing the copper features.
摘要翻译：本发明涉及制造互连线和通孔的方法。根据本发明，铜在图案化涂层的开口内生长。图案化的涂层可以是抗蚀剂涂层或介电涂层。任何一种类型的涂层可以在铜籽晶层上形成，从而种子层在图案间隙内露出。图案化之后也可以在图案间隙内提供铜籽晶层。铜特征通过电镀在图案间隙内生长。在图案涂层是抗蚀剂的情况下，剥离抗蚀剂，留下逆向图案图案中的铜特征。铜的特征可以涂覆有扩散阻挡层和电介质。电介质被抛光以留下电介质填充铜特征之间的空间。本发明提供铜线和通孔，而不需要电介质或金属蚀刻步骤。本发明的另一个好处是通过在生长铜特征之前修整图案化涂层可以增加线宽。

9. 发明授权

US06879051B1 Systems and methods to determine seed layer thickness of trench sidewalls 失效
标题翻译：确定沟槽侧壁种子层厚度的系统和方法
公开(公告)号：US06879051B1
公开(公告)日：2005-04-12
申请号：US10050454
申请日：2002-01-16
申请人： Bhanwar Singh , Michael K. Templeton , Bharath Rangarajan , Ramkumar Subramanian
发明人： Bhanwar Singh , Michael K. Templeton , Bharath Rangarajan , Ramkumar Subramanian
IPC分类号： C23C16/04 , C23C16/52 , H01L21/31
CPC分类号： C23C16/045 , C23C16/52
摘要： One aspect of the present invention relates to a method to facilitate formation of seed layer portions on sidewall surfaces of a trench formed in a substrate. The method involves the steps of forming a conformal seed layer over a barrier layer disposed conformal to a trench, wherein the trench is formed in the substrate; reflecting a light beam of x-ray radiation at the seed layer sidewall portions; generating a measurement signal based on the reflected portion of the light beam; and determining a thickness of the sidewall portions based on the measurement signal while the sidewall portions are being formed over the trench.
摘要翻译：本发明的一个方面涉及一种促进在衬底中形成的沟槽的侧壁表面上形成种子层部分的方法。该方法包括以下步骤：在与沟槽共形设置的阻挡层上形成保形种子层，其中沟槽形成在衬底中; 在种子层侧壁部分反射x射线辐射的光束; 基于所述光束的反射部分生成测量信号; 以及当在所述沟槽上形成所述侧壁部分时，基于所述测量信号来确定所述侧壁部分的厚度。

10. 发明授权

US06771356B1 Scatterometry of grating structures to monitor wafer stress 失效
标题翻译：光栅结构的散射法监测晶片应力
公开(公告)号：US06771356B1
公开(公告)日：2004-08-03
申请号：US10050626
申请日：2002-01-16
申请人： Christopher F. Lyons , Bhanwar Singh , Steven C. Avanzino , Khoi A. Phan , Bharath Rangarajan , Ramkumar Subramanian , Cyrus E. Tabery
发明人： Christopher F. Lyons , Bhanwar Singh , Steven C. Avanzino , Khoi A. Phan , Bharath Rangarajan , Ramkumar Subramanian , Cyrus E. Tabery
IPC分类号： G01B1116
CPC分类号： G01B11/165
摘要： A system for monitoring a fabrication process is provided. The system includes one or more light sources, each light source directing light to one or more gratings on a wafer. Light reflected from the gratings is collected by a measuring system that processes the collected light. The collected light is indicative of distortion due to stress at respective portions of the wafer. The measuring system provides distortion/stress related data to a processor that determines the acceptability of the distortion of the respective portions of the wafer. The collected light may be analyzed by scatterometry systems to produce scatterometry signatures associated with distortion and to produce feed-forward control information that can be employed to control semiconductor fabrication processes.
摘要翻译：提供了一种用于监视制造工艺的系统。该系统包括一个或多个光源，每个光源将光引导到晶片上的一个或多个光栅。从光栅反射的光被处理收集的光的测量系统收集。所收集的光指示由于晶片的各个部分处的应力引起的变形。测量系统向处理器提供失真/应力相关数据，该处理器确定晶片各部分的失真的可接受性。收集的光可以通过散射测量系统进行分析，以产生与失真相关联的散射仪签名并产生可用于控制半导体制造过程的前馈控制信息。

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