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1. 发明授权

US07521768B2 Electric device comprising an LDMOS transistor 有权
标题翻译：电子装置包括LDMOS晶体管
公开(公告)号：US07521768B2
公开(公告)日：2009-04-21
申请号：US10569171
申请日：2004-08-24
申请人： Stephan Jo Cecile Henri Theeuwen , Freerk Van Rijs , Petra Christina Anna Hammes , Ivo Bernhard Pouwel , Hendrikus Ferdinand Franciscus Jos
发明人： Stephan Jo Cecile Henri Theeuwen , Freerk Van Rijs , Petra Christina Anna Hammes , Ivo Bernhard Pouwel , Hendrikus Ferdinand Franciscus Jos
IPC分类号： H01L27/088 , H01L29/78
CPC分类号： H01L29/0847 , H01L29/402 , H01L29/66659 , H01L29/7835
摘要： The LDMOS transistor (99) of the invention is provided with a stepped shield structure (50) and/or with a first (25) and a second (26) drain extension region having a higher dopant concentration than the second drain extension region, and being covered by the shield.
摘要翻译：本发明的LDMOS晶体管（99）设置有阶梯式屏蔽结构（50）和/或具有比第二漏极延伸区域更高的掺杂剂浓度的第一（25）和第二（26）漏极延伸区域，以及被盾盖住。

2. 发明申请

US20080237705A1 Ldmos Transistor 审中-公开
标题翻译： Ldmos晶体管
公开(公告)号：US20080237705A1
公开(公告)日：2008-10-02
申请号：US11997209
申请日：2006-08-02
申请人： Stephan Jo Cecile Henri Theeuwen , Freerk Van Rijs , Petra C.A. Hammes
发明人： Stephan Jo Cecile Henri Theeuwen , Freerk Van Rijs , Petra C.A. Hammes
IPC分类号： H01L29/78
CPC分类号： H01L29/41758 , H01L21/76895 , H01L23/4827 , H01L23/53219 , H01L29/402 , H01L29/41725 , H01L29/4175 , H01L29/456 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： The LDMOS transistor (1) of the invention comprises a substrate (2), a gate electrode (10), a substrate contact region (11), a source region (3), a channel region (4) and a drain region (5), which drain region (5) comprises a drain contact region (6) and drain extension region (7). The drain contact region (6) is electrically connected to a top metal layer (23), which extends over the drain extension region (7), with a distance (723) between the top metal layer (23) and the drain extension region (7) that is larger than 2μm. This way the area of the drain contact region (6) may be reduced and the RF power output efficiency of the LDMOS transistor (1) increased. In another embodiment the source region (3) is electrically connected to the substrate contact region (11) via a suicide layer (32) instead of a first metal layer (21), thereby reducing the capacitive coupling between the source region (3) and the drain region (5) and hence increasing the RF power output efficiency of the LDMOS transistor (1) further.
摘要翻译：本发明的LDMOS晶体管（1）包括基板（2），栅极电极（10），基板接触区域（11），源极区域（3），沟道区域（4）和漏极区域），该漏极区（5）包括漏极接触区（6）和漏极延伸区（7）。漏极接触区域（6）电连接到在漏极延伸区域（7）上延伸的顶部金属层（23），顶部金属层（23）和漏极延伸区域（23）之间的距离（723） 7）大于2mum。这样可以减小漏极接触区域（6）的面积，并且增加LDMOS晶体管（1）的RF功率输出效率。在另一个实施例中，源极区（3）经由硅化物层（32）而不是第一金属层（21）电连接到衬底接触区（11），从而减小源区（3）和漏极区域（5），从而进一步提高LDMOS晶体管（1）的RF功率输出效率。

3. 发明授权

US07989879B2 LDMOS transistor 有权
标题翻译： LDMOS晶体管
公开(公告)号：US07989879B2
公开(公告)日：2011-08-02
申请号：US11995087
申请日：2006-07-10
申请人： Freerk Van Rijs , Stephan J. C. H. Theeuwen , Petra C. A. Hammes
发明人： Freerk Van Rijs , Stephan J. C. H. Theeuwen , Petra C. A. Hammes
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L29/402 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： The LDMOS transistor (1) of the invention comprises a source region (3), a channel region (4), a drain extension region (7) and a gate electrode (10). The LDMOS transistor (1) further comprises a first gate oxide layer (8) and a second gate oxide layer (9), which is thicker than the first gate oxide layer (8). The first gate oxide layer (8) at least extends over a first portion of the channel region (4), which is adjacent to the source region (3). The second gate oxide layer (9) extends over a region where a local maximum (A, B) of the electric field (E) generates hot carriers thereby reducing the impact of the hot carriers and reducing the Idq-degradation. In another embodiment the second gate oxide layer (9) extends over a second portion of the channel region (4), which mutually connects the drain extension region (7) and the first portion of the channel region (4), thereby improving the linear efficiency of the LDMOS transistor (1).
摘要翻译：本发明的LDMOS晶体管（1）包括源极区（3），沟道区（4），漏极延伸区（7）和栅电极（10）。 LDMOS晶体管（1）还包括比第一栅极氧化物层（8）厚的第一栅极氧化物层（8）和第二栅极氧化物层（9）。第一栅极氧化物层（8）至少延伸在与源极区域（3）相邻的沟道区域（4）的第一部分上。第二栅极氧化物层（9）在电场（E）的局部最大值（A，B））产生热载流子的区域上延伸，从而减少热载流子的影响并降低Idq降解。在另一个实施例中，第二栅极氧化物层（9）在沟道区域（4）的第二部分上延伸，沟道区域（4）相互连接漏极延伸区域（7）和沟道区域（4）的第一部分，从而改善线性 LDMOS晶体管（1）的效率。

4. 发明申请

US20110298535A1 SYSTEM AND METHOD FOR COMPENSATING FOR CHANGES IN AN OUTPUT IMPEDANCE OF A POWER AMPLIFIER 有权
标题翻译：用于补偿功率放大器的输出阻抗变化的系统和方法
公开(公告)号：US20110298535A1
公开(公告)日：2011-12-08
申请号：US12796559
申请日：2010-06-08
申请人： Freerk Van Rijs , Alexander Otto Harm
发明人： Freerk Van Rijs , Alexander Otto Harm
IPC分类号： H03F3/50
CPC分类号： H03F1/565 , H03F1/0222 , H03F1/0288 , H03F3/195 , H03F3/245 , H03F2200/102 , H03F2200/213 , H03F2200/222 , H03F2200/378 , H03F2200/387 , H03F2200/391 , H03F2200/504 , H03F2200/546 , H03F2200/75
摘要： System and method for compensating for changes in an output impedance of a power amplifier uses an impedance compensating circuit with an impedance inverter coupled to the power amplifier. The impedance inverter of the impedance compensating circuit is configured such that an output impedance of the impedance inverter is proportional to the inverse of the output impedance of the power amplifier to compensate for changes in the output impedance of the power amplifier.
摘要翻译：用于补偿功率放大器的输出阻抗的变化的系统和方法使用具有耦合到功率放大器的阻抗反相器的阻抗补偿电路。阻抗补偿电路的阻抗逆变器被配置为使得阻抗逆变器的输出阻抗与功率放大器的输出阻抗的倒数成比例，以补偿功率放大器的输出阻抗的变化。

5. 发明申请

US20070007591A1 Electric device comprising an ldmos transistor 有权
标题翻译：包括ldmos晶体管的电子装置
公开(公告)号：US20070007591A1
公开(公告)日：2007-01-11
申请号：US10569171
申请日：2004-08-24
申请人： Stephan jo Cecile Theeuwen , Freerk Van Rijs , Petra Christina Hammes , Ivo Pouwel , Henrikus Ferdinand Jos
发明人： Stephan jo Cecile Theeuwen , Freerk Van Rijs , Petra Christina Hammes , Ivo Pouwel , Henrikus Ferdinand Jos
IPC分类号： H01L29/76
CPC分类号： H01L29/0847 , H01L29/402 , H01L29/66659 , H01L29/7835
摘要： The LDMOS transistor (99) of the invention is provided with a stepped shield structure (50) and/or with a first (25) and a second (26) drain extension region having a higher dopant concentration than the second drain extension region, and being covered by the shield.
摘要翻译：本发明的LDMOS晶体管（99）设置有阶梯式屏蔽结构（50）和/或具有比第二漏极延伸区域更高的掺杂剂浓度的第一（25）和第二（26）漏极延伸区域，以及被盾盖住。

6. 发明授权

US06437420B1 Semiconductor elements for semiconductor device 失效
标题翻译：半导体元件半导体元件
公开(公告)号：US06437420B1
公开(公告)日：2002-08-20
申请号：US09613227
申请日：2000-07-10
申请人： Freerk Van Rijs , Ronald Dekker
发明人： Freerk Van Rijs , Ronald Dekker
IPC分类号： H01L27082
CPC分类号： H01L23/645 , H01L2224/02381 , H01L2224/05001 , H01L2224/05011 , H01L2224/05023 , H01L2224/05085 , H01L2224/05568 , H01L2224/16 , H01L2924/01078 , H01L2924/01079 , H01L2924/1305 , H01L2924/3011 , H01L2924/00
摘要： The invention relates to a semiconductor device (100) with a semiconductor body (10) comprising at least one semiconductor element (H) with an active area (A) and a coil (20) coupled to said element (H). The coil (20) and a further coil (21) jointly form a transformer (F). The semiconductor body (10) is secured to a carrier plate (30) which comprises an electrically insulating material and is covered with a conductor track (21). According to the invention, the further coil (21) is positioned on the carrier plate (30) and is formed by the conductor track (21) and electrically separated from the coil (20). In this way, a-device (100) is obtained which is easier to manufacture than the known device. Moreover, the communication between the element (H) and the outside world does not involve an electrical coupling and hence, for example, bonding wires, are not necessary. The invention is particularly advantageous for a (discrete) bipolar transistor, which can suitably be used for surface mounting. The invention further comprises an easy method of manufacturing a device (100) according to the invention.
摘要翻译：本发明涉及具有半导体本体（10）的半导体器件（100），该半导体本体（10）包括至少一个具有有源区（A）的半导体元件（H）和耦合到所述元件（H）的线圈（20）。线圈（20）和另外的线圈（21）共同形成变压器（F）。半导体本体（10）固定在承载板（30）上，承载板（30）包括电绝缘材料并被导体轨道（21）覆盖。根据本发明，另外的线圈（21）位于承载板（30）上并且由导体轨道（21）形成并与线圈（20）电隔离。以这种方式，获得比已知装置更容易制造的装置（100）。此外，元件（H）和外界之间的连通不涉及电耦合，因此例如不需要接合线。本发明对于可以适当地用于表面安装的（分立的）双极晶体管是特别有利的。本发明还包括一种制造根据本发明的装置（100）的简单方法。

7. 发明授权

US06410395B1 Method of manufacturing a semiconductor device comprising SiGe HBTs 失效
标题翻译：制造包含SiGe HBT的半导体器件的方法
公开(公告)号：US06410395B1
公开(公告)日：2002-06-25
申请号：US09713865
申请日：2000-11-16
申请人： Doede Terpstra , Jan Willem Slotboom , Youri Ponomarev , Petrus Hubertus Cornelis Magnee , Freerk Van Rijs
发明人： Doede Terpstra , Jan Willem Slotboom , Youri Ponomarev , Petrus Hubertus Cornelis Magnee , Freerk Van Rijs
IPC分类号： H01L21331
CPC分类号： H01L29/66242 , H01L21/82285 , H01L27/0826
摘要： A method of manufacturing a semiconductor device comprising heterojunction bipolar transistors (HBTs), in which method a first semiconductor layer of monocrystalline silicon (5), a second semiconductor layer of monocrystalline silicon comprising 5 to 25 at. % germanium (6) and a third semiconductor layer of monocrystalline silicon (7) are successively provided on a surface (2) of a silicon wafer (1) by means of epitaxial deposition. Base zones of the transistors are formed in the second semiconductor layer. In this method, the second semiconductor layer is deposited without a base doping, said doping being formed at a later stage. Said doping can be formed by means of an ion implantation process or a VPD (Vapor Phase Doping) process. This method enables integrated circuits comprising npn-transistors as well as pnp-transistors to be manufactured.
摘要翻译：一种制造包括异质结双极晶体管（HBT）的半导体器件的方法，其中单晶硅的第一半导体层（5），第二半导体单晶硅的半导体层，包括5至25μm。通过外延沉积，在硅晶片（1）的表面（2）上依次提供了锗（6）和单晶硅（7）的第三半导体层。在第二半导体层中形成晶体管的基极区。在该方法中，第二半导体层被沉积而不进行基底掺杂，所述掺杂在稍后阶段形成。所述掺杂可以通过离子注入工艺或VPD（气相掺杂）工艺形成。该方法使得能够制造包括npn晶体管的集成电路以及pnp晶体管。

8. 发明授权

US06355972B1 Semiconductor device and method of manufacturing same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06355972B1
公开(公告)日：2002-03-12
申请号：US09585826
申请日：2000-06-01
申请人： Freerk Van Rijs , Ronald Dekker , Dave Michel Henrique Hartskeerl
发明人： Freerk Van Rijs , Ronald Dekker , Dave Michel Henrique Hartskeerl
IPC分类号： H01L2970
CPC分类号： H01L29/42304 , H01L23/4824 , H01L29/41708 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a semiconductor device comprising a bipolar transistor having a collector (1), a base (2) and an emitter (3) at its active area (A). The semiconductor body (10) of the device is covered with an insulating layer (20). At least a part of a base connection conductor (5) and an emitter connection conductor (6) extend over the insulating layer (20) and lead to a base connection area (8) and an emitter connection area (9), respectively. The known transistor is characterized by poor gain, particularly at high frequencies and at high power. A device according to the invention is characterized in that the emitter connection area (8) and the base connection area (9), viewed in projection, are present on the same side of the active area (A), the emitter connection conductor (6) is divided into two or more sub-conductors (6A, 6B) and the base connection conductor (5) is divided into one or more further sub-conductors (5) which are present between the sub-conductors (6A, 6B) and form a co-planar transmission line (T) therewith. In this way, the inductance of the emitter connection conductor (6) is reduced considerably, resulting in a much higher gain, particularly at high frequencies and high power. Preferably, the semiconductor body (A) is interrupted at the area of the transmission line (T) and is glued to an insulating substrate (40).
摘要翻译：本发明涉及一种包括在其有源区（A）上具有集电极（1），基极（2）和发射极（3）的双极晶体管的半导体器件。该器件的半导体本体（10）被绝缘层（20）覆盖。基极连接导体（5）和发射极连接导体（6）的至少一部分分别延伸到绝缘层（20）上，并分别导向基极连接区域（8）和发射极连接区域（9）。已知的晶体管的特征在于增益不良，特别是在高频和高功率下。根据本发明的装置的特征在于，在投影中观察到的发射极连接区域（8）和基座连接区域（9）存在于有源区域（A）的相同侧，发射极连接导体（6））分成两个或更多个分导体（6A，6B），并且基极连接导体（5）被分成一个或多个另外的分导体（5），它们分别存在于分导体（6A，6B）和与其形成共面传输线（T）。以这种方式，发射极连接导体（6）的电感显着降低，导致高得多的增益，特别是在高频和高功率下。优选地，半导体本体（A）在传输线（T）的区域处被中断，并且被粘合到绝缘衬底（40）上。

9. 发明申请

US20090218622A1 LDMOS TRANSISTOR 有权
标题翻译： LDMOS晶体管
公开(公告)号：US20090218622A1
公开(公告)日：2009-09-03
申请号：US11995087
申请日：2006-07-10
申请人： Freerk Van Rijs , Stephan J., C., H. Theeuwen , Petra C., A. Hammes
发明人： Freerk Van Rijs , Stephan J., C., H. Theeuwen , Petra C., A. Hammes
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L29/402 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： The LDMOS transistor (1) of the invention comprises a source region (3), a channel region (4), a drain extension region (7) and a gate electrode (10). The LDMOS transistor (1) further comprises a first gate oxide layer (8) and a second gate oxide layer (9), which is thicker than the first gate oxide layer (8). The first gate oxide layer (8) at least extends over a first portion of the channel region (4), which is adjacent to the source region (3). The second gate oxide layer (9) extends over a region where a local maximum (A, B) of the electric field (E) generates hot carriers thereby reducing the impact of the hot carriers and reducing the Idq-degradation. In another embodiment the second gate oxide layer (9) extends over a second portion of the channel region (4), which mutually connects the drain extension region (7) and the first portion of the channel region (4), thereby improving the linear efficiency of the LDMOS transistor (1).
摘要翻译：本发明的LDMOS晶体管（1）包括源极区（3），沟道区（4），漏极延伸区（7）和栅电极（10）。 LDMOS晶体管（1）还包括比第一栅极氧化物层（8）厚的第一栅极氧化物层（8）和第二栅极氧化物层（9）。第一栅极氧化物层（8）至少延伸在与源极区域（3）相邻的沟道区域（4）的第一部分上。第二栅极氧化物层（9）在电场（E）的局部最大值（A，B））产生热载流子的区域上延伸，从而减少热载流子的影响并降低Idq降解。在另一个实施例中，第二栅极氧化物层（9）在沟道区域（4）的第二部分上延伸，沟道区域（4）相互连接漏极延伸区域（7）和沟道区域（4）的第一部分，从而改善线性 LDMOS晶体管（1）的效率。

10. 发明授权

US06917077B2 Protection diode for improved ruggedness of a radio frequency power transistor and self-defining method to manufacture such protection diode 有权
标题翻译：用于改善射频功率晶体管的耐用性的保护二极管和用于制造这种保护二极管的自定义方法
公开(公告)号：US06917077B2
公开(公告)日：2005-07-12
申请号：US09972576
申请日：2001-10-05
申请人： Petrus Hubertus Cornelis Magnee , Freerk Van Rijs , Hendrik Gezienus Albert Huizing
发明人： Petrus Hubertus Cornelis Magnee , Freerk Van Rijs , Hendrik Gezienus Albert Huizing
IPC分类号： H01L21/331 , H01L21/822 , H01L21/8222 , H01L27/02 , H01L27/04 , H01L27/06 , H01L29/08 , H01L29/10 , H01L29/732 , H01L29/861 , H01L31/119
CPC分类号： H01L29/66287 , H01L27/0255 , H01L29/0804 , H01L29/0821 , H01L29/8611 , Y10S438/91
摘要： A semiconductor arrangement including: a substrate having a substrate layer (13) with an upper and lower surface, the substrate layer (13) being of a first conductivity type; a first buried layer (12) in the substrate, extending along said lower surface below a first portion of said upper surface of said substrate layer (13), and a second buried layer (12) in the substrate, extending along said lower surface below a second portion of said upper surface of said substrate layer (13); a first diffusion (26) in said first portion of said substrate layer (13), being of a second conductivity type opposite to said first conductivity type and having a first distance to said first buried layer (12) for defining a first breakdown voltage between said first diffusion (26) and said first buried layer (12); a second diffusion (45) in said second portion of said substrate layer (13), being of said second conductivity type and having a second distance to said second buried layer (12) for defining a second breakdown voltage between said second diffusion (45) and said second buried layer (12); said first distance being larger than said second distance such that said first breakdown voltage is larger than said second breakdown voltage.
摘要翻译：一种半导体装置，包括：具有上表面和下表面的衬底层（13）的衬底，所述衬底层（13）是第一导电类型; 在衬底中的第一掩埋层（12），沿着所述衬底层（13）的所述上表面的第一部分下方的所述下表面延伸，以及在衬底中的第二掩埋层（12），沿着所述衬底的下表面延伸所述衬底层（13）的所述上表面的第二部分; 在所述衬底层（13）的所述第一部分中的第一扩散（26），其具有与所述第一导电类型相反的第二导电类型，并且具有到所述第一掩埋层（12）的第一距离，所述第一扩散层（26）和所述第一掩埋层（12）; 在所述衬底层（13）的所述第二部分中的第二扩散（45），具有所述第二导电类型并且具有到所述第二掩埋层（12）的第二距离，用于限定所述第二扩散（45）之间的第二击穿电压，和所述第二掩埋层（12）; 所述第一距离大于所述第二距离，使得所述第一击穿电压大于所述第二击穿电压。

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