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1. 发明申请

US20130056855A1 METHOD OF MANUFACTURING IC COMPRISING A BIPOLAR TRANSISTOR AND IC 有权
标题翻译：制造包含双极晶体管和IC的IC的方法
公开(公告)号：US20130056855A1
公开(公告)日：2013-03-07
申请号：US13599389
申请日：2012-08-30
申请人： Johannes Josephus Theodorus Marinus DONKERS , Petrus Hubertus Cornelis MAGNEE , Blandine DURIEZ , Evelyne GRIDELET , Hans MERTENS , Tony VANHOUCKE
发明人： Johannes Josephus Theodorus Marinus DONKERS , Petrus Hubertus Cornelis MAGNEE , Blandine DURIEZ , Evelyne GRIDELET , Hans MERTENS , Tony VANHOUCKE
IPC分类号： H01L29/737 , H01L21/331
CPC分类号： H01L29/7378 , H01L21/8249 , H01L27/0623 , H01L29/1004 , H01L29/161 , H01L29/165 , H01L29/456 , H01L29/66242
摘要： Disclosed is an integrated circuit and a method of manufacturing an integrated circuit comprising a bipolar transistor, the method comprising providing a substrate comprising a pair of isolation regions separated by an active region comprising a collector; forming a base layer stack over said substrate; forming a migration layer having a first migration temperature and an etch stop layer; forming a base contact layer having a second migration temperature; etching an emitter window in the base contact layer, thereby forming cavities extending from the emitter window; and exposing the resultant structure to the first migration temperature in a hydrogen atmosphere, thereby filling the cavities with the migration layer material.
摘要翻译：公开了一种集成电路和制造包括双极晶体管的集成电路的方法，所述方法包括提供包括由包括集电极的有源区域分离的一对隔离区域的衬底; 在所述衬底上形成基层堆叠; 形成具有第一迁移温度和蚀刻停止层的迁移层; 形成具有第二迁移温度的基底接触层; 蚀刻基底接触层中的发射器窗口，从而形成从发射器窗口延伸的空腔; 并在氢气氛中将所得结构暴露于第一迁移温度，由此用迁移层材料填充空腔。

2. 发明申请

US20090200641A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20090200641A1
公开(公告)日：2009-08-13
申请号：US11658228
申请日：2005-07-07
申请人： Godefridus Adrianus Maria Hurkx , Prabhat Agarwal , Abraham Rudolf Balkenende , Petrus Hubertus Cornelis Magnee , Melanie Maria Hubertina Wagemans , Erik Petrus Antonius Maria Bakkers , Erwin Hijzen
发明人： Godefridus Adrianus Maria Hurkx , Prabhat Agarwal , Abraham Rudolf Balkenende , Petrus Hubertus Cornelis Magnee , Melanie Maria Hubertina Wagemans , Erik Petrus Antonius Maria Bakkers , Erwin Hijzen
IPC分类号： H01L29/73 , H01L21/331
CPC分类号： H01L29/0804 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/0821 , H01L29/7378 , Y10S977/936
摘要： The invention relates to a semiconductor device (10) with a semiconductor body (12) comprising a bipolar transistor with an emitter region, a base region and a collector region (1, 2, 3) of, respectively, a first conductivity type, a second conductivity type opposite to the first conductivity type, and the first conductivity type. One of the emitter or collector regions (1, 3) comprises a nanowire (30). The base region (2) has been formed from a layer (20) at the surface of the semiconductor body (12); the other one (3, 1) of the emitter or collector regions (1, 3) has been formed in the semiconductor body (12) below the base region (2). The emitter or collector region (1, 3) comprising the nanowire (30) has been provided on the surface of the semiconductor body (12) such that its longitudinal axis extends perpendicularly to the surface.
摘要翻译：本发明涉及具有半导体本体（12）的半导体器件（10），该半导体器件（12）包括分别具有第一导电类型的发射极区，基极区和集电极区（1,2,3）的双极晶体管，与第一导电类型相反的第二导电类型和第一导电类型。发射极或集电极区域（1,3）中的一个包括纳米线（30）。基底区域（2）由半导体本体（12）表面的层（20）形成; 发射极或集电极区域（1,3）中的另一个（3,1）已经形成在基极区域（2）下方的半导体本体（12）中。包括纳米线（30）的发射极或集电极区域（1,3）已经设置在半导体本体（12）的表面上，使得其纵向轴线垂直于该表面延伸。

3. 发明授权

US06410395B1 Method of manufacturing a semiconductor device comprising SiGe HBTs 失效
标题翻译：制造包含SiGe HBT的半导体器件的方法
公开(公告)号：US06410395B1
公开(公告)日：2002-06-25
申请号：US09713865
申请日：2000-11-16
申请人： Doede Terpstra , Jan Willem Slotboom , Youri Ponomarev , Petrus Hubertus Cornelis Magnee , Freerk Van Rijs
发明人： Doede Terpstra , Jan Willem Slotboom , Youri Ponomarev , Petrus Hubertus Cornelis Magnee , Freerk Van Rijs
IPC分类号： H01L21331
CPC分类号： H01L29/66242 , H01L21/82285 , H01L27/0826
摘要： A method of manufacturing a semiconductor device comprising heterojunction bipolar transistors (HBTs), in which method a first semiconductor layer of monocrystalline silicon (5), a second semiconductor layer of monocrystalline silicon comprising 5 to 25 at. % germanium (6) and a third semiconductor layer of monocrystalline silicon (7) are successively provided on a surface (2) of a silicon wafer (1) by means of epitaxial deposition. Base zones of the transistors are formed in the second semiconductor layer. In this method, the second semiconductor layer is deposited without a base doping, said doping being formed at a later stage. Said doping can be formed by means of an ion implantation process or a VPD (Vapor Phase Doping) process. This method enables integrated circuits comprising npn-transistors as well as pnp-transistors to be manufactured.
摘要翻译：一种制造包括异质结双极晶体管（HBT）的半导体器件的方法，其中单晶硅的第一半导体层（5），第二半导体单晶硅的半导体层，包括5至25μm。通过外延沉积，在硅晶片（1）的表面（2）上依次提供了锗（6）和单晶硅（7）的第三半导体层。在第二半导体层中形成晶体管的基极区。在该方法中，第二半导体层被沉积而不进行基底掺杂，所述掺杂在稍后阶段形成。所述掺杂可以通过离子注入工艺或VPD（气相掺杂）工艺形成。该方法使得能够制造包括npn晶体管的集成电路以及pnp晶体管。

4. 发明授权

US08901669B2 Method of manufacturing an IC comprising a plurality of bipolar transistors and IC comprising a plurality of bipolar transistors 有权
标题翻译：制造包括多个双极晶体管的IC的方法和包括多个双极晶体管的IC
公开(公告)号：US08901669B2
公开(公告)日：2014-12-02
申请号：US13560517
申请日：2012-07-27
申请人： Hans Mertens , Johannes Theodorus Marinus Donkers , Evelyne Gridelet , Tony Vanhoucke , Petrus Hubertus Cornelis Magnee
发明人： Hans Mertens , Johannes Theodorus Marinus Donkers , Evelyne Gridelet , Tony Vanhoucke , Petrus Hubertus Cornelis Magnee
IPC分类号： H01L29/66
CPC分类号： H01L21/8222 , H01L21/82285 , H01L27/0825 , H01L27/0826
摘要： A method of manufacturing an integrated circuit comprising bipolar transistors including first and second type bipolar transistors, the method comprising providing a substrate comprising first isolation regions each separated from a second isolation region by an active region comprising a collector impurity of one of the bipolar transistors; forming a base layer stack over the substrate; forming a first emitter cap layer of a first effective thickness over the base layer stack in the areas of the first type bipolar transistor; forming a second emitter cap layer of a second effective thickness different from the first effective thickness over the base layer stack in the areas of the second type bipolar transistor; and forming an emitter over the emitter cap layer of each of the bipolar transistors. An IC in accordance with this method.
摘要翻译：一种制造集成电路的方法，包括包括第一和第二类型双极晶体管的双极晶体管，所述方法包括提供包括第一隔离区域的衬底，每个隔离区域与第二隔离区域分离，所述有源区域包括所述双极晶体管之一的集电极杂质; 在衬底上形成基层堆叠; 在所述第一类型双极晶体管的区域中在所述基极层堆叠上形成第一有效厚度的第一发射极盖层; 在所述第二类型双极晶体管的区域中形成与所述基极层叠层上的所述第一有效厚度不同的第二有效厚度的第二发射极帽层; 以及在每个双极晶体管的发射极盖层上形成发射极。根据这种方法的IC。

5. 发明授权

US08871599B2 Method of manufacturing IC comprising a bipolar transistor and IC 有权
标题翻译：制造包括双极晶体管和IC的IC的方法
公开(公告)号：US08871599B2
公开(公告)日：2014-10-28
申请号：US13599389
申请日：2012-08-30
申请人： Johannes Josephus Theodorus Marinus Donkers , Petrus Hubertus Cornelis Magnee , Blandine Duriez , Evelyne Gridelet , Hans Mertens , Tony Vanhoucke
发明人： Johannes Josephus Theodorus Marinus Donkers , Petrus Hubertus Cornelis Magnee , Blandine Duriez , Evelyne Gridelet , Hans Mertens , Tony Vanhoucke
IPC分类号： H01L21/331 , H01L21/8249 , H01L29/737
CPC分类号： H01L29/7378 , H01L21/8249 , H01L27/0623 , H01L29/1004 , H01L29/161 , H01L29/165 , H01L29/456 , H01L29/66242
摘要： Disclosed is an integrated circuit and a method of manufacturing an integrated circuit comprising a bipolar transistor, the method comprising providing a substrate comprising a pair of isolation regions separated by an active region comprising a collector; forming a base layer stack over said substrate; forming a migration layer having a first migration temperature and an etch stop layer; forming a base contact layer having a second migration temperature; etching an emitter window in the base contact layer, thereby forming cavities extending from the emitter window; and exposing the resultant structure to the first migration temperature in a hydrogen atmosphere, thereby filling the cavities with the migration layer material.
摘要翻译：公开了一种集成电路和制造包括双极晶体管的集成电路的方法，所述方法包括提供包括由包括集电极的有源区域分离的一对隔离区域的衬底; 在所述衬底上形成基层堆叠; 形成具有第一迁移温度和蚀刻停止层的迁移层; 形成具有第二迁移温度的基底接触层; 蚀刻基底接触层中的发射器窗口，从而形成从发射器窗口延伸的空腔; 并在氢气氛中将所得结构暴露于第一迁移温度，由此用迁移层材料填充空腔。

6. 发明授权

US07915709B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07915709B2
公开(公告)日：2011-03-29
申请号：US11658228
申请日：2005-07-07
申请人： Godefridus Adrianus Maria Hurkx , Prabhat Agarwal , Abraham Rudolf Balkenende , Petrus Hubertus Cornelis Magnee , Melanie Maria Hubertina Wagemans , Erik Petrus Antonius Maria Bakkers , Erwin Hijzen
发明人： Godefridus Adrianus Maria Hurkx , Prabhat Agarwal , Abraham Rudolf Balkenende , Petrus Hubertus Cornelis Magnee , Melanie Maria Hubertina Wagemans , Erik Petrus Antonius Maria Bakkers , Erwin Hijzen
IPC分类号： H01L29/66 , H01L21/8222
CPC分类号： H01L29/0804 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/0821 , H01L29/7378 , Y10S977/936
摘要： The invention relates to a semiconductor device (10) with a semiconductor body (12) comprising a bipolar transistor with an emitter region, a base region and a collector region (1, 2, 3) of, respectively, a first conductivity type, a second conductivity type opposite to the first conductivity type, and the first conductivity type. One of the emitter or collector regions (1, 3) comprises a nanowire (30). The base region (2) has been formed from a layer (20) at the surface of the semiconductor body (12); the other one (3, 1) of the emitter or collector regions (1, 3) has been formed in the semiconductor body (12) below the base region (2). The emitter or collector region (1, 3) comprising the nanowire (30) has been provided on the surface of the semiconductor body (12) such that its longitudinal axis extends perpendicularly to the surface.
摘要翻译：本发明涉及具有半导体本体（12）的半导体器件（10），该半导体器件（12）包括分别具有第一导电类型的发射极区，基极区和集电极区（1,2,3）的双极晶体管，与第一导电类型相反的第二导电类型和第一导电类型。发射极或集电极区域（1,3）中的一个包括纳米线（30）。基底区域（2）由半导体本体（12）表面的层（20）形成; 发射极或集电极区域（1,3）中的另一个（3,1）已经形成在基极区域（2）下方的半导体本体（12）中。包括纳米线（30）的发射极或集电极区域（1,3）已经设置在半导体本体（12）的表面上，使得其纵向轴线垂直于该表面延伸。

7. 发明授权

US07794540B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07794540B2
公开(公告)日：2010-09-14
申请号：US10539549
申请日：2003-12-16
申请人： Petrus Hubertus Cornelis Magnee , Johannes Josephus Theodorus Marinus Donkers , Xiaoping Shi
发明人： Petrus Hubertus Cornelis Magnee , Johannes Josephus Theodorus Marinus Donkers , Xiaoping Shi
IPC分类号： C30B25/00 , C30B28/12 , H01L21/00 , H01L27/06
CPC分类号： H01L21/02529 , H01L21/02532 , H01L21/02639 , H01L21/02642
摘要： Method of manufacturing a semiconductor device, in which on a region of silicon oxide (5) situated next to a region of monocrystalline silicon (4) at the surface (3) of a semiconductor body (1), a non-monocrystalline auxiliary layer (8) is formed. The auxiliary layer is formed in two steps. In the first step, the silicon body is heated in an atmosphere comprising a gaseous arsenic compound; in the second step it is heated in an atmosphere comprising a gaseous silicon compound instead of said arsenic compound. Thus, the regions of silicon oxide are provided with an amorphous or polycrystalline silicon seed layer in a self-aligned manner.
摘要翻译：制造半导体器件的方法，其中在位于半导体本体（1）的表面（3）的单晶硅（4）的旁边的氧化硅（5）的区域上，形成非单晶辅助层（ 8）。辅助层分两步形成。在第一步骤中，硅体在包含气态砷化合物的气氛中加热; 在第二步中，在包含气态硅化合物的气氛中代替所述砷化合物进行加热。因此，氧化硅区域以自对准的方式设置有非晶或多晶硅籽晶层。

8. 发明授权

US07566919B2 Method to reduce seedlayer topography in BICMOS process 有权
标题翻译：减少BICMOS过程中种子层形貌的方法
公开(公告)号：US07566919B2
公开(公告)日：2009-07-28
申请号：US10581639
申请日：2004-12-09
申请人： Johannes Josephus Theodorus Marinus Donkers , Petrus Hubertus Cornelis Magnee , Eddy Kunnen , Francois Igor Neuilly
发明人： Johannes Josephus Theodorus Marinus Donkers , Petrus Hubertus Cornelis Magnee , Eddy Kunnen , Francois Igor Neuilly
IPC分类号： H01L21/20
CPC分类号： H01L21/8249 , H01L29/66242 , H01L29/66272
摘要： A method for forming an epitaxial base layer in a bipolar device. The method comprises the steps of: providing a structure having a field isolation oxide region (12) adjacent to an active silicon region (10); forming a silicon nitride/silicon stack (14, 16) above the field isolation oxide region (12), wherein the silicon nitride/silicon stack (14, 16) includes a top layer of silicon (14) and a bottom layer of silicon nitride (16); performing an etch to the silicon nitride/silicon stack (14, 16) to form a stepped seed layer, wherein the top layer of silicon is etched laterally at the same time the bottom layer of silicon nitride is etched; and growing an Si/SiGe/Si stack (20) over the stepped seed layer and active region (10).
摘要翻译：一种在双极器件中形成外延基底层的方法。该方法包括以下步骤：提供具有与有源硅区域（10）相邻的场隔离氧化物区域（12）的结构; 在所述场隔离氧化物区域（12）上形成氮化硅/硅堆叠（14,16），其中所述氮化硅/硅堆叠（14,16）包括硅顶层（14）和底层氮化硅（16）; 对所述氮化硅/硅堆叠（14,16）进行蚀刻以形成阶梯式种子层，其中在蚀刻所述底层氮化硅的同时侧向蚀刻所述硅顶层; 以及在所述阶梯式种子层和有源区域（10）上生长Si / SiGe / Si堆叠（20）。

9. 发明申请

US20130087799A1 BIPOLAR TRANSISTOR MANUFACTURING METHOD, BIPOLAR TRANSISTOR AND INTEGRATED CIRCUIT 有权
标题翻译：双极晶体管制造方法，双极晶体管和集成电路
公开(公告)号：US20130087799A1
公开(公告)日：2013-04-11
申请号：US13616400
申请日：2012-09-14
申请人： Evelyne GRIDELET , Johannes Josephus Theodorus Marinus DONKERS , Tony VANHOUCKE , Petrus Hubertus Cornelis MAGNEE , Hans MERTENS , Blandine DURIEZ
发明人： Evelyne GRIDELET , Johannes Josephus Theodorus Marinus DONKERS , Tony VANHOUCKE , Petrus Hubertus Cornelis MAGNEE , Hans MERTENS , Blandine DURIEZ
IPC分类号： H01L29/739 , H01L21/331
CPC分类号： H01L29/732 , H01L29/66242 , H01L29/7378
摘要： Disclosed is a method of manufacturing a bipolar transistor, comprising providing a substrate (10) comprising a first isolation region (12) separated from a second isolation region by an active region (11) comprising a collector impurity; forming a layer stack over said substrate, said layer stack comprising a base layer (14, 14′), a silicon capping layer (15) over said base layer and a silicon-germanium (SiGe) base contact layer (40) over said silicon capping layer; etching the SiGe base contact layer to form an emitter window (50) over the collector impurity, wherein the silicon emitter cap layer is used as etch stop layer; forming sidewall spacers (22) in the emitter window; and filling the emitter window with an emitter material (24). A bipolar transistor manufactured in accordance with this method and an IC comprising one or more of such bipolar transistors are also disclosed.
摘要翻译：公开了一种制造双极晶体管的方法，包括提供包括通过包括集电极杂质的有源区（11）与第二隔离区分离的第一隔离区（12）的衬底（10）在所述衬底上形成层堆叠，所述层堆叠包括在所述基底层上方的基底层（14,14'），硅覆盖层（15）和位于所述硅上的硅 - 锗（SiGe）基底接触层（40）盖层; 蚀刻SiGe基极接触层以在集电极杂质上形成发射极窗口（50），其中硅发射极盖层用作蚀刻停止层; 在发射器窗口中形成侧壁间隔物（22）; 以及用发射体材料（24）填充发射器窗口。还公开了根据该方法制造的双极晶体管和包括一个或多个这样的双极晶体管的IC。

10. 发明授权

US06917077B2 Protection diode for improved ruggedness of a radio frequency power transistor and self-defining method to manufacture such protection diode 有权
标题翻译：用于改善射频功率晶体管的耐用性的保护二极管和用于制造这种保护二极管的自定义方法
公开(公告)号：US06917077B2
公开(公告)日：2005-07-12
申请号：US09972576
申请日：2001-10-05
申请人： Petrus Hubertus Cornelis Magnee , Freerk Van Rijs , Hendrik Gezienus Albert Huizing
发明人： Petrus Hubertus Cornelis Magnee , Freerk Van Rijs , Hendrik Gezienus Albert Huizing
IPC分类号： H01L21/331 , H01L21/822 , H01L21/8222 , H01L27/02 , H01L27/04 , H01L27/06 , H01L29/08 , H01L29/10 , H01L29/732 , H01L29/861 , H01L31/119
CPC分类号： H01L29/66287 , H01L27/0255 , H01L29/0804 , H01L29/0821 , H01L29/8611 , Y10S438/91
摘要： A semiconductor arrangement including: a substrate having a substrate layer (13) with an upper and lower surface, the substrate layer (13) being of a first conductivity type; a first buried layer (12) in the substrate, extending along said lower surface below a first portion of said upper surface of said substrate layer (13), and a second buried layer (12) in the substrate, extending along said lower surface below a second portion of said upper surface of said substrate layer (13); a first diffusion (26) in said first portion of said substrate layer (13), being of a second conductivity type opposite to said first conductivity type and having a first distance to said first buried layer (12) for defining a first breakdown voltage between said first diffusion (26) and said first buried layer (12); a second diffusion (45) in said second portion of said substrate layer (13), being of said second conductivity type and having a second distance to said second buried layer (12) for defining a second breakdown voltage between said second diffusion (45) and said second buried layer (12); said first distance being larger than said second distance such that said first breakdown voltage is larger than said second breakdown voltage.
摘要翻译：一种半导体装置，包括：具有上表面和下表面的衬底层（13）的衬底，所述衬底层（13）是第一导电类型; 在衬底中的第一掩埋层（12），沿着所述衬底层（13）的所述上表面的第一部分下方的所述下表面延伸，以及在衬底中的第二掩埋层（12），沿着所述衬底的下表面延伸所述衬底层（13）的所述上表面的第二部分; 在所述衬底层（13）的所述第一部分中的第一扩散（26），其具有与所述第一导电类型相反的第二导电类型，并且具有到所述第一掩埋层（12）的第一距离，所述第一扩散层（26）和所述第一掩埋层（12）; 在所述衬底层（13）的所述第二部分中的第二扩散（45），具有所述第二导电类型并且具有到所述第二掩埋层（12）的第二距离，用于限定所述第二扩散（45）之间的第二击穿电压，和所述第二掩埋层（12）; 所述第一距离大于所述第二距离，使得所述第一击穿电压大于所述第二击穿电压。

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