专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5918147A Process for forming a semiconductor device with an antireflective layer 失效
标题翻译：用于形成具有抗反射层的半导体器件的工艺
公开(公告)号：US5918147A
公开(公告)日：1999-06-29
申请号：US413021
申请日：1995-03-29
申请人： Stanley M. Filipiak , Ted R. White , T. P. Ong , Jung-Hui Lin , Wayne M. Paulson , Bernard J. Roman
发明人： Stanley M. Filipiak , Ted R. White , T. P. Ong , Jung-Hui Lin , Wayne M. Paulson , Bernard J. Roman
IPC分类号： G03F7/11 , H01L21/027 , H01L21/285 , H01L21/316 , H01L21/318 , H01L21/3213
CPC分类号： H01L21/28512 , H01L21/0276 , H01L21/31604 , H01L21/3185 , H01L21/32133
摘要： Antireflective layers (54, 86, and 109) have been developed that have discrete portions (541, 542, 861, 862, 863, 1091, and 1092). The discrete portions (541, 542, 861, 862, 863, 1091, and 1092) allow the antireflective layers (54, 86, and 109) to be used in many instances where using a single layer of uniform composition would be difficult or impossible. Alternatively, a single antireflective layer with a continuously graded composition can be used.
摘要翻译：已经开发了具有离散部分（541,542,861,862,863,1091和1092）的抗反射层（54,86和109）。离散部分（541,542,861,862,863,1091和1092）允许在许多情况下使用抗反射层（54,86和109），其中使用均匀组成的单层将是困难的或不可能的。或者，可以使用具有连续渐变组成的单个抗反射层。

2. 发明授权

US06686633B1 Semiconductor device, memory cell, and processes for forming them 有权
标题翻译：半导体器件，存储单元及其形成工艺
公开(公告)号：US06686633B1
公开(公告)日：2004-02-03
申请号：US09653338
申请日：2000-08-31
申请人： Craig S. Lage , Mousumi Bhat , Yeong-Jyh Tom Lii , Andrew G. Nagy , Larry E. Frisa , Stanley M. Filipiak , David L. O'Meara , T. P. Ong , Michael P. Woo , Terry G. Sparks , Carol M. Gelatos
发明人： Craig S. Lage , Mousumi Bhat , Yeong-Jyh Tom Lii , Andrew G. Nagy , Larry E. Frisa , Stanley M. Filipiak , David L. O'Meara , T. P. Ong , Michael P. Woo , Terry G. Sparks , Carol M. Gelatos
IPC分类号： H01L2976
CPC分类号： H01L27/11 , H01L21/76801 , H01L21/76832 , H01L21/76834 , H01L21/76895 , H01L21/76897 , H01L27/1104
摘要： A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (522 and 524), wherein each local interconnect (522, 524) cross couples the inverters of the SRAM and is formed within a single opening (70). Also, interconnect portions (104) of word lines are laterally offset from silicon portions (36) of the same word line, so that the interconnect portions do not interfere with bit line connections.
摘要翻译：半导体器件包括静态随机存取存储器单元的存储器阵列。使用与逻辑型器件更紧密相关联的工艺流程来形成SRAM单元。 SRAM单元使用一个半导体层形成，与至少三个SRAM单元相似。 SRAM单元包括许多特征，允许其尺寸缩放到非常小的尺寸（小于0.25微米，并且可能低至0.1微米甚至更小）。独特的过程集成方案允许形成局部互连（522和524），其中每个局部互连（522,524）交叉耦合SRAM的反相器并形成在单个开口（70）内。此外，字线的互连部分（104）横向偏离同一字线的硅部分（36），使得互连部分不干扰位线连接。

3. 发明授权

US06184073B2 Process for forming a semiconductor device having an interconnect or conductive film electrically insulated from a conductive member or region 失效
标题翻译：用于形成具有与导电部件或区域电绝缘的互连或导电膜的半导体器件的工艺
公开(公告)号：US06184073B2
公开(公告)日：2001-02-06
申请号：US08997714
申请日：1997-12-23
申请人： Craig S. Lage , Mousumi Bhat , Yeong-Jyh Tom Lii , Andrew G. Nagy , Larry E. Frisa , Stanley M. Filipiak , David L. O'Meara , T. P. Ong , Michael P. Woo , Terry G. Sparks , Carol M. Gelatos
发明人： Craig S. Lage , Mousumi Bhat , Yeong-Jyh Tom Lii , Andrew G. Nagy , Larry E. Frisa , Stanley M. Filipiak , David L. O'Meara , T. P. Ong , Michael P. Woo , Terry G. Sparks , Carol M. Gelatos
IPC分类号： H01L218234
CPC分类号： H01L27/11 , H01L21/76801 , H01L21/76832 , H01L21/76834 , H01L21/76895 , H01L21/76897 , H01L27/1104
摘要： A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (522 and 524), wherein each local interconnect (522, 524) cross couples the inverters of the SRAM and is formed within a single opening (70). Also, interconnect portions (104) of word lines are laterally offset from silicon portions (36) of the same word line, so that the interconnect portions do not interfere with bit line connections.
摘要翻译：半导体器件包括静态随机存取存储器单元的存储器阵列。使用与逻辑型器件更紧密相关联的工艺流程来形成SRAM单元。 SRAM单元使用一个半导体层形成，与至少三个SRAM单元相似。 SRAM单元包括许多特征，允许其尺寸缩放到非常小的尺寸（小于0.25微米，并且可能低至0.1微米甚至更小）。独特的过程集成方案允许形成局部互连（522和524），其中每个局部互连（522,524）交叉耦合SRAM的反相器并形成在单个开口（70）内。此外，字线的互连部分（104）横向偏离同一字线的硅部分（36），使得互连部分不干扰位线连接。

4. 发明授权

US06174810B1 Copper interconnect structure and method of formation 失效
标题翻译：铜互连结构和形成方法
公开(公告)号：US06174810B1
公开(公告)日：2001-01-16
申请号：US09055510
申请日：1998-04-06
申请人： Rabiul Islam , Avgerinos V. Gelatos , Kevin Lucas , Stanley M. Filipiak , Ramnath Venkatraman
发明人： Rabiul Islam , Avgerinos V. Gelatos , Kevin Lucas , Stanley M. Filipiak , Ramnath Venkatraman
IPC分类号： H01L2144
CPC分类号： H01L21/76808 , H01L21/76801 , H01L21/76832 , H01L21/76834 , H01L21/76838
摘要： In one embodiment, a copper interconnect structure is formed by depositing a dielectric layer (28) on a semiconductor substrate (10). The dielectric layer (28) is then patterned to form interconnect openings (29). A layer of copper (34) is then formed within the interconnect openings (29). A portion of the copper layer (34) is then removed to form copper interconnects (39) within the interconnect openings (29). A copper barrier layer (40) is then formed overlying the copper interconnects (39). Adhesion between the copper barrier layer (40) and the copper interconnects (39) is improved by exposing the exposed surface of the copper interconnects (39) to a plasma generated using only ammonia as a source gas.
摘要翻译：在一个实施例中，通过在半导体衬底（10）上沉积介电层（28）来形成铜互连结构。然后将电介质层（28）图案化以形成互连开口（29）。然后在互连开口（29）内形成一层铜（34）。然后去除铜层（34）的一部分以在互连开口（29）内形成铜互连（39）。然后在铜互连（39）上形成铜阻挡层（40）。通过将铜互连（39）的暴露表面暴露于仅使用氨作为源气体产生的等离子体，可以改善铜阻挡层（40）和铜互连（39）之间的粘合性。

5. 发明授权

US07442598B2 Method of forming an interlayer dielectric 有权
标题翻译：形成层间电介质的方法
公开(公告)号：US07442598B2
公开(公告)日：2008-10-28
申请号：US11148455
申请日：2005-06-09
申请人： Paul A. Grudowski , Stanley M. Filipiak , Yongloo Jeon , Chad E. Weintraub
发明人： Paul A. Grudowski , Stanley M. Filipiak , Yongloo Jeon , Chad E. Weintraub
IPC分类号： H01L21/8238 , H01L21/302
CPC分类号： H01L21/76834 , H01L21/31111
摘要： A method for forming a semiconductor device comprises providing a semiconductor substrate; forming a first stressor layer over a surface of the semiconductor substrate; selectively removing portions of the first stressor layer; forming a second stressor layer over the surface of the semiconductor substrate and the first stressor layer; and selectively removing portions of the second stressor layer using an isotropic etch. In one embodiment, the isotropic etch is a wet etch that selectively removes the second stressor layer without removing a significant amount of the first stressor layer and also planarizing a boundary between the first stressor layer and the second stressor layer.
摘要翻译：一种形成半导体器件的方法包括提供半导体衬底; 在所述半导体衬底的表面上形成第一应力层; 选择性地去除所述第一应激层的部分; 在所述半导体衬底和所述第一应力层的表面上形成第二应力层; 并且使用各向同性蚀刻选择性地去除第二应力层的部分。在一个实施例中，各向同性蚀刻是湿蚀刻，其在不去除大量的第一应力层的情况下选择性地去除第二应力层，并且还平面化第一应力层和第二应力层之间的边界。

6. 发明授权

US6054377A Method for forming an inlaid via in a semiconductor device 失效
标题翻译：在半导体器件中形成镶嵌通孔的方法
公开(公告)号：US6054377A
公开(公告)日：2000-04-25
申请号：US858109
申请日：1997-05-19
申请人： Stanley M. Filipiak , John C. Arnold , Phillip Crabtree
发明人： Stanley M. Filipiak , John C. Arnold , Phillip Crabtree
IPC分类号： H01L21/316 , H01L21/768 , H01L21/441
CPC分类号： H01L21/76807 , H01L21/31625 , H01L2221/1031 , H01L2221/1036
摘要： A inlaid interconnect is formed in a semiconductor device (30). A first interlayer dielectric (ILD) 40 is deposited and etched to form a via opening (44). An etchstop layer (42) is deposited on ILD (40). A second ILD (45) is deposited on etchstop layer (42) in a manner so that a pinch-off region (46) is formed to prevent substantial deposition of the ILD material into via opening (44). While a small deposit (47) of ILD material may form within the via opening, this can be easily removed in a subsequent etch of ILD (45) which forms a trench opening (48) in ILD (45). A metal layer (50) is then deposited and polished to form a metal interconnect having a trench portion (52) and a via portion (54) in device (30). The present invention avoids the need for a substantial over-etch to clear the via, and avoids the need to form a thick resist mask to form the via opening, while maintaining a controlled via diameter.
摘要翻译：嵌入的互连形成在半导体器件（30）中。沉积和蚀刻第一层间电介质（ILD）40以形成通孔（44）。蚀刻阻挡层（42）沉积在ILD（40）上。第二ILD（45）以这样的方式沉积在蚀刻阻挡层（42）上，使得形成夹断区域（46）以防止ILD材料大量沉积到通孔（44）中。虽然ILD材料的小沉积物（47）可以在通孔开口内形成，但是在ILD（45）中形成沟槽开口（48）的ILD（45）的后续蚀刻中可以容易地去除这种沉积物（47）。然后沉积和抛光金属层（50）以形成在器件（30）中具有沟槽部分（52）和通孔部分（54）的金属互连。本发明避免了实质上过度蚀刻以清除通孔的需要，并避免需要形成厚的抗蚀剂掩模以形成通路孔，同时保持受控的通孔直径。

7. 发明授权

US5447887A Method for capping copper in semiconductor devices 失效
标题翻译：在半导体器件中封装铜的方法
公开(公告)号：US5447887A
公开(公告)日：1995-09-05
申请号：US222759
申请日：1994-04-01
申请人： Stanley M. Filipiak , Avgerinos Gelatos
发明人： Stanley M. Filipiak , Avgerinos Gelatos
IPC分类号： H01L21/768 , H01L21/44 , H01L21/48
CPC分类号： H01L21/76849 , H01L21/76834 , H01L21/76867 , H01L21/76886
摘要： A silicon nitride layer (34) has improved adhesion to underlying copper interconnect members (30) through the incorporation of an intervening copper silicide layer (32). Layer (32) is formed in-situ with a plasma enhanced chemical vapor deposition (PECVD) process for depositing silicon nitride layer (34). To form layer (32), a semiconductor substrate (12) is provided having a desired copper pattern formed thereon. The copper pattern may include copper interconnects, copper plugs, or other copper members. The substrate is placed into a PECVD reaction chamber. Silane is introduced into the reaction chamber in the absence of a plasma to form a copper silicide layer on any exposed copper surfaces. After a silicide layer of a sufficient thickness (for example, 10 to 100 angstroms) is formed, PECVD silicon nitride is deposited. The copper silicide layer improves adhesion, such that silicon nitride layer is less prone to peeling away from underlying copper members.
摘要翻译：氮化硅层（34）通过引入中间铜硅化物层（32）而具有改进的对底层铜互连构件（30）的粘合性。用等离子体增强化学气相沉积（PECVD）工艺原位形成层（32），用于沉积氮化硅层（34）。为了形成层（32），提供了在其上形成有所需铜图案的半导体衬底（12）。铜图案可以包括铜互连，铜插头或其它铜构件。将基板放入PECVD反应室中。在不存在等离子体的情况下将硅烷引入反应室，以在任何暴露的铜表面上形成硅化铜层。在形成足够厚度（例如10至100埃）的硅化物层之后，沉积PECVD氮化硅。硅化铜层提高粘合性，使得氮化硅层不容易从下面的铜构件剥离。

8. 发明授权

US07763538B2 Dual plasma treatment barrier film to reduce low-k damage 有权
标题翻译：双等离子体处理屏障膜降低低k损伤
公开(公告)号：US07763538B2
公开(公告)日：2010-07-27
申请号：US11328693
申请日：2006-01-10
申请人： Michael D. Turner , Ritwik Chatterjee , Stanley M. Filipiak
发明人： Michael D. Turner , Ritwik Chatterjee , Stanley M. Filipiak
IPC分类号： H01L21/4763
CPC分类号： H01L21/02362 , H01L21/02074 , H01L21/02167 , H01L21/0217 , H01L21/0234 , H01L21/3105 , H01L21/3165 , H01L21/76826
摘要： A method is provided for creating a barrier layer (217) on a substrate comprising a dielectric layer (203) and a metal interconnect (211). In accordance with the method, the substrate is treated with a first plasma comprising helium, thereby forming a treated substrate. The treated substrate is then exposed to a second plasma selected from the group consisting of oxidizing plasmas and reducing plasmas. Next, a barrier layer is created on the treated substrate.
摘要翻译：提供了一种用于在包括电介质层（203）和金属互连（211）的衬底上产生阻挡层（217）的方法。根据该方法，用包括氦的第一等离子体处理衬底，从而形成经处理的衬底。然后将经处理的底物暴露于选自氧化等离子体和还原等离子体的第二等离子体中。接下来，在经处理的基底上产生阻挡层。

9. 发明申请

US20070298623A1 METHOD FOR STRAINING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：用于应变半导体器件的方法
公开(公告)号：US20070298623A1
公开(公告)日：2007-12-27
申请号：US11426463
申请日：2006-06-26
申请人： Gregory S. Spencer , Stanley M. Filipiak , Narayannan C. Ramani , Michael D. Turner
发明人： Gregory S. Spencer , Stanley M. Filipiak , Narayannan C. Ramani , Michael D. Turner
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/268 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A strained semiconductor layer is achieved by an overlying stressed dielectric layer. The stress in the dielectric layer is increased by a radiation anneal. The radiation anneal can be either by scanning using a laser beam or a flash tool that provides the anneal to the whole dielectric layer simultaneously. The heat is intense, preferably 900-1400 degrees Celcius, but for a very short duration of less than 10 milliseconds; preferably about 1 millisecond or even shorter. The result of the radiation anneal can also be used to activate the source/drain. Thus, this type of radiation anneal can result in a larger change in stress, activation of the source/drain, and still no expansion of the source/drain.
摘要翻译：应变半导体层通过覆盖的应力介电层实现。电介质层中的应力通过辐射退火而增加。辐射退火可以是通过使用激光束进行扫描或者同时向整个电介质层提供退火的闪光工具。热量很强，最好是900-1400摄氏度，但持续时间不到10毫秒; 优选约1毫秒甚至更短。辐射退火的结果也可用于激活源极/漏极。因此，这种类型的辐射退火可导致应力的变化较大，源极/漏极的激活以及源极/漏极的扩展。

10. 发明授权

US06218733B1 Semiconductor device having a titanium-aluminum compound 失效
标题翻译：具有钛 - 铝化合物的半导体器件
公开(公告)号：US06218733B1
公开(公告)日：2001-04-17
申请号：US08254854
申请日：1994-06-06
申请人： Robert W. Fiordalice , Stanley M. Filipiak , Johnson Olufemi Olowolafe , Hisao Kawasaki
发明人： Robert W. Fiordalice , Stanley M. Filipiak , Johnson Olufemi Olowolafe , Hisao Kawasaki
IPC分类号： H01L2348
CPC分类号： H01L21/76852 , H01L21/32051 , H01L21/321 , H01L21/76843 , H01L21/76846 , H01L21/76867 , H01L21/76886 , H01L23/53223 , H01L2924/0002 , Y10S257/915 , H01L2924/00
摘要： The present invention includes a process for forming an intermetallic layer and a device formed by the process. The process includes a reaction step where a metal-containing layer reacts with a metal-containing gas, wherein the metals of the layer and gas are different. In one embodiment of the present invention, titanium aluminide may be formed on the sides of an interconnect. The process may be performed in a variety of equipment, such as a furnace, a rapid thermal processor, a plasma etcher, and a sputter deposition machine. The reaction to form the intermetallic layer is typically performed while the substrate is at a temperature no more than 700 degrees Celsius.
摘要翻译：本发明包括形成金属间化合物的方法和通过该方法形成的装置。该方法包括其中含金属层与含金属气体反应的反应步骤，其中该层和气体的金属是不同的。在本发明的一个实施方案中，可以在互连的侧面上形成铝化铝。该方法可以在各种设备中进行，例如炉，快速热处理器，等离子体蚀刻器和溅射沉积机。形成金属间化合物的反应通常在基板处于不超过700摄氏度的温度下进行。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式