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    • 3. 发明授权
    • Deposition and densification process for titanium nitride barrier layers
    • 氮化钛阻挡层的沉积和致密化过程
    • US07838441B2
    • 2010-11-23
    • US12426815
    • 2009-04-20
    • Amit KhandelwalAvgerinos V. GelatosChristophe MarcadalMei Chang
    • Amit KhandelwalAvgerinos V. GelatosChristophe MarcadalMei Chang
    • H01L21/768
    • H01L21/28556H01L21/321H01L21/76843H01L21/76862
    • In one embodiment, a method for forming a titanium nitride barrier material on a substrate is provided which includes depositing a titanium nitride layer on the substrate by a metal-organic chemical vapor deposition (MOCVD) process, and thereafter, densifying the titanium nitride layer by exposing the substrate to a plasma process. In one example, the MOCVD process and the densifying plasma process is repeated to form a barrier stack by depositing a second titanium nitride layer on the first titanium nitride layer. In another example, a third titanium nitride layer is deposited on the second titanium nitride layer. Subsequently, the method provides depositing a conductive material on the substrate and exposing the substrate to a annealing process. In one example, each titanium nitride layer may have a thickness of about 15 Å and the titanium nitride barrier stack may have a copper diffusion potential of less than about 5×1010 atoms/cm2.
    • 在一个实施例中,提供了一种在衬底上形成氮化钛阻挡材料的方法,其包括通过金属 - 有机化学气相沉积(MOCVD)工艺在衬底上沉积氮化钛层,然后通过以下步骤致密化氮化钛层: 将衬底暴露于等离子体工艺。 在一个实例中,通过在第一氮化钛层上沉积第二氮化钛层来重复MOCVD工艺和致密等离子体工艺以形成势垒堆叠。 在另一示例中,在第二氮化钛层上沉积第三氮化钛层。 随后,该方法提供在衬底上沉积导电材料并将衬底暴露于退火过程。 在一个示例中,每个氮化钛层可以具有约15埃的厚度,氮化钛阻挡层可以具有小于约5×10 10原子/ cm 2的铜扩散电位。
    • 4. 发明授权
    • Process for forming copper interconnect structure
    • 形成铜互连结构的工艺
    • US5391517A
    • 1995-02-21
    • US120097
    • 1993-09-13
    • Avgerinos V. GelatosRobert W. Fiordalice
    • Avgerinos V. GelatosRobert W. Fiordalice
    • H01L21/3205H01L21/768H01L23/522H01L23/532H01L21/44
    • H01L23/5226H01L21/32051H01L21/76838H01L23/53238H01L2924/0002
    • A copper metallization structure and process for the formation of electrical interconnections fabricated with pure copper metal is provided. The metallization structure includes an interface layer (22) intermediate to a dielectric layer (12), and a copper interconnect (30). The interface layer (22) functions to adhere the copper interconnect (30) to a device substrate (10) and to prevent the diffusion of copper into underlying dielectric layers. The interconnect layer (22) is fabricated by depositing a first titanium layer (16) followed by the sequential deposition of a titanium nitride layer (18), and a second titanium layer (20). A copper layer (24) is deposited to overlie the second titanium layer (20) and an annealing step is carried out to form a copper-titanium intermetallic layer (26). The titanium nitride layer (18) functions as a diffusion barrier preventing the diffusion of copper into the underlying dielectric layer (12), and the copper titanium intermetallic layer (26) provides an adhesive material, which adheres the copper layer (24) to the device substrate ( 10). Following the formation of the intermetallic layer (26), the device surface is planarized to form a planar surface (28), and to form an inlaid copper interconnect (30).
    • 提供了一种用于形成用纯铜金属制造的电互连的铜金属化结构和工艺。 金属化结构包括介于介电层(12)中间的界面层(22)和铜互连(30)。 界面层(22)用于将铜互连(30)粘附到器件衬底(10)并防止铜扩散到下面的介电层中。 通过沉积第一钛层(16)然后顺序沉积氮化钛层(18)和第二钛层(20)来制造互连层(22)。 沉积铜层(24)以覆盖第二钛层(20),并执行退火步骤以形成铜 - 钛金属间层(26)。 氮化钛层(18)作为阻止铜扩散到下面的电介质层(12)中的扩散阻挡层而起作用,铜钛金属间化合物层(26)提供将铜层(24)粘合到 器件衬底(10)。 在形成金属间层(26)之后,将器件表面平坦化以形成平坦表面(28),并形成镶嵌铜互连(30)。
    • 5. 发明授权
    • Method for polish planarizing a semiconductor substrate by using a boron
nitride polish stop
    • 通过使用氮化硼抛光停止来对半导体衬底进行抛光平坦化的方法
    • US5064683A
    • 1991-11-12
    • US604855
    • 1990-10-29
    • Stephen S. PoonAvgerinos V. Gelatos
    • Stephen S. PoonAvgerinos V. Gelatos
    • H01L21/02H01L21/3105H01L21/321
    • H01L21/31053H01L21/02065H01L21/02074H01L21/3212
    • In a polish palnarization process using a polishing apparatus and an abrasive slurry, a boron nitride (BN) polish stop layer (18) is provided to increase the polish selectivity. The BN layer deposited in accordance with the invention has a hexagonal-close-pack crystal orientation and is characterized by chemical inertness and high hardness. The BN layer has a negligible polish removal rate yielding extremely high polish selectivity when used as a polish stop for polishing a number of materials commonly used in the fabrication of semiconductor devices. In accordance with the invention, a substrate (12) is provided having an uneven topography including elevated regions and recessed regions. A BN polish stop layer (18) is desposited to overlie the substrate (12) and a fill material (20, 36) which can be dielectric material or a conductive material, is deposited to overlie the BN polish stop (18) and the recessed regions of the substrate. The fill material is then polished back until the BN polish stop is reached resulting in the formation of a planar surface (38).
    • 在使用抛光装置和磨料浆料的抛光法制法中,提供了氮化硼(BN)抛光停止层(18)以提高抛光选择性。 根据本发明沉积的BN层具有六方密封组合晶体取向,其特征在于化学惰性和高硬度。 当用作抛光通常用于制造半导体器件的许多材料的抛光停止时,BN层具有可忽略的抛光除去率,产生极高的抛光选择性。 根据本发明,提供了具有包括升高区域和凹陷区域的不平坦形貌的基板(12)。 BN抛光停止层(18)被布置成覆盖在基板(12)上,并且可以沉积可以是电介质材料或导电材料的填充材料(20,36)以覆盖在BN抛光止挡(18)上并且凹陷 基底的区域。 然后将填充材料抛光回直到达到BN抛光止挡,从而形成平坦表面(38)。