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1. 发明授权

US5918147A Process for forming a semiconductor device with an antireflective layer 失效
标题翻译：用于形成具有抗反射层的半导体器件的工艺
公开(公告)号：US5918147A
公开(公告)日：1999-06-29
申请号：US413021
申请日：1995-03-29
申请人： Stanley M. Filipiak , Ted R. White , T. P. Ong , Jung-Hui Lin , Wayne M. Paulson , Bernard J. Roman
发明人： Stanley M. Filipiak , Ted R. White , T. P. Ong , Jung-Hui Lin , Wayne M. Paulson , Bernard J. Roman
IPC分类号： G03F7/11 , H01L21/027 , H01L21/285 , H01L21/316 , H01L21/318 , H01L21/3213
CPC分类号： H01L21/28512 , H01L21/0276 , H01L21/31604 , H01L21/3185 , H01L21/32133
摘要： Antireflective layers (54, 86, and 109) have been developed that have discrete portions (541, 542, 861, 862, 863, 1091, and 1092). The discrete portions (541, 542, 861, 862, 863, 1091, and 1092) allow the antireflective layers (54, 86, and 109) to be used in many instances where using a single layer of uniform composition would be difficult or impossible. Alternatively, a single antireflective layer with a continuously graded composition can be used.
摘要翻译：已经开发了具有离散部分（541,542,861,862,863,1091和1092）的抗反射层（54,86和109）。离散部分（541,542,861,862,863,1091和1092）允许在许多情况下使用抗反射层（54,86和109），其中使用均匀组成的单层将是困难的或不可能的。或者，可以使用具有连续渐变组成的单个抗反射层。

2. 发明授权

US06686633B1 Semiconductor device, memory cell, and processes for forming them 有权
标题翻译：半导体器件，存储单元及其形成工艺
公开(公告)号：US06686633B1
公开(公告)日：2004-02-03
申请号：US09653338
申请日：2000-08-31
申请人： Craig S. Lage , Mousumi Bhat , Yeong-Jyh Tom Lii , Andrew G. Nagy , Larry E. Frisa , Stanley M. Filipiak , David L. O'Meara , T. P. Ong , Michael P. Woo , Terry G. Sparks , Carol M. Gelatos
发明人： Craig S. Lage , Mousumi Bhat , Yeong-Jyh Tom Lii , Andrew G. Nagy , Larry E. Frisa , Stanley M. Filipiak , David L. O'Meara , T. P. Ong , Michael P. Woo , Terry G. Sparks , Carol M. Gelatos
IPC分类号： H01L2976
CPC分类号： H01L27/11 , H01L21/76801 , H01L21/76832 , H01L21/76834 , H01L21/76895 , H01L21/76897 , H01L27/1104
摘要： A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (522 and 524), wherein each local interconnect (522, 524) cross couples the inverters of the SRAM and is formed within a single opening (70). Also, interconnect portions (104) of word lines are laterally offset from silicon portions (36) of the same word line, so that the interconnect portions do not interfere with bit line connections.
摘要翻译：半导体器件包括静态随机存取存储器单元的存储器阵列。使用与逻辑型器件更紧密相关联的工艺流程来形成SRAM单元。 SRAM单元使用一个半导体层形成，与至少三个SRAM单元相似。 SRAM单元包括许多特征，允许其尺寸缩放到非常小的尺寸（小于0.25微米，并且可能低至0.1微米甚至更小）。独特的过程集成方案允许形成局部互连（522和524），其中每个局部互连（522,524）交叉耦合SRAM的反相器并形成在单个开口（70）内。此外，字线的互连部分（104）横向偏离同一字线的硅部分（36），使得互连部分不干扰位线连接。

3. 发明授权

US06184073B2 Process for forming a semiconductor device having an interconnect or conductive film electrically insulated from a conductive member or region 失效
标题翻译：用于形成具有与导电部件或区域电绝缘的互连或导电膜的半导体器件的工艺
公开(公告)号：US06184073B2
公开(公告)日：2001-02-06
申请号：US08997714
申请日：1997-12-23
申请人： Craig S. Lage , Mousumi Bhat , Yeong-Jyh Tom Lii , Andrew G. Nagy , Larry E. Frisa , Stanley M. Filipiak , David L. O'Meara , T. P. Ong , Michael P. Woo , Terry G. Sparks , Carol M. Gelatos
发明人： Craig S. Lage , Mousumi Bhat , Yeong-Jyh Tom Lii , Andrew G. Nagy , Larry E. Frisa , Stanley M. Filipiak , David L. O'Meara , T. P. Ong , Michael P. Woo , Terry G. Sparks , Carol M. Gelatos
IPC分类号： H01L218234
CPC分类号： H01L27/11 , H01L21/76801 , H01L21/76832 , H01L21/76834 , H01L21/76895 , H01L21/76897 , H01L27/1104
摘要： A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (522 and 524), wherein each local interconnect (522, 524) cross couples the inverters of the SRAM and is formed within a single opening (70). Also, interconnect portions (104) of word lines are laterally offset from silicon portions (36) of the same word line, so that the interconnect portions do not interfere with bit line connections.
摘要翻译：半导体器件包括静态随机存取存储器单元的存储器阵列。使用与逻辑型器件更紧密相关联的工艺流程来形成SRAM单元。 SRAM单元使用一个半导体层形成，与至少三个SRAM单元相似。 SRAM单元包括许多特征，允许其尺寸缩放到非常小的尺寸（小于0.25微米，并且可能低至0.1微米甚至更小）。独特的过程集成方案允许形成局部互连（522和524），其中每个局部互连（522,524）交叉耦合SRAM的反相器并形成在单个开口（70）内。此外，字线的互连部分（104）横向偏离同一字线的硅部分（36），使得互连部分不干扰位线连接。

4. 发明授权

US5801098A Method of decreasing resistivity in an electrically conductive layer 失效
标题翻译：降低导电层电阻率的方法
公开(公告)号：US5801098A
公开(公告)日：1998-09-01
申请号：US708245
申请日：1996-09-03
申请人： Robert Fiordalice , Sam Garcia , T. P. Ong
发明人： Robert Fiordalice , Sam Garcia , T. P. Ong
IPC分类号： H01L21/768 , H01L21/441
CPC分类号： H01L21/76838
摘要： A method of decreasing resistivity in an electrically conductive layer (23) includes providing a substrate (14), using a high density plasma sputtering technique to deposit the electrically conductive layer (23) over the substrate (14), and exposing the electrically conductive layer (23) to an anneal in an ambient comprised of a plasma (21).
摘要翻译：一种降低导电层（23）中的电阻率的方法包括：使用高密度等离子体溅射技术提供衬底（14），以将导电层（23）沉积在衬底（14）上，以及使导电层（23）在由等离子体（21）组成的环境中进行退火。

5. 发明授权

US6077768A Process for fabricating a multilevel interconnect 失效
标题翻译：制造多层互连的工艺
公开(公告)号：US6077768A
公开(公告)日：2000-06-20
申请号：US749316
申请日：1996-11-14
申请人： T. P. Ong , Robert Fiordalice , Ramnath Venkatraman
发明人： T. P. Ong , Robert Fiordalice , Ramnath Venkatraman
IPC分类号： H01L21/768 , H01L23/522 , H01L21/4763
CPC分类号： H01L21/76877 , H01L21/76879 , H01L23/5226 , H01L2924/0002
摘要： A process for fabrication of a multilevel interconnect structure includes the formation of an inlaid interconnect (42) overlying an aluminum layer (34). The inlaid interconnect (42) is formed within an interlevel dielectric layer that is processed to contain an interconnect channel (24) and a via opening (14) residing at the bottom of the interconnect channel (24). The aluminum layer (34) is selectively deposited to fill the via opening (14) at the bottom of an interconnect channel (24). Selective deposition is enhanced by the use of a nucleation layer (20) which is formed on the bottom of the via opening, without being formed on the sidewalls, by use of directional deposition technique such as inductively coupled plasma (ICP) deposition. Nucleation layer (20) eases requirements of a cleaning operation prior to selective deposition and provides a surface from which void-free selective growth can occur.
摘要翻译：制造多层互连结构的工艺包括形成覆盖铝层（34）的镶嵌互连（42）。嵌入式互连（42）形成在层间介质层内，该层间介质层被处理成包含位于互连通道（24）的底部的互连通道（24）和通孔开口（14）。选择性地沉积铝层（34）以填充互连通道（24）的底部处的通孔（14）。通过使用形成在通孔开口底部而不形成在侧壁上的成核层（20），通过使用诸如感应耦合等离子体（ICP）沉积的定向沉积技术来增强选择性沉积。成核层（20）在选择性沉积之前降低了清洁操作的要求，并且提供了可以从其出现空隙的选择性生长的表面。

6. 发明授权

US5880041A Method for forming a dielectric layer using high pressure 失效
标题翻译：使用高压形成电介质层的方法
公开(公告)号：US5880041A
公开(公告)日：1999-03-09
申请号：US249608
申请日：1994-05-27
申请人： T. P. Ong
发明人： T. P. Ong
IPC分类号： H01L21/316
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/31662
摘要： A method for forming a dielectric layer on a surface of a substrate uses high pressure. A pressure vessel of a high pressure oxidation equipment is heated to a predetermined temperature. The substrate is placed inside the pressure vessel. The pressure vessel is pressurized to a pressure above atmospheric pressure. A flow of an oxidizing gas and a flow of steam are introduced into the pressure vessel, wherein the steam flow is only a fraction of the oxidizing gas flow. The dielectric layer on the surface is formed through an oxidizing reaction of the oxidizing gas and steam with the surface of the substrate, wherein the flow of steam acts in a catalytic-like manner to parabolicly accelerate the oxidizing reaction at the surface.
摘要翻译：在基板的表面上形成电介质层的方法使用高压。将高压氧化设备的压力容器加热至预定温度。将基板放置在压力容器内。将压力容器加压至高于大气压的压力。将氧化气体流和蒸汽流引入压力容器中，其中蒸汽流仅是氧化气体流量的一部分。表面上的电介质层通过氧化气体和蒸汽与基底的表面的氧化反应形成，其中蒸汽流以催化状态起作用以抛物面地加速表面处的氧化反应。

7. 发明授权

US5783485A Process for fabricating a metallized interconnect 失效
标题翻译：用于制造金属化互连的工艺
公开(公告)号：US5783485A
公开(公告)日：1998-07-21
申请号：US684069
申请日：1996-07-19
申请人： T. P. Ong , Robert W. Fiordalice , Ramnath Venkatraman , Elizabeth J. Weitzman
发明人： T. P. Ong , Robert W. Fiordalice , Ramnath Venkatraman , Elizabeth J. Weitzman
IPC分类号： H01L21/768 , H01L23/522 , H01L21/44
CPC分类号： H01L21/76877 , H01L21/76879 , H01L23/5226 , H01L2924/0002
摘要： A process for fabrication of a metallized interconnect structure includes the formation of an inlaid interconnect (42) overlying an aluminum layer (34). The inlaid interconnect (42) is formed within an interlevel dielectric layer that is processed to contain an interconnect channel (24) and a via opening (14) residing at the bottom of the interconnect channel (24). The aluminum layer (34) is selectively deposited to at least partially fill the via opening (14) at the bottom of an interconnect channel (24). An adhesion layer (36) is deposited to overlie the aluminum layer (34) within the via opening (14), and a second aluminum layer (38) is blanket deposited and planarized to form the inlaid interconnect (42) in the interconnect channel (24).
摘要翻译：金属化互连结构的制造方法包括形成覆盖铝层（34）的镶嵌互连（42）。嵌入式互连（42）形成在层间介质层内，该层间介质层被处理成包含位于互连通道（24）的底部的互连通道（24）和通孔开口（14）。选择性地沉积铝层（34）以至少部分地填充在互连通道（24）的底部处的通孔开口（14）。沉积粘附层（36）以覆盖通孔开口（14）内的铝层（34），并且第二铝层（38）被覆盖沉积并平坦化以在互连通道（...）中形成镶嵌互连（42） 24）。

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