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1. 发明授权

US5357478A Semiconductor integrated circuit device including a plurality of cell array blocks 失效
标题翻译：包括多个单元阵列块的半导体集成电路装置
公开(公告)号：US5357478A
公开(公告)日：1994-10-18
申请号：US767332
申请日：1991-09-30
申请人： Shigeru Kikuda , Shigeru Mori , Yoshikazu Morooka , Hiroshi Miyamoto , Makoto Suwa , Mitsuya Kinoshita
发明人： Shigeru Kikuda , Shigeru Mori , Yoshikazu Morooka , Hiroshi Miyamoto , Makoto Suwa , Mitsuya Kinoshita
IPC分类号： H01L21/822 , G11C5/02 , G11C11/401 , H01L27/04 , H01L27/10 , G11C8/00
CPC分类号： G11C5/025
摘要： A plurality of sub chips are formed on a chip. An input/output buffer region is arranged around the plurality of sub chips. Each sub chip includes a sub chip control circuit region and a plurality of memory cell array blocks. Each memory cell array block includes a memory cell array region, a row decoder and control circuit region, a sense amplifier region and an input/output latch region.
摘要翻译：在芯片上形成多个子芯片。输入/输出缓冲区布置在多个子芯片周围。每个子芯片包括子芯片控制电路区域和多个存储单元阵列块。每个存储单元阵列块包括存储单元阵列区域，行解码器和控制电路区域，读出放大器区域和输入/输出锁存区域。

2. 发明授权

US5574729A Redundancy circuit for repairing defective bits in semiconductor memory device 失效
标题翻译：用于修复半导体存储器件中的有缺陷的位的冗余电路
公开(公告)号：US5574729A
公开(公告)日：1996-11-12
申请号：US338817
申请日：1994-11-10
申请人： Mitsuya Kinoshita , Shigeru Mori , Yoshikazu Morooka , Hiroshi Miyamoto , Shigeru Kikuda , Makoto Suwa
发明人： Mitsuya Kinoshita , Shigeru Mori , Yoshikazu Morooka , Hiroshi Miyamoto , Shigeru Kikuda , Makoto Suwa
IPC分类号： G11C11/401 , G11C29/00 , G11C29/04 , G06F11/00
CPC分类号： G11C29/848
摘要： A semiconductor memory device includes a plurality of memory blocks, i main row or column select lines extending over the plurality of memory blocks, and a decoder for selecting one of the main row or column select lines in accordance with an applied address signal. The decoder includes i outputs. Each of the memory blocks includes a plurality of memory cells arranged in rows and columns and at least (i+1) sub row or column select lines each for selecting one row or one column of memory cells. A shift redundancy circuit is provided for each of the memory blocks, for connecting the main row or column select line and the sub row or column select line. The shift redundancy circuit includes a switch circuit for connecting one main row or column select line to one of the plurality of adjacent sub row or column select lines, and a circuit for setting a connection path of the switch circuit. The shift redundancy circuit connects successively adjacent sub row or column select lines to main row or column select lines in one to one correspondence except a defective sub row or column select line associated with a defective bit.
摘要翻译：一种半导体存储器件包括多个存储块，i个在多个存储块上延伸的主行或列选择线，以及用于根据所施加的地址信号选择主行或列选择线中的一个的解码器。解码器包括i个输出。每个存储块包括排列成行和列的多个存储器单元和至少（i + 1）个子行或列选择线，每个用于选择一行或一列存储单元。为每个存储块提供移位冗余电路，用于连接主行或列选择线和子行或列选择线。移位冗余电路包括用于将一个主行或列选择线连接到多个相邻子行或列选择线中的一个的开关电路和用于设置开关电路的连接路径的电路。除了与有缺陷的位相关联的有缺陷的子行或列选择线之外，移位冗余电路将连续相邻的子行或列选择线以一对一的对应方式连接到主行或列选择线。

3. 发明授权

US5063313A Delay circuit employing different threshold FET's 失效
标题翻译：延迟电路使用不同的阈值FET
公开(公告)号：US5063313A
公开(公告)日：1991-11-05
申请号：US459238
申请日：1989-12-29
申请人： Shigeru Kikuda , Hiroshi Miyamoto , Michihiro Yamada
发明人： Shigeru Kikuda , Hiroshi Miyamoto , Michihiro Yamada
IPC分类号： H01L27/092 , H01L21/8238 , H03K5/00 , H03K5/04 , H03K5/13 , H03K19/0948
CPC分类号： H03K5/133 , H03K2005/00195
摘要： A delay circuit having a complementary insulated gate device comprises an inverter (10) having a series connection of a p type field effect transistor Q3 and an n type field effect transistor Q4 and a transmission gate (20) having a parallel connection of a p type field effect transistor Q1 and an n type field effect transistor Q2 connected to the preceding stage of the inverter (10), and the gates of the transistors Q1 and Q2 are connected together to an output terminal (3). The logical threshold voltage of the inverter (10) is set at a higher value in the range of the input voltage of the inverter (10). There is a peculiar period in which the transistors Q1 and Q2 of the transmission gate (20) transmit only a litle increase of the input voltage to the inverter (10) during the increase of the input voltage. Due to the existence of this peculiar period, this circuit outputs a delayed output signal only when the input voltage increases. In addition, the rise time and fall time of the output signal are short.
摘要翻译：具有互补绝缘栅极器件的延迟电路包括具有ap型场效应晶体管Q3和n型场效应晶体管Q4的串联连接的反相器（10）和具有ap型场效应的并联连接的传输门（20）晶体管Q1和连接到反相器（10）的前级的n型场效应晶体管Q2，并且晶体管Q1和Q2的栅极连接到输出端子（3）。在逆变器（10）的输入电压的范围内，将逆变器（10）的逻辑门限电压设定为较高的值。在输入电压增加期间，传输门（20）的晶体管Q1和Q2仅传输到逆变器（10）的输入电压的一个特殊周期。由于存在这个特殊周期，该电路仅在输入电压增加时输出延迟的输出信号。另外，输出信号的上升时间和下降时间短。

4. 发明授权

US4994689A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US4994689A
公开(公告)日：1991-02-19
申请号：US435860
申请日：1989-11-14
申请人： Shigeru Kikuda , Hiroshi Miyamoto
发明人： Shigeru Kikuda , Hiroshi Miyamoto
IPC分类号： H03K19/003 , G05F3/20 , G11C11/407 , G11C11/409 , H01L21/8249 , H01L27/06 , H03K17/22 , H03K17/284 , H03K19/0948
CPC分类号： H03K17/284 , G05F3/205 , H03K17/223
摘要： A potential of a semiconductor substrate is clamped to a ground potential by a V.sub.BB clamping circuit until a first time period has elapsed since turning on of a power supply. Furthermore, the operation of a main circuit is prohibited until a second time period has elapsed which is longer than the first time period, so that a rise in a substrate voltage is suppressed until the driving capability of a V.sub.BB generating circuit is fully achieved.
摘要翻译：通过VBB钳位电路将半导体衬底的电位钳位到接地电位，直到从电源接通开始经过第一时间段。此外，主电路的操作被禁止，直到经过长于第一时间段的第二时间段，从而抑制基板电压的上升，直到VBB发生电路的驱动能力完全达到。

5. 发明授权

US4931668A MIS transistor driven inverter circuit capable of individually controlling rising portion and falling portion of output waveform 失效
标题翻译：能够单独控制输出波形的上升部分和下降部分的MIS晶体管驱动的逆变器电路
公开(公告)号：US4931668A
公开(公告)日：1990-06-05
申请号：US143399
申请日：1988-01-13
申请人： Shigeru Kikuda , Michihiro Yamada , Hiroshi Miyamoto
发明人： Shigeru Kikuda , Michihiro Yamada , Hiroshi Miyamoto
IPC分类号： H03K4/94 , H03F1/52 , H03K5/01 , H03K5/12 , H03K17/04 , H03K17/08 , H03K19/003
CPC分类号： H03K5/01 , H03K19/00361
摘要： A resistor is connected to an input portion of a CMOS inverter. An input of the CMOS inverter is affected by a time constant of an RC circuit comprising the resistor and gate stray capacitance of the CMOS inverter. In addition, there is provided an n channel MOS transistor having a drain and a source connected to both ends of the resistor, respectively, and a gate connected to an input signal source. Only in the rising portion of an input signal, the n channel MOS transistor is turned on, so that the resistor is bypassed. Thus, a waveform of output of the CMOS inverter is not delayed at the falling portion. Only at the rising portion, the waveform thereof is delayed due to the time constant of the above described RC circuit.
摘要翻译：电阻器连接到CMOS反相器的输入部分。 CMOS反相器的输入受到包括CMOS反相器的电阻和栅杂散电容的RC电路的时间常数的影响。另外，提供了一个n沟道MOS晶体管，其漏极和源极分别连接到电阻器的两端，栅极连接到输入信号源。只有在输入信号的上升部分，n沟道MOS晶体管导通，使得电阻器被旁路。因此，CMOS反相器的输出波形在下降部分不延迟。仅在上升部分，由于上述RC电路的时间常数，其波形被延迟。

6. 发明授权

US5321654A Semiconductor device having no through current flow in standby period 失效
标题翻译：半导体器件在待机期间没有通过电流流动
公开(公告)号：US5321654A
公开(公告)日：1994-06-14
申请号：US863975
申请日：1992-04-06
申请人： Hiroshi Miyamoto , Yoshikazu Morooka , Shigeru Mori , Shigeru Kikuda , Makoto Suwa , Mitsuya Kinoshita
发明人： Hiroshi Miyamoto , Yoshikazu Morooka , Shigeru Mori , Shigeru Kikuda , Makoto Suwa , Mitsuya Kinoshita
IPC分类号： G11C11/408 , G11C5/14 , G11C7/22 , G11C8/18 , G11C11/401 , G11C11/409 , H01L21/822 , H01L27/04 , H01L27/10 , G11C7/00
CPC分类号： G11C7/22 , G11C5/14 , G11C8/18
摘要： A semiconductor device having amplifying circuits provided near corresponding bonding pads receiving external signals, and positioned between the bonding pads and internal circuits to which such external signals are to be applied. The device includes a control signal generating circuit for the amplifying circuits which is not provided in conventional semiconductor devices. In response to external control signals, the control signal generating circuit generates internal control signals for controlling electric paths between a power supply and ground in the amplifying circuits. During the standby period of the semiconductor device, the paths between the power supply and ground are cut regardless of the potential of the corresponding bonding pads, preventing flow of a through current.
摘要翻译：一种具有放大电路的半导体器件，该放大电路设置在相应的接合焊盘附近，接收外部信号，并且位于接合焊盘和要施加这样的外部信号的内部电路之间。该装置包括用于放大电路的控制信号发生电路，其不在常规半导体器件中提供。响应于外部控制信号，控制信号发生电路产生用于控制放大电路中的电源和接地之间的电气路径的内部控制信号。在半导体器件的待机期间，电源和接地之间的路径被切断，而不管相应的焊盘的电位如何，防止通过电流的流动。

7. 发明授权

US4879679A Dynamic random access memory having storage gate electrode grounding means 失效
标题翻译：具有存储栅电极接地装置的动态随机存取存储器
公开(公告)号：US4879679A
公开(公告)日：1989-11-07
申请号：US163017
申请日：1988-03-02
申请人： Shigeru Kikuda , Hiroshi Miyamoto
发明人： Shigeru Kikuda , Hiroshi Miyamoto
IPC分类号： G11C11/404 , G11C11/4072 , G11C11/4074 , H01L21/8242 , H01L27/08 , H01L27/10 , H01L27/108
CPC分类号： G11C11/4074 , G11C11/4072 , Y10T307/281
摘要： A dynamic RAM provided on a semiconductor substrate comprises: a memory cell including a capacitor for storing electric charges as information, the capacitor having a storage gate electrode to which a potential other than a ground potential is applied during normal operation of the dynamic RAM; a peripheral circuit including a CMOS circuit; and grounding means for applying the ground potential to the storage gate electrode only in a predetermined period immediately after a start of application of a power supply voltage to the dynamic RAM.
摘要翻译：提供在半导体衬底上的动态RAM包括：存储单元，其包括用于存储电荷作为信息的电容器，所述电容器具有在所述动态RAM的正常操作期间施加除了地电势之外的电位的存储栅电极; 包括CMOS电路的外围电路; 以及仅在开始向动态RAM施加电源电压之后的预定时间段内将接地电位施加到存储栅电极的接地装置。

8. 发明授权

US5448516A Semiconductor memory device suitable for high integration 失效
标题翻译：半导体存储器件适合高集成度
公开(公告)号：US5448516A
公开(公告)日：1995-09-05
申请号：US301753
申请日：1994-09-07
申请人： Yasuhiko Tsukikawa , Shigeru Kikuda , Hiroshi Miyamoto
发明人： Yasuhiko Tsukikawa , Shigeru Kikuda , Hiroshi Miyamoto
IPC分类号： G11C11/401 , G11C5/02 , H01L27/10 , G11C13/00
CPC分类号： G11C5/025
摘要： A chip is divided into at least four regions of two rows and two columns. In each region, memory array blocks are provided between corresponding first control circuits disposed in the column direction at a constant pitch. A column decoder is disposed adjacent to the first control circuit. Second control circuits are disposed corresponding to the first control circuits. The second control circuits excluding the second control circuit on the column decoder side are formed in the same pattern.
摘要翻译：芯片被分成至少四行和两列的区域。在每个区域中，存储器阵列块以恒定的间距设置在列方向上布置的对应的第一控制电路之间。列解码器被布置为与第一控制电路相邻。对应于第一控制电路设置第二控制电路。排列在列解码器侧的第二控制电路的第二控制电路以相同的图案形成。

9. 发明授权

US5384784A Semiconductor memory device comprising a test circuit and a method of operation thereof 失效
标题翻译：半导体存储器件，包括测试电路及其操作方法
公开(公告)号：US5384784A
公开(公告)日：1995-01-24
申请号：US750040
申请日：1991-08-27
申请人： Shigeru Mori , Makoto Suwa , Hiroshi Miyamoto , Yoshikazu Morooka , Shigeru Kikuda , Mitsuya Kinoshita
发明人： Shigeru Mori , Makoto Suwa , Hiroshi Miyamoto , Yoshikazu Morooka , Shigeru Kikuda , Mitsuya Kinoshita
IPC分类号： G11C11/409 , G11C11/401 , G11C29/00 , G11C29/34 , G06F15/20
CPC分类号： G11C29/34
摘要： A semiconductor memory device includes a memory array. The bit line pairs of the odd number order in the memory array belong to a first group, and the bit line pairs of the even number order belong to a second group. A first amplifier is connected to each bit line pair. Corresponding to the first group, write buses read buses and a read/test circuit are provided. Corresponding to the second group, write buses read buses and a read/test circuit are provided. A column decoder selects a plurality of bit line pairs simultaneously at the time of testing. At the time of testing, each of the read/test circuits compares data read out from the plurality of bit line pairs belonging to the corresponding group with a given expected data for providing the comparison result.
摘要翻译：半导体存储器件包括存储器阵列。存储器阵列中奇数次序的位线对属于第一组，偶数顺序的位线对属于第二组。第一放大器连接到每个位线对。对应于第一组，写总线读总线和读/测电路。对应于第二组，写总线读总线和读/测电路。列解码器在测试时同时选择多个位线对。在测试时，每个读/测试电路将从属于相应组的多个位线对中读出的数据与给定的预期数据进行比较，以提供比较结果。

10. 发明授权

US5586076A Semiconductor memory device permitting high speed data transfer and high density integration 失效
标题翻译：半导体存储器件允许高速数据传输和高密度集成
公开(公告)号：US5586076A
公开(公告)日：1996-12-17
申请号：US304899
申请日：1994-09-13
申请人： Hiroshi Miyamoto , Yoshikazu Morooka , Kiyohiro Furutani , Shigeru Kikuda
发明人： Hiroshi Miyamoto , Yoshikazu Morooka , Kiyohiro Furutani , Shigeru Kikuda
IPC分类号： G11C11/401 , G11C7/10 , G11C11/409 , G11C11/4096 , G11C7/00 , G11C11/24
CPC分类号： G11C11/4096 , G11C7/10
摘要： In a memory cell array, data lines are formed into a hierarchical arrangement of sub data lines provided for every block and a main data line common to each block, and a sub data line selected by a column address among sub data lines belonging a block which are simultaneously selected by a row address is connected to a bit line. Accordingly, the sub data line length is reduced, which reduces floating capacitance, reading and writing operations can be conducted at a high speed, and sub data lines can be selectively operated. In addition, power required for charging the sub data lines can be reduced, and entire power consumption by the semiconductor memory device can be reduced as well.
摘要翻译：在存储单元阵列中，数据线被形成为每个块提供的子数据线和每个块共同的主数据线的分层布置，以及由属于块的子数据线之间的列地址选择的子数据线通过行地址同时选择连接到位线。因此，减少了子数据线的长度，这降低了浮动电容，可以高速地执行读和写操作，并且可以选择性地操作子数据线。此外，可以减少对子数据线进行充电所需的功率，并且可以减小半导体存储器件的整体功耗。

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