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    • 2. 发明授权
    • Redundancy circuit for repairing defective bits in semiconductor memory
device
    • 用于修复半导体存储器件中的有缺陷的位的冗余电路
    • US5574729A
    • 1996-11-12
    • US338817
    • 1994-11-10
    • Mitsuya KinoshitaShigeru MoriYoshikazu MorookaHiroshi MiyamotoShigeru KikudaMakoto Suwa
    • Mitsuya KinoshitaShigeru MoriYoshikazu MorookaHiroshi MiyamotoShigeru KikudaMakoto Suwa
    • G11C11/401G11C29/00G11C29/04G06F11/00
    • G11C29/848
    • A semiconductor memory device includes a plurality of memory blocks, i main row or column select lines extending over the plurality of memory blocks, and a decoder for selecting one of the main row or column select lines in accordance with an applied address signal. The decoder includes i outputs. Each of the memory blocks includes a plurality of memory cells arranged in rows and columns and at least (i+1) sub row or column select lines each for selecting one row or one column of memory cells. A shift redundancy circuit is provided for each of the memory blocks, for connecting the main row or column select line and the sub row or column select line. The shift redundancy circuit includes a switch circuit for connecting one main row or column select line to one of the plurality of adjacent sub row or column select lines, and a circuit for setting a connection path of the switch circuit. The shift redundancy circuit connects successively adjacent sub row or column select lines to main row or column select lines in one to one correspondence except a defective sub row or column select line associated with a defective bit.
    • 一种半导体存储器件包括多个存储块,i个在多个存储块上延伸的主行或列选择线,以及用于根据所施加的地址信号选择主行或列选择线中的一个的解码器。 解码器包括i个输出。 每个存储块包括排列成行和列的多个存储器单元和至少(i + 1)个子行或列选择线,每个用于选择一行或一列存储单元。 为每个存储块提供移位冗余电路,用于连接主行或列选择线和子行或列选择线。 移位冗余电路包括用于将一个主行或列选择线连接到多个相邻子行或列选择线中的一个的开关电路和用于设置开关电路的连接路径的电路。 除了与有缺陷的位相关联的有缺陷的子行或列选择线之外,移位冗余电路将连续相邻的子行或列选择线以一对一的对应方式连接到主行或列选择线。
    • 3. 发明授权
    • Delay circuit employing different threshold FET's
    • 延迟电路使用不同的阈值FET
    • US5063313A
    • 1991-11-05
    • US459238
    • 1989-12-29
    • Shigeru KikudaHiroshi MiyamotoMichihiro Yamada
    • Shigeru KikudaHiroshi MiyamotoMichihiro Yamada
    • H01L27/092H01L21/8238H03K5/00H03K5/04H03K5/13H03K19/0948
    • H03K5/133H03K2005/00195
    • A delay circuit having a complementary insulated gate device comprises an inverter (10) having a series connection of a p type field effect transistor Q3 and an n type field effect transistor Q4 and a transmission gate (20) having a parallel connection of a p type field effect transistor Q1 and an n type field effect transistor Q2 connected to the preceding stage of the inverter (10), and the gates of the transistors Q1 and Q2 are connected together to an output terminal (3). The logical threshold voltage of the inverter (10) is set at a higher value in the range of the input voltage of the inverter (10). There is a peculiar period in which the transistors Q1 and Q2 of the transmission gate (20) transmit only a litle increase of the input voltage to the inverter (10) during the increase of the input voltage. Due to the existence of this peculiar period, this circuit outputs a delayed output signal only when the input voltage increases. In addition, the rise time and fall time of the output signal are short.
    • 具有互补绝缘栅极器件的延迟电路包括具有ap型场效应晶体管Q3和n型场效应晶体管Q4的串联连接的反相器(10)和具有ap型场效应的并联连接的传输门(20) 晶体管Q1和连接到反相器(10)的前级的n型场效应晶体管Q2,并且晶体管Q1和Q2的栅极连接到输出端子(3)。 在逆变器(10)的输入电压的范围内,将逆变器(10)的逻辑门限电压设定为较高的值。 在输入电压增加期间,传输门(20)的晶体管Q1和Q2仅传输到逆变器(10)的输入电压的一个特殊周期。 由于存在这个特殊周期,该电路仅在输入电压增加时输出延迟的输出信号。 另外,输出信号的上升时间和下降时间短。