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1. 发明授权

US5903575A Semiconductor memory device having fast data writing mode and method of writing testing data in fast data writing mode 失效
标题翻译：具有快速数据写入模式的半导体存储器件和以快速数据写入模式写入测试数据的方法
公开(公告)号：US5903575A
公开(公告)日：1999-05-11
申请号：US158837
申请日：1993-11-29
申请人： Shigeru Kikuda
发明人： Shigeru Kikuda
IPC分类号： G11C29/00 , G01R31/28 , G11C11/401 , G11C29/10 , G11C29/24 , G11C29/34 , H01L27/10
CPC分类号： G11C29/24
摘要： Disclosed is a semiconductor memory device including a normal memory array and preliminary memory array enabling a mutual data transfer. Word lines in the normal memory array and those in the preliminary memory array are controlled by separate row decoders and separate word drivers. Bit lines and sense amplifiers are provided commonly to the normal memory array and the preliminary memory array. When test data is written in a predetermined pattern into the normal memory array, data corresponding to the predetermined pattern is written in advance for each memory cell in the preliminary memory array. Then, after the row decoder and word driver for the preliminary memory array are enabled so that the word lines in the preliminary memory array are activated, the row decoder and word driver for the normal memory array are enabled so that the word lines in the preliminary memory array are activated. Thus, data signals read from memory cells of one row in the normal memory array are simultaneously amplified by the sense amplifiers via the bit lines and then transferred via the bit lines to memory cells of one row in the preliminary memory array. In this result, the test data are written at one time into the memory cells of one row in the normal memory array.
摘要翻译：公开了一种包括正常存储器阵列和能够进行相互数据传输的初步存储器阵列的半导体存储器件。正常存储器阵列中的字线和初步存储器阵列中的字线由单独的行解码器和单独的字驱动器控制。位线和读出放大器通常提供给正常存储器阵列和初步存储器阵列。当以预定图案将测试数据写入正常存储器阵列中时，预备存储器阵列中的每个存储单元预先写入与预定图案对应的数据。然后，在初步存储器阵列的行解码器和字驱动器被使能以使得初步存储器阵列中的字线被激活之后，启用用于正常存储器阵列的行解码器和字驱动器，使得初步存储器阵列中的字线存储器阵列被激活。因此，从正常存储器阵列中的一行的存储单元读取的数据信号经由位线被读出放大器同时放大，然后经由位线被传送到预备存储器阵列中的一行的存储单元。在该结果中，将测试数据一次写入正常存储器阵列中的一行的存储单元。

2. 发明授权

US5321654A Semiconductor device having no through current flow in standby period 失效
标题翻译：半导体器件在待机期间没有通过电流流动
公开(公告)号：US5321654A
公开(公告)日：1994-06-14
申请号：US863975
申请日：1992-04-06
申请人： Hiroshi Miyamoto , Yoshikazu Morooka , Shigeru Mori , Shigeru Kikuda , Makoto Suwa , Mitsuya Kinoshita
发明人： Hiroshi Miyamoto , Yoshikazu Morooka , Shigeru Mori , Shigeru Kikuda , Makoto Suwa , Mitsuya Kinoshita
IPC分类号： G11C11/408 , G11C5/14 , G11C7/22 , G11C8/18 , G11C11/401 , G11C11/409 , H01L21/822 , H01L27/04 , H01L27/10 , G11C7/00
CPC分类号： G11C7/22 , G11C5/14 , G11C8/18
摘要： A semiconductor device having amplifying circuits provided near corresponding bonding pads receiving external signals, and positioned between the bonding pads and internal circuits to which such external signals are to be applied. The device includes a control signal generating circuit for the amplifying circuits which is not provided in conventional semiconductor devices. In response to external control signals, the control signal generating circuit generates internal control signals for controlling electric paths between a power supply and ground in the amplifying circuits. During the standby period of the semiconductor device, the paths between the power supply and ground are cut regardless of the potential of the corresponding bonding pads, preventing flow of a through current.
摘要翻译：一种具有放大电路的半导体器件，该放大电路设置在相应的接合焊盘附近，接收外部信号，并且位于接合焊盘和要施加这样的外部信号的内部电路之间。该装置包括用于放大电路的控制信号发生电路，其不在常规半导体器件中提供。响应于外部控制信号，控制信号发生电路产生用于控制放大电路中的电源和接地之间的电气路径的内部控制信号。在半导体器件的待机期间，电源和接地之间的路径被切断，而不管相应的焊盘的电位如何，防止通过电流的流动。

3. 发明授权

US4879679A Dynamic random access memory having storage gate electrode grounding means 失效
标题翻译：具有存储栅电极接地装置的动态随机存取存储器
公开(公告)号：US4879679A
公开(公告)日：1989-11-07
申请号：US163017
申请日：1988-03-02
申请人： Shigeru Kikuda , Hiroshi Miyamoto
发明人： Shigeru Kikuda , Hiroshi Miyamoto
IPC分类号： G11C11/404 , G11C11/4072 , G11C11/4074 , H01L21/8242 , H01L27/08 , H01L27/10 , H01L27/108
CPC分类号： G11C11/4074 , G11C11/4072 , Y10T307/281
摘要： A dynamic RAM provided on a semiconductor substrate comprises: a memory cell including a capacitor for storing electric charges as information, the capacitor having a storage gate electrode to which a potential other than a ground potential is applied during normal operation of the dynamic RAM; a peripheral circuit including a CMOS circuit; and grounding means for applying the ground potential to the storage gate electrode only in a predetermined period immediately after a start of application of a power supply voltage to the dynamic RAM.
摘要翻译：提供在半导体衬底上的动态RAM包括：存储单元，其包括用于存储电荷作为信息的电容器，所述电容器具有在所述动态RAM的正常操作期间施加除了地电势之外的电位的存储栅电极; 包括CMOS电路的外围电路; 以及仅在开始向动态RAM施加电源电压之后的预定时间段内将接地电位施加到存储栅电极的接地装置。

4. 发明授权

US6166415A Semiconductor device with improved noise resistivity 失效
标题翻译：具有提高噪声电阻率的半导体器件
公开(公告)号：US6166415A
公开(公告)日：2000-12-26
申请号：US184083
申请日：1998-11-02
申请人： Kazuhiro Sakemi , Shigeru Kikuda , Satoshi Kawasaki
发明人： Kazuhiro Sakemi , Shigeru Kikuda , Satoshi Kawasaki
IPC分类号： H01L21/762 , H01L21/8234 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/76224 , H01L21/823475 , H01L21/823493
摘要： A dummy pattern that is inserted to stabilize the form of a transistor active region is implanted with an impurity of the same conductivity type as a well, and the impurity-doped region of the dummy pattern is supplied with a potential through a metal interconnection. Hence, fluctuation of a well potential due to noise hardly occurs, and a semiconductor device enduring latch up, for example, to a greater extent can be provided.
摘要翻译：插入以稳定晶体管有源区的形式的虚拟图案被注入与阱相同的导电类型的杂质，并且通过金属互连向虚设图案的杂质掺杂区域提供电位。因此，几乎不发生由于噪声引起的阱电位的波动，并且可以提供例如在更大程度上耐受闩锁的半导体器件。

5. 发明授权

US5767929A Liquid crystal display apparatus with shorting ring 失效
标题翻译：带短路环的液晶显示装置
公开(公告)号：US5767929A
公开(公告)日：1998-06-16
申请号：US674714
申请日：1996-07-02
申请人： Shigeru Yachi , Naoki Nakagawa , Shigeru Kikuda
发明人： Shigeru Yachi , Naoki Nakagawa , Shigeru Kikuda
IPC分类号： G02F1/1362 , G02F1/1333 , G02F1/1343
CPC分类号： G02F1/1362 , G02F2001/136263
摘要： A liquid crystal display apparatus comprising: gate signal lines, source signal lines, thin film transistors, terminals, an insulating film and auxiliary lines provided to surround a circumference of a displaying section, wherein source signal lines are grouped into groups; and an extended length of the source signal line in an area outside of the displaying section and a surrounding length of the auxiliary line in the area outside of the displaying section are so determined that source signal lines in a group have intersecting portions only with a specified auxiliary line.
摘要翻译：一种液晶显示装置，包括：栅极信号线，源极信号线，薄膜晶体管，端子，绝缘膜和设置成围绕显示部分的圆周的辅助线，其中源极信号线被分组成组; 并且在显示部分外部的区域中的源极信号线的延长长度和在显示部分外部的区域中辅助线的周围长度被确定为一组中的源极信号线仅具有指定的辅助线。

6. 发明授权

US5357478A Semiconductor integrated circuit device including a plurality of cell array blocks 失效
标题翻译：包括多个单元阵列块的半导体集成电路装置
公开(公告)号：US5357478A
公开(公告)日：1994-10-18
申请号：US767332
申请日：1991-09-30
申请人： Shigeru Kikuda , Shigeru Mori , Yoshikazu Morooka , Hiroshi Miyamoto , Makoto Suwa , Mitsuya Kinoshita
发明人： Shigeru Kikuda , Shigeru Mori , Yoshikazu Morooka , Hiroshi Miyamoto , Makoto Suwa , Mitsuya Kinoshita
IPC分类号： H01L21/822 , G11C5/02 , G11C11/401 , H01L27/04 , H01L27/10 , G11C8/00
CPC分类号： G11C5/025
摘要： A plurality of sub chips are formed on a chip. An input/output buffer region is arranged around the plurality of sub chips. Each sub chip includes a sub chip control circuit region and a plurality of memory cell array blocks. Each memory cell array block includes a memory cell array region, a row decoder and control circuit region, a sense amplifier region and an input/output latch region.
摘要翻译：在芯片上形成多个子芯片。输入/输出缓冲区布置在多个子芯片周围。每个子芯片包括子芯片控制电路区域和多个存储单元阵列块。每个存储单元阵列块包括存储单元阵列区域，行解码器和控制电路区域，读出放大器区域和输入/输出锁存区域。

7. 发明授权

US5146429A Semiconductor memory device including a redundancy circuitry for repairing a defective memory cell and a method for repairing a defective memory cell 失效
标题翻译：包括用于修复有缺陷的存储单元的冗余电路的半导体存储器件以及用于修复有缺陷的存储器单元的方法
公开(公告)号：US5146429A
公开(公告)日：1992-09-08
申请号：US617737
申请日：1990-11-26
申请人： Shinji Kawai , Shigeru Mori , Shigeru Kikuda
发明人： Shinji Kawai , Shigeru Mori , Shigeru Kikuda
IPC分类号： G11C11/413 , G11C29/00 , G11C29/04
CPC分类号： G11C29/848
摘要： A semicondcutor memory device includes an array of a plurality of memory cells arranged in a matrix manner, and a row or column decoder responsive to an external address signal for generating a row or column selecting signal. The memory cell array comprises (n+1) rows or columns. The row or column decoder comprises n output nodes. Transmission gates are provided between the decoder output node and row lines or column selecting lines for connecting each output node and each row line or column selecting line. The transmission gates are formed of a pair of CMOS transmission gates, whereby one output node is connected to two adjacent row lines or column selecting lines. This memory device further includes a circuit defining the connection manner of the transmission gate. This defining circuit turns one pair of CMOS transmission gates ON and OFF complementally. When there is a defective memory cell, the decoder output nodes are grouped into a first group including the output node corresponding to the faulty row or column having the defective memory cell, and a second group formed of the remaining output nodes. The defining circuit applies control signals to the CMOS transmission gates so that the ON/OFF states of the CMOS transmission gate pair related to the first group of output nodes and the CMOS transmission gate pair related to the second group of output node differ. The memory device further includes switching devices provided corresponding to each row line or column selecting line, responsive to the control signal from the defining cirucit to be turned on/off. This switching device connects only the faulty row line or the faulty column selecting line to the reference potential fixedly.
摘要翻译：半切割器存储器件包括以矩阵方式布置的多个存储器单元的阵列，以及响应于用于产生行或列选择信号的外部地址信号的行或列解码器。存储单元阵列包括（n + 1）行或列。行或列解码器包括n个输出节点。在解码器输出节点和用于连接每个输出节点和每行行或列选择线的行线或列选择线之间提供传输门。传输门由一对CMOS传输门形成，其中一个输出节点连接到两个相邻的行线或列选择线。该存储装置还包括限定传输门的连接方式的电路。该定义电路互补地将一对CMOS传输门ON和OFF。当存在有缺陷的存储器单元时，解码器输出节点被分组为包括与具有缺陷存储单元的故障行或列相对应的输出节点的第一组，以及由剩余输出节点形成的第二组。定义电路将控制信号施加到CMOS传输门，使得与第一组输出节点相关的CMOS传输门对的ON / OFF状态和与第二组输出节点相关的CMOS传输门对不同。存储器件还包括响应于来自定义电路的控制信号而被打开/关闭而对应于每行行或列选择线提供的开关装置。该开关装置仅将故障行线或故障列选择线固定为参考电位。

8. 发明授权

US06962827B1 Semiconductor device capable of shortening test time and suppressing increase in chip area, and method of manufacturing semiconductor integrated circuit device 失效
标题翻译：能够缩短测试时间并抑制芯片面积增加的半导体器件，以及半导体集成电路器件的制造方法
公开(公告)号：US06962827B1
公开(公告)日：2005-11-08
申请号：US10640322
申请日：2003-08-14
申请人： Katsuya Furue , Shigeru Kikuda , Kiyohiro Furutani , Tetsushi Tanizaki , Shigehiro Kuge , Takashi Kono
发明人： Katsuya Furue , Shigeru Kikuda , Kiyohiro Furutani , Tetsushi Tanizaki , Shigehiro Kuge , Takashi Kono
IPC分类号： G01R31/28 , G01R31/3185 , G11C29/00 , G11C29/12 , G11C29/56 , H01L21/66 , H01L23/544
CPC分类号： H01L22/34 , G11C29/006 , G11C29/12 , G11C2029/0403 , H01L2924/0002 , H01L2924/00
摘要： A plurality of semiconductor integrated circuits and a plurality of TEG circuits are aligned and provided on a substrate. In the TEG circuit, a built-in test circuit is provided in a region which faces a semiconductor integrated circuit across a dicing line region. The built-in test circuit and the semiconductor integrated circuit are connected by an interconnection which is provided on the dicing line region. The interconnection is cut for isolation into chips.
摘要翻译：多个半导体集成电路和多个TEG电路对准并设置在基板上。在TEG电路中，在穿过切割线区域的面向半导体集成电路的区域中提供内置测试电路。内置测试电路和半导体集成电路通过设置在切割线区域上的互连来连接。互连被切割以分离成芯片。

9. 发明授权

US6091651A Semiconductor memory device with improved test efficiency 失效
标题翻译：半导体存储器件具有提高的测试效率
公开(公告)号：US6091651A
公开(公告)日：2000-07-18
申请号：US165502
申请日：1998-10-02
申请人： Kiyohiro Furutani , Takeshi Hamamoto , Shigeru Kikuda
发明人： Kiyohiro Furutani , Takeshi Hamamoto , Shigeru Kikuda
IPC分类号： G01R31/28 , G11C29/02 , G11C29/34 , G11C29/50 , H01L21/8242 , H01L27/108 , G11C7/00
CPC分类号： G11C29/022 , G11C29/02 , G11C29/50
摘要： I/O lines in an I/O gate-sense amplifier portion are arranged in the order of IOA, /IOB, IOB, and /IOA. As a result, the potentials of adjacent I/O lines are necessarily different at the time of writing/reading the same data to/from a plurality of memory cells during a multi-bit test. Therefore, a short-circuit fault caused between adjacent I/O lines can be detected at the same time.
摘要翻译： I / O门检测放大器部分中的I / O线以IOA，/ IOB，IOB和/ IOA的顺序排列。结果，在多位测试期间，在从多个存储单元写入/读取相同数据时，相邻I / O线的电位必然是不同的。因此，可以同时检测相邻I / O线之间产生的短路故障。

10. 发明授权

US5448516A Semiconductor memory device suitable for high integration 失效
标题翻译：半导体存储器件适合高集成度
公开(公告)号：US5448516A
公开(公告)日：1995-09-05
申请号：US301753
申请日：1994-09-07
申请人： Yasuhiko Tsukikawa , Shigeru Kikuda , Hiroshi Miyamoto
发明人： Yasuhiko Tsukikawa , Shigeru Kikuda , Hiroshi Miyamoto
IPC分类号： G11C11/401 , G11C5/02 , H01L27/10 , G11C13/00
CPC分类号： G11C5/025
摘要： A chip is divided into at least four regions of two rows and two columns. In each region, memory array blocks are provided between corresponding first control circuits disposed in the column direction at a constant pitch. A column decoder is disposed adjacent to the first control circuit. Second control circuits are disposed corresponding to the first control circuits. The second control circuits excluding the second control circuit on the column decoder side are formed in the same pattern.
摘要翻译：芯片被分成至少四行和两列的区域。在每个区域中，存储器阵列块以恒定的间距设置在列方向上布置的对应的第一控制电路之间。列解码器被布置为与第一控制电路相邻。对应于第一控制电路设置第二控制电路。排列在列解码器侧的第二控制电路的第二控制电路以相同的图案形成。

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