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1. 发明授权

US5448516A Semiconductor memory device suitable for high integration 失效
标题翻译：半导体存储器件适合高集成度
公开(公告)号：US5448516A
公开(公告)日：1995-09-05
申请号：US301753
申请日：1994-09-07
申请人： Yasuhiko Tsukikawa , Shigeru Kikuda , Hiroshi Miyamoto
发明人： Yasuhiko Tsukikawa , Shigeru Kikuda , Hiroshi Miyamoto
IPC分类号： G11C11/401 , G11C5/02 , H01L27/10 , G11C13/00
CPC分类号： G11C5/025
摘要： A chip is divided into at least four regions of two rows and two columns. In each region, memory array blocks are provided between corresponding first control circuits disposed in the column direction at a constant pitch. A column decoder is disposed adjacent to the first control circuit. Second control circuits are disposed corresponding to the first control circuits. The second control circuits excluding the second control circuit on the column decoder side are formed in the same pattern.
摘要翻译：芯片被分成至少四行和两列的区域。在每个区域中，存储器阵列块以恒定的间距设置在列方向上布置的对应的第一控制电路之间。列解码器被布置为与第一控制电路相邻。对应于第一控制电路设置第二控制电路。排列在列解码器侧的第二控制电路的第二控制电路以相同的图案形成。

2. 发明授权

US07161387B2 Semiconductor device and level conversion circuit 失效
公开(公告)号：US07161387B2
公开(公告)日：2007-01-09
申请号：US10947257
申请日：2004-09-23
申请人： Kyoji Yamasaki , Yasuhiko Tsukikawa
发明人： Kyoji Yamasaki , Yasuhiko Tsukikawa
IPC分类号： H03K19/0175
CPC分类号： H03K3/356113 , H03K3/012 , H03K17/223
摘要： A level conversion circuit that converts a signal outputted from a second internal circuit receiving a first power supply voltage to a signal of a level of a second power supply voltage having a voltage level different than the first power supply voltage to apply its output signal to a first internal circuit, is provided with a mechanism for cutting off a path passing a through current in the level conversion circuit when the first power supply voltage is cut off.

3. 发明授权

US06903961B2 Semiconductor memory device having twin-cell units 失效
标题翻译：具有双电池单元的半导体存储器件
公开(公告)号：US06903961B2
公开(公告)日：2005-06-07
申请号：US10606240
申请日：2003-06-26
申请人： Yasuhiko Tsukikawa , Takashi Ito
发明人： Yasuhiko Tsukikawa , Takashi Ito
IPC分类号： H01L27/108 , G11C7/18 , G11C11/401 , G11C11/404 , G11C11/405 , G11C11/4097 , H01L21/8242 , H01L27/02 , G11C11/24
CPC分类号： H01L27/10882 , G11C7/18 , G11C11/405 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/10814
摘要： Each of twin-cell units each formed of two DRAM cells has a cell plate electrically isolated from the cell plates in the other twin-cell units. Thereby, voltages on two storage nodes storing mutually complementary data in the same twin-cell unit change similarly to each other owing to capacitive coupling.
摘要翻译：每个由两个DRAM单元形成的双电池单元具有与其他双电池单元中的电池板电隔离的电池板。因此，由于电容耦合，在同一双胞单元中存储互补数据的两个存储节点上的电压彼此类似地改变。

4. 发明申请

US20050088881A1 Semiconductor memory device driven with low voltage 失效
标题翻译：半导体存储器件采用低电压驱动
公开(公告)号：US20050088881A1
公开(公告)日：2005-04-28
申请号：US10972537
申请日：2004-10-26
申请人： Takeo Miki , Yasuhiko Tsukikawa , Shinji Tanaka
发明人： Takeo Miki , Yasuhiko Tsukikawa , Shinji Tanaka
IPC分类号： H01L21/8242 , G11C5/00 , G11C5/14 , G11C7/06 , G11C7/08 , G11C7/12 , G11C11/401 , G11C11/407 , G11C11/4074 , G11C11/409 , H01L27/108
CPC分类号： G11C11/4074 , G11C5/14
摘要： Independent power supply systems are provided for a peripheral circuit other than a column decoder, an array-relevant circuit, and a column decoder respectively, so that a peripheral power supply voltage, an array power supply voltage, and a column decoder power supply voltage generated independently of each other are supplied to the peripheral circuit, the array-relevant circuit, and the column decoder as an operating power supply voltage, respectively. Preferably, the column decoder power supply voltage during normal operation is set as an intermediate voltage between the peripheral power supply voltage and the array power supply voltage. Thus, an array configuration suitable for driving a transistor with a low voltage in order to achieve lower power consumption can be obtained.
摘要翻译：分别为列解码器，阵列相关电路和列解码器之外的外围电路提供独立电源系统，从而产生外围电源电压，阵列电源电压和列解码器电源电压彼此独立地分别作为工作电源电压提供给外围电路，阵列相关电路和列解码器。优选地，正常操作期间的列解码器电源电压被设置为外围电源电压和阵列电源电压之间的中间电压。因此，可以获得适于驱动具有低电压的晶体管以实现更低功耗的阵列配置。

5. 发明授权

US06687174B2 Semiconductor memory device capable of switching output data width 有权
标题翻译：能够切换输出数据宽度的半导体存储器件
公开(公告)号：US06687174B2
公开(公告)日：2004-02-03
申请号：US10336803
申请日：2003-01-06
申请人： Yukiko Maruyama , Yasuhiko Tsukikawa , Mikio Asakura , Takashi Itou
发明人： Yukiko Maruyama , Yasuhiko Tsukikawa , Mikio Asakura , Takashi Itou
IPC分类号： G11C700
CPC分类号： G11C11/4087 , G11C7/1045
摘要： In response to an output data width switching mode signal, a predecoder zone+selector zone outputs selection signals SEL0 to SEL7 and WORDA to WORDC to a preamplifier+write driver zone. The preamplifier+write driver zone can switch connection between global I/O lines GIO to GIO and a data bus in response to these selection signals. Read data is output to a pad without through a selector circuit or the like on the data bus, whereby a simple structure can be obtained with no critical adjustment of a delay time resulting from mode switching or address change.
摘要翻译：响应于输出数据宽度切换模式信号，预解码器区域+选择器区域将选择信号SEL0至SEL7和WORDA输出到WORDC到前置放大器+写入驱动器区域。前置放大器+写入驱动器区可以切换全局I / O线GIO <0>到GIO <7>之间的连接，并响应于这些选择信号切换数据总线。通过数据总线上的选择器电路等将读取数据输出到焊盘，由此可以在不进行由模式切换或地址变更引起的延迟时间的临界调整的情况下获得简单的结构。

6. 发明授权

US06535412B1 Semiconductor memory device capable of switching output data width 失效
公开(公告)号：US06535412B1
公开(公告)日：2003-03-18
申请号：US09557866
申请日：2000-04-24
申请人： Yukiko Maruyama , Yasuhiko Tsukikawa , Mikio Asakura , Takashi Itou
发明人： Yukiko Maruyama , Yasuhiko Tsukikawa , Mikio Asakura , Takashi Itou
IPC分类号： G11C700
CPC分类号： G11C11/4087 , G11C7/1045
摘要： In response to an output data width switching mode signal, a predecoder zone+selector zone outputs selection signals SEL0 to SEL7 and WORDA to WORDC to a preamplifier+write driver zone. The preamplifier+write driver zone can switch connection between global I/O lines GIO to GIO and a data bus in response to these selection signals. Read data is output to a pad without through a selector circuit or the like on the data bus, whereby a simple structure can be obtained with no critical adjustment of a delay time resulting from mode switching or address change.

7. 发明授权

US5619457A Dynamic semiconductor memory device that can control through current of input buffer circuit for external input/output control signal 失效
标题翻译：动态半导体存储器件可以通过输入缓冲电路的电流来控制外部输入/输出控制信号
公开(公告)号：US5619457A
公开(公告)日：1997-04-08
申请号：US589687
申请日：1996-01-22
申请人： Goro Hayakawa , Yasuhiko Tsukikawa
发明人： Goro Hayakawa , Yasuhiko Tsukikawa
IPC分类号： G11C11/403 , G11C7/22 , G11C11/406 , G11C11/34
CPC分类号： G11C7/22 , G11C11/406
摘要： A first logic gate circuit receives an internal row strobe signal, an internal column strobe signal and a self refresh mode for providing an operation state detection signal. The operation state detection signal attains an H level when in a stand-by state and a self refresh state. A second CMOS logic gate circuit is closed when the operation state detection signal attains an H level. Therefore, an external input/output control signal is not transmitted to the internal circuit, and a through current does not flow in the CMOS logic gate independent of the level of the external input/output control signal.
摘要翻译：第一逻辑门电路接收内部行选通信号，内部列选通信号和用于提供操作状态检测信号的自刷新模式。当处于待机状态和自刷新状态时，操作状态检测信号达到H电平。当操作状态检测信号达到H电平时，第二CMOS逻辑门电路闭合。因此，外部输入/输出控制信号不会发送到内部电路，并且直流电流不会流入CMOS逻辑门，而与外部输入/输出控制信号的电平无关。

8. 发明申请

US20070103197A1 Semiconductor device and level conversion circuit 失效
标题翻译：半导体器件和电平转换电路
公开(公告)号：US20070103197A1
公开(公告)日：2007-05-10
申请号：US11642726
申请日：2006-12-21
申请人： Kyoji Yamasaki , Yasuhiko Tsukikawa
发明人： Kyoji Yamasaki , Yasuhiko Tsukikawa
IPC分类号： H03K19/0175
CPC分类号： H03K3/356113 , H03K3/012 , H03K17/223
摘要： A level conversion circuit that converts a signal outputted from a second internal circuit receiving a first power supply voltage to a signal of a level of a second power supply voltage having a voltage level different than the first power supply voltage to apply its output signal to a first internal circuit, is provided with a mechanism for cutting off a path passing a through current in the level conversion circuit when the first power supply voltage is cut off.
摘要翻译：电平转换电路，将从接收第一电源电压的第二内部电路输出的信号转换为具有与第一电源电压不同的电压电平的第二电源电压的电平的信号，以将其输出信号施加到第一内部电路设置有用于在第一电源电压被切断时切断通过电平转换电路中的通过电流的路径的机构。

9. 发明申请

US20050219893A1 Semiconductor memory device having dummy word line 失效
标题翻译：具有虚拟字线的半导体存储器件
公开(公告)号：US20050219893A1
公开(公告)日：2005-10-06
申请号：US11131384
申请日：2005-05-18
申请人： Yasuhiko Tsukikawa , Takashi Ito
发明人： Yasuhiko Tsukikawa , Takashi Ito
IPC分类号： H01L27/108 , G11C7/18 , G11C11/401 , G11C11/404 , G11C11/405 , G11C11/4097 , H01L21/8242 , H01L27/02 , G11C11/24
CPC分类号： H01L27/10882 , G11C7/18 , G11C11/405 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/10814
摘要： Each cell unit has a cell plate electrically isolated from the cell plates in the other cell units.
摘要翻译：每个电池单元具有与其它电池单元中的电池板电隔离的电池板。

10. 发明授权

US06934204B2 Semiconductor device with reduced terminal input capacitance 失效
标题翻译：半导体器件具有降低的端子输入电容
公开(公告)号：US06934204B2
公开(公告)日：2005-08-23
申请号：US10140196
申请日：2002-05-08
申请人： Takashi Itou , Yasuhiko Tsukikawa
发明人： Takashi Itou , Yasuhiko Tsukikawa
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3185 , G11C7/00 , G11C11/401 , G11C29/00 , G11C29/14 , H04L1/22
CPC分类号： G01R31/31701 , G11C29/1201 , G11C29/46
摘要： A P-channel MOS transistor is provided between a terminal and an SVIH detection circuit for performing test mode detection. The P-channel MOS transistor is rendered non-conductive when a potential supplied to the terminal that is used commonly for signal input during the test setting and the normal operation is a power-supply potential EXTVDD or below. The SVIH detection circuit detects that a test mode is to be set when the potential at the terminal becomes higher than a prescribed potential. During the normal operation, the terminal is disconnected from the SVIH detection circuit so that the input capacitance of the terminal can be made to be about the same as that of another input terminal, and a high speed operation becomes possible. Moreover, there is no need to take into account the parasitic capacitance of an interconnection line leading to the SVIH detection circuit.
摘要翻译：在端子和SVIH检测电路之间提供P沟道MOS晶体管，用于执行测试模式检测。当在测试设置和正常操作期间通常用于信号输入的端子提供的电位是电源电位EXTVDD或更低时，P沟道MOS晶体管变得不导通。 SVIH检测电路检测到当端子电位变得高于规定电位时，要设置测试模式。在正常工作期间，端子与SVIH检测电路断开，使得端子的输入电容可以与其他输入端子的输入电容大致相同，并且可以进行高速运转。此外，不需要考虑通向SVIH检测电路的互连线的寄生电容。

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