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1. 发明授权

US08675422B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08675422B2
公开(公告)日：2014-03-18
申请号：US13204276
申请日：2011-08-05
申请人： Kiyohiro Furutani , Yoshinori Matsui
发明人： Kiyohiro Furutani , Yoshinori Matsui
IPC分类号： G11C7/06
CPC分类号： G11C11/4074 , G11C5/147
摘要： A semiconductor device includes an internal circuit and an internal voltage generation circuit which generates an internal voltage stabilized with respect to a variation of the power supply voltage supplied from the outside and supplies the internal voltage to the internal circuit. The internal voltage generation circuit performs control so that when the power supply voltage rises to exceed a predetermined value, an operation of stabilizing the internal voltage is stopped to cause the internal voltage to increase with the rise of the power supply voltage.
摘要翻译：半导体器件包括内部电路和内部电压产生电路，其产生相对于从外部提供的电源电压的变化而稳定的内部电压并将内部电压提供给内部电路。内部电压产生电路执行控制，使得当电源电压上升到超过预定值时，停止内部电压稳定的操作，以使内部电压随着电源电压的上升而增加。

2. 发明授权

US08462560B2 Semiconductor device, method for controlling the same, and semiconductor system 有权
标题翻译：半导体装置及其控制方法以及半导体系统
公开(公告)号：US08462560B2
公开(公告)日：2013-06-11
申请号：US12697728
申请日：2010-02-01
申请人： Kiyohiro Furutani , Seiji Narui
发明人： Kiyohiro Furutani , Seiji Narui
IPC分类号： G11C7/10 , G11C7/00 , G11C8/00 , G11C7/04
CPC分类号： G11C11/40626 , G11C8/06 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40615 , G11C2211/4061 , G11C2211/4067
摘要： The semiconductor device includes a temperature sensor controlled so that temperature measurement is made once at each of a plurality of different reference temperatures at an interval of a preset number of times of refresh operations and a plurality of latch circuits holding the results of temperature measurement. A refresh period is set from outputs of the latch circuits inclusive of the result of temperature measurement carried out last time for each of a plurality of different reference temperatures. After start of measurement, temperature measurements are repeated every wait time corresponding to circulation of the refresh operations. The refresh period is set such that the high-temperature side results of temperature measurement are prioritized (FIG. 2).
摘要翻译：该半导体装置包括温度传感器，该温度传感器被控制成使得以预定次数的刷新操作的间隔和保持温度测量结果的多个锁存电路在多个不同参考温度中的每一个进行一次温度测量。包括针对多个不同参考温度中的每一个的上次执行的温度测量结果的锁存电路的输出设置刷新周期。在测量开始之后，对应于刷新操作的循环的每个等待时间重复温度测量。刷新周期被设定为使得温度测量的高温侧结果被优先化（图2）。

3. 发明申请

US20120275256A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120275256A1
公开(公告)日：2012-11-01
申请号：US13455668
申请日：2012-04-25
申请人： Kiyohiro FURUTANI , Takuya KADOWAKI
发明人： Kiyohiro FURUTANI , Takuya KADOWAKI
IPC分类号： G11C7/06
CPC分类号： G11C7/08 , G11C7/222 , G11C11/40618 , G11C11/4074 , G11C11/4076 , G11C11/4091
摘要： A device may include, but is not limited to, a bit line; a power line supplied with a power voltage; a sense amplifier circuit amplifying a voltage of the bit line by using the power voltage of the power line; and a control circuit configured to respond to an active command and supply, as the power voltage, the power line with a first voltage during a first period and a second voltage lower than the first voltage during a second period. The control circuit is further configured to respond to a refresh command and supply, as the power voltage, the power line with the second voltage during both the first and second periods.
摘要翻译：设备可以包括但不限于位线; 提供电源电压的电力线; 读出放大器电路，通过使用电力线的电源电压来放大位线的电压; 以及控制电路，被配置为响应于有效命令，并且在第一时段期间以第一电压提供电力线，并在第二时段期间提供低于第一电压的第二电压。控制电路还被配置为响应刷新命令并在第一和第二周期期间提供具有第二电压的电力线作为电源电压。

4. 发明授权

US07885132B2 Semiconductor memory device enhancing reliability in data reading 有权
标题翻译：半导体存储器件提高了数据读取的可靠性
公开(公告)号：US07885132B2
公开(公告)日：2011-02-08
申请号：US12437021
申请日：2009-05-07
申请人： Takashi Kubo , Takashi Itoh , Yasuhiro Kashiwazaki , Taku Ogura , Kiyohiro Furutani
发明人： Takashi Kubo , Takashi Itoh , Yasuhiro Kashiwazaki , Taku Ogura , Kiyohiro Furutani
IPC分类号： G11C7/04
CPC分类号： G11C11/5642 , G11C5/145 , G11C7/06 , G11C7/12 , G11C16/24 , G11C16/26 , G11C16/30 , G11C2207/065 , G11C2207/2227 , G11C2211/5634 , G11C2211/5645
摘要： An internal voltage generating circuit generates and supplies a boosted voltage higher than an internal power supply voltage, as an operating power supply voltage, to a sense amplifier in a read circuit for reading data of a memory cell. A bit line precharge current supplied via an internal data line is produced from the internal power supply voltage. It is possible to provide a nonvolatile semiconductor memory device, which can perform a precise sense operation and an accurate reading of data even under a low power supply voltage condition.
摘要翻译：内部电压产生电路产生并提供高于作为工作电源电压的内部电源电压的升压电压到用于读取存储器单元的数据的读取电路中的读出放大器。从内部电源电压产生经由内部数据线提供的位线预充电电流。可以提供一种非易失性半导体存储器件，即使在低电源电压条件下也能进行精确的读出操作和数据的精确读取。

5. 发明申请

US20100253317A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100253317A1
公开(公告)日：2010-10-07
申请号：US12753582
申请日：2010-04-02
申请人： Shinya OKUNO , Kiyohiro FURUTANI
发明人： Shinya OKUNO , Kiyohiro FURUTANI
IPC分类号： G05F3/16 , H01L27/06
CPC分类号： G11C8/10 , G11C5/144 , G11C5/145
摘要： To include a first X decoder constituted by a transistor whose off-leakage current has a first temperature characteristic, a pre-decoder circuit and a peripheral circuit constituted by a transistor whose off-leakage current has a second temperature characteristic, a power supply control circuit that inactivates the X decoder when a temperature exceeds a first threshold during a standby state, and a power supply control circuit that inactivates the pre-decoder and the peripheral circuit when a temperature exceeds a second threshold during the standby state. According to the present invention, whether power supply control is performed on a plurality of circuit blocks is determined based on different temperatures, therefore optimum power supply control can be performed on each of circuit blocks.
摘要翻译：为了包括由漏电流具有第一温度特性的晶体管构成的第一X解码器，由解除漏电流具有第二温度特性的晶体管构成的预解码器电路和外围电路，电源控制电路在待机状态期间当温度超过第一阈值时使X解码器失活;以及电源控制电路，其在待机状态期间当温度超过第二阈值时使预解码器和外围电路失活。根据本发明，基于不同的温度来确定是否对多个电路块执行电源控制，因此可以对每个电路块执行最佳的电源控制。

6. 发明申请

US20100191987A1 Semiconductor device using plural external voltage and data processing system including the same 审中-公开
标题翻译：使用多个外部电压的半导体器件和包括其的数据处理系统
公开(公告)号：US20100191987A1
公开(公告)日：2010-07-29
申请号：US12656402
申请日：2010-01-28
申请人： Kiyohiro Furutani , Shoji Kaneko
发明人： Kiyohiro Furutani , Shoji Kaneko
IPC分类号： G06F1/26 , H02J1/00
CPC分类号： G11C11/4074 , G11C5/147 , H02J1/00 , Y10T307/696 , Y10T307/707
摘要： To provide a first internal voltage generating circuit that generates an internal voltage based on a first external voltage and a second internal voltage generating circuit that generates the internal voltage based on a second external voltage. The semiconductor device generates an internal voltage from a plurality of the first and second external voltages. These external voltages can be utilized efficiently depending on a load state. Therefore, even in a semiconductor device with greatly varying consumption power, it is not necessary to enlarge only a particular power supply device.
摘要翻译：提供基于第一外部电压产生内部电压的第一内部电压产生电路和基于第二外部电压产生内部电压的第二内部电压产生电路。半导体器件从多个第一和第二外部电压产生内部电压。可以根据负载状态有效地利用这些外部电压。因此，即使在具有大大变化的消耗功率的半导体器件中，也不需要仅放大特定的电源装置。

7. 发明申请

US20100181839A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20100181839A1
公开(公告)日：2010-07-22
申请号：US12656011
申请日：2010-01-13
申请人： Kenji Takahashi , Kiyohiro Furutani
发明人： Kenji Takahashi , Kiyohiro Furutani
IPC分类号： H02J1/00
CPC分类号： H03K5/133 , G06F1/3203 , G06F1/3287 , H03K19/0013 , H03K19/0016 , Y02D10/171 , Y10T307/696
摘要： A semiconductor device includes two functional circuits, PMOS transistors and NMOS transistors. The PMOS transistors control whether or not a power supply potential is to be delivered to functional circuits, and the NMOS transistors control whether or not a power supply potential GND is to be delivered to the functional circuits. An external terminal supplied with a third power supply potential and another external terminal is supplied with a fourth power supply potential higher than the third power supply potential. A power supply control circuit delivers a control signal, having the fourth power supply potential as amplitude, to transistors to control the electrically conducting state or the electrically non-conducting state of transistors. The power supply control circuit also delivers a control signal, having the third power supply potential as amplitude, to transistors to control the electrically conducting or non-conducting state of the NMOS transistors.
摘要翻译：半导体器件包括两个功能电路，PMOS晶体管和NMOS晶体管。 PMOS晶体管控制是否将电源电势输送到功能电路，并且NMOS晶体管控制是否将电源电位GND传送到功能电路。提供有第三电源电位的外部端子和另一个外部端子被提供有高于第三电源电位的第四电源电位。电源控制电路将具有第四电源电位作为振幅的控制信号传送到晶体管，以控制晶体管的导电状态或非导通状态。电源控制电路还将具有作为振幅的第三电源电位的控制信号传送到晶体管以控制NMOS晶体管的导电或非导通状态。

8. 发明授权

US06717887B1 Semiconductor memory device having configuration for selecting desired delay locked loop clock 有权
标题翻译：具有用于选择期望的延迟锁定环时钟的配置的半导体存储器件
公开(公告)号：US06717887B1
公开(公告)日：2004-04-06
申请号：US10438928
申请日：2003-05-16
申请人： Takashi Kono , Kiyohiro Furutani
发明人： Takashi Kono , Kiyohiro Furutani
IPC分类号： G11C800
CPC分类号： H03L7/0805 , G11C7/22 , G11C7/222 , H03L7/0812
摘要： A frequency divider divides a frequency of a DLL clock CLK_P into two, to generate ZCLK_PD0 and ZCLK_PD1. A delay circuit generates ZCLK_PDD0, ZCLK_PDD1 obtained by delaying ZCLK_PD0, ZCLK_PD1 respectively by Tc (=a backward amount of CLK_P with respect to an external clock+a delay amount of an internal clock with respect to the external clock). A frequency division select instruction circuit generates ZSEL0, ZSEL1 based on an internal clock CLK, and ZCLK_PDD0, PDD1. A ZSEL0 shifter circuit generates ZSEL1_D2 including a clock pulse of ZSEL1. A ZCLK_P #2 select circuit selects a clock pulse of ZCLK_PD0 using ZSEL1_D2.
摘要翻译：分频器将DLL时钟CLK_P的频率分成两个，以产生ZCLK_PD0和ZCLK_PD1。延迟电路通过将ZCLK_PD0，ZCLK_PD1分别延迟Tc（=相对于外部时钟的相对于外部时钟的内部时钟的延迟量的相对于外部时钟的反向量）而获得的ZCLK_PDD0，ZCLK_PDD1）。分频选择指令电路基于内部时钟CLK和ZCLK_PDD0，PDD1生成ZSEL0，ZSEL1。 ZSEL0移位器电路产生包含ZSEL1的时钟脉冲的ZSEL1_D2。 ZCLK_P＃2选择电路使用ZSEL1_D2选择ZCLK_PD0的时钟脉冲。

9. 发明授权

US06552939B1 Semiconductor memory device having disturb test circuit 失效
标题翻译：具有干扰测试电路的半导体存储器件
公开(公告)号：US06552939B1
公开(公告)日：2003-04-22
申请号：US09976116
申请日：2001-10-15
申请人： Takeo Miki , Kiyohiro Furutani
发明人： Takeo Miki , Kiyohiro Furutani
IPC分类号： G11C2900
CPC分类号： G11C29/50016 , G11C11/401 , G11C29/50
摘要： In a semiconductor memory device having normal circuit blocks (NBL) and a redundant circuit block (RBL) for replacement, a test mode setting unit (14, 19) sets a spare non-selection mode (TMSPROFF) and enables to restore an original address of a normal circuit (DE) in a state before executing a replacement to thereby implement a disturb test even after the replacement.
摘要翻译：在具有正常电路块（NBL）和用于替换的冗余电路块（RBL）的半导体存储器件中，测试模式设置单元（14,19）设置备用非选择模式（TMSPROFF）并使能够恢复原始地址在执行替换之前的状态下的正常电路（DE），从而即使在更换之后也执行干扰测试。

10. 发明授权

US06542422B1 Semiconductor memory device performing high speed coincidence comparison operation with defective memory cell address 失效
标题翻译：半导体存储器件执行具有缺陷存储单元地址的高速一致比较操作
公开(公告)号：US06542422B1
公开(公告)日：2003-04-01
申请号：US10246455
申请日：2002-09-19
申请人： Kiyohiro Furutani , Takeshi Hamamoto , Takashi Kubo
发明人： Kiyohiro Furutani , Takeshi Hamamoto , Takashi Kubo
IPC分类号： G11C700
CPC分类号： G11C29/842 , G11C7/1051 , G11C11/4087 , G11C2207/107
摘要： When an inputted column address CA and a defect address are compared with each other, an preset defect address and a defect conversion address obtained by inverse conversion of the defect address are both inputted to a comparison circuit. In the comparison circuit, coincidence determination operations are performed being switched between when address conversion is applied to the column address CA and when no address conversion is applied thereto, thereby coincidence comparison can be effected without using the column address CA after an address conversion operation; therefore, a delay in a determination operation accompanying a conversion operation is canceled to perform high speed data reading.
摘要翻译：当将输入的列地址CA和缺陷地址相互比较时，通过对缺陷地址进行逆转换而获得的预设缺陷地址和缺陷转换地址都被输入到比较电路。在比较电路中，在将地址转换应用于列地址CA之间进行切换时，并且当不对其进行地址转换时进行重合确定操作，从而可以在地址转换操作之后不使用列地址CA来实现一致比较; 因此，取消伴随转换操作的确定操作的延迟以执行高速数据读取。

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