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1. 发明授权

US5609511A Polishing method 失效
标题翻译：抛光方法
公开(公告)号：US5609511A
公开(公告)日：1997-03-11
申请号：US421247
申请日：1995-04-13
申请人： Shigeo Moriyama , Yoshio Kawamura , Yoshio Homma , Kikuo Kusukawa , Takeshi Furusawa
发明人： Shigeo Moriyama , Yoshio Kawamura , Yoshio Homma , Kikuo Kusukawa , Takeshi Furusawa
IPC分类号： B23Q17/24 , B24B49/04 , B24B49/12 , B24D7/12 , H01L21/304 , B24B49/00 , B24B51/00
CPC分类号： B24B37/013 , B24B49/12 , B24D7/12
摘要： Disclosed is a method of polishing a thin film layer to be polished, which is formed on the surface of a substrate, by pressing the substrate on the surface of a polishing pad and relatively moving the substrate and the polishing pad, the method comprising the steps of: detecting the position of a front surface of the thin film layer to be polished using a first sensor and also detecting the position of a bottom surface of the thin film layer using a second sensor, on the way of the polishing; calculating the residual thickness of the thin film layer on the basis of the detected positions of the front and bottom surfaces of the thin film layer; and controlling the processing condition of the subsequent polishing on the basis of the calculated residual thickness of the thin film layer.
摘要翻译：本发明公开了一种通过将基板压在抛光垫的表面上并使基板和抛光垫相对移动而形成在基板表面上的抛光薄膜层的方法，该方法包括步骤使用第一传感器检测待研磨的薄膜层的前表面的位置，并且在抛光的同时使用第二传感器检测薄膜层的底面的位置; 基于检测到的薄膜层的前表面和底表面的位置计算薄膜层的剩余厚度; 并根据计算出的薄膜层的残留厚度来控制后续研磨的处理条件。

2. 发明申请

US20130221505A1 PRINTED WIRING BOARD 有权
标题翻译：印刷线路板
公开(公告)号：US20130221505A1
公开(公告)日：2013-08-29
申请号：US13598751
申请日：2012-08-30
申请人： Toshiki FURUTANI , Takeshi Furusawa
发明人： Toshiki FURUTANI , Takeshi Furusawa
IPC分类号： H01L23/495
CPC分类号： H01L23/49541 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L2224/16225 , H01L2924/15311 , H01L2924/3511
摘要： A printed wiring board includes a substrate, a first buildup formed on a first surface of the substrate and including the outermost conductive layer, and a second buildup layer formed on a second surface of the substrate and including the outermost conductive layer. The outermost layer of the first buildup has pads positioned to connect a semiconductor component, the first buildup has a component mounting region directly under the component such that the outermost layer of the first buildup has a portion in the region, the outermost layer of the second buildup has a portion directly under the region, and the portions satisfy the ratio in the range of from 1.1 to 1.35, where the ratio is obtained by dividing a planar area of the portion of the second buildup by a planar area of the portion of the first buildup.
摘要翻译：印刷布线板包括基板，形成在基板的第一表面上并且包括最外面的导电层的第一累积物和形成在基板的第二表面上并且包括最外面导电层的第二累积层。第一堆积的最外层具有定位成连接半导体部件的焊盘，第一堆积具有直接在部件下方的部件安装区域，使得第一堆积物的最外层具有该区域中的一部分，第二部分的最外层积聚部分具有直接在该区域下方的部分，并且这些部分满足在1.1至1.35范围内的比率，其中通过将第二聚集部分的平面面积除以该部分的平面面积获得的比例第一次积累

3. 发明授权

US07605448B2 Semiconductor device with seal ring 有权
标题翻译：半导体器件带密封圈
公开(公告)号：US07605448B2
公开(公告)日：2009-10-20
申请号：US11220603
申请日：2005-09-08
申请人： Takeshi Furusawa , Noriko Miura , Kinya Goto , Masazumi Matsuura
发明人： Takeshi Furusawa , Noriko Miura , Kinya Goto , Masazumi Matsuura
IPC分类号： H01L21/56
CPC分类号： H01L23/585 , H01L23/3192 , H01L23/53295 , H01L23/564 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device according to the invention is a semiconductor device which includes a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls in closed loop form in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.
摘要翻译：根据本发明的半导体器件是一种半导体器件，其包括相对介电常数小于3.5的低介电常数膜，在平面图中设置有一个或多个密闭环，其为闭环形式的防潮壁并且其中至少一个所述密封环包括在芯片角附近以向内突出形式的密封环突出部分。

4. 发明授权

US06903445B2 Semiconductor device having low-K insulating film 有权
标题翻译：具有低K绝缘膜的半导体器件
公开(公告)号：US06903445B2
公开(公告)日：2005-06-07
申请号：US10896885
申请日：2004-07-23
申请人： Daisuke Ryuzaki , Takeshi Furusawa
发明人： Daisuke Ryuzaki , Takeshi Furusawa
IPC分类号： H01L23/522 , H01L21/312 , H01L21/316 , H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/52 , H01L29/40 , H01L31/0328
CPC分类号： H01L21/76826 , C23C16/0272 , C23C16/401 , H01L21/02126 , H01L21/02131 , H01L21/022 , H01L21/02216 , H01L21/02282 , H01L21/02321 , H01L21/0234 , H01L21/02362 , H01L21/312 , H01L21/3122 , H01L21/3143 , H01L21/3148 , H01L21/31629 , H01L21/31633 , H01L21/3185 , H01L21/76801 , H01L21/76807 , H01L21/76819 , H01L21/76822 , H01L21/76829 , H01L21/76832 , H01L21/76835 , H01L21/7684
摘要： Disclosed is a semiconductor device having a dielectric film of a stacked structure, comprising a low dielectric constant film containing silicon, oxygen and carbon a modified layer for the low dielectric constant film containing silicon, oxygen, carbon and fluorine and a dielectric protection film formed successively on a semiconductor substrate, the semiconductor device being manufactured by applying a plasma treatment using a fluorine-containing gas to the surface of an organic siloxane film to form a modified layer and then forming a dielectric protection film, which can improve the adhesivity with the dielectric protection film without increasing the dielectric constant of the organic siloxane film to prevent delamination.
摘要翻译：公开了具有叠层结构的电介质膜的半导体器件，包括含有硅，氧和碳的低介电常数膜，用于含有硅，氧，碳和氟的低介电常数膜的改性层和相继形成的介电保护膜在半导体衬底上，半导体器件是通过使用含氟气体的等离子体处理施加到有机硅氧烷膜的表面上以形成改性层，然后形成电介质保护膜来制造的，这可以改善与电介质的粘附性保护膜不增加有机硅氧烷膜的介电常数，防止分层。

5. 发明授权

US06599830B2 Semiconductor device and manufacturing method thereof 有权
公开(公告)号：US06599830B2
公开(公告)日：2003-07-29
申请号：US10187998
申请日：2002-07-03
申请人： Takeshi Furusawa , Takao Kumihashi , Shuntaro Machida
发明人： Takeshi Furusawa , Takao Kumihashi , Shuntaro Machida
IPC分类号： H01L214763
CPC分类号： H01L21/76832 , H01L21/02126 , H01L21/02282 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/3122 , H01L21/76802 , H01L21/76807 , H01L21/7681 , H01L21/76811 , H01L21/76813 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： To provide a method for manufacturing a semiconductor device, by which it is possible to form a trench or a hole with high aspect ratio on a methylsiloxane type film with low dielectric constant with causing neither via-connection failure nor short-circuit failure even when lower level interconnect is covered with etching stopper. The method comprises the processes of forming a layered film with a silicon oxide film on upper layer of a methylsiloxane type film and forming the layered film using a hard mask. When the etching stopper is etched, the silicon oxide film acts as a hard mask for the methylsiloxane type film, and transfer of faceting to the methylsiloxane type film is prevented. Thus, parasitic capacitance of multi-level interconnect can be reduced without causing via-connection failure and short failure.

6. 发明授权

US08513808B2 Semiconductor device having trench-isolated element formation region 有权
标题翻译：具有沟槽隔离元件形成区域的半导体器件
公开(公告)号：US08513808B2
公开(公告)日：2013-08-20
申请号：US13095735
申请日：2011-04-27
申请人： Katsuhiko Hotta , Takeshi Furusawa , Toshikazu Matsui , Takuro Homma
发明人： Katsuhiko Hotta , Takeshi Furusawa , Toshikazu Matsui , Takuro Homma
IPC分类号： H01L23/522 , H01L21/768 , H01L23/525
CPC分类号： H01L24/03 , H01L23/522 , H01L23/53223 , H01L23/585 , H01L24/05 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05093 , H01L2224/05096 , H01L2224/05166 , H01L2224/05187 , H01L2224/05554 , H01L2224/05567 , H01L2224/05571 , H01L2224/05624 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01021 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/04941 , H01L2924/1306 , H01L2924/14 , H01L2924/04953 , H01L2924/00014 , H01L2924/00 , H01L2224/05552
摘要： Provided is a technique capable of improving the reliability of a semiconductor device having a slit made over a main surface of a semiconductor substrate, so as to surround each element formation region. In the technique, a second passivation film covers the side surface of an opening made to make the upper surface of a sixth-layer interconnection M6 used for bonding pads naked, and the inner walls (the side surfaces and the bottom surface) of a slit made to surround the circumference of a guard ring and made in a first passivation film, an insulating film for bonding, and an interlayer dielectric, so as to cause the bottom thereof not to penetrate through a barrier insulating film.
摘要翻译：提供了一种能够提高半导体器件的半导体器件的可靠性的技术，该半导体器件具有在半导体衬底的主表面上形成的狭缝，以便围绕每个元件形成区域。在该技术中，第二钝化膜覆盖开口的侧表面，使得用于接合焊盘的第六层互连M6的上表面裸露，狭缝的内壁（侧表面和底表面）围绕保护环的周围并制成第一钝化膜，用于接合的绝缘膜和层间电介质，以使其底部不穿透阻挡绝缘膜。

7. 发明授权

US08365402B2 Method for manufacturing printed wiring board 有权
标题翻译：印刷电路板制造方法
公开(公告)号：US08365402B2
公开(公告)日：2013-02-05
申请号：US12533454
申请日：2009-07-31
申请人： Toshiki Furutani , Takeshi Furusawa
发明人： Toshiki Furutani , Takeshi Furusawa
IPC分类号： H01K3/10
CPC分类号： H05K1/113 , H01L21/486 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/15311 , H05K1/0269 , H05K3/0035 , H05K3/107 , H05K3/205 , H05K3/421 , H05K3/423 , H05K3/428 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0542 , H05K2203/166 , H05K2203/167 , Y10T29/49117 , Y10T29/49124 , Y10T29/49155 , Y10T29/49165 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A method for manufacturing a printed wiring board, in which filled vias with a reduction in faulty connections are formed, and providing such a printed wiring board. After an electroless plated film is formed on an inner wall of a via opening, electrolytic plating is performed on insulative resin base material; the via opening is filled with plating metal and a filled via is formed. Therefore, during electrolytic plating, a plating metal is deposited from electroless plated film on the side wall of the via opening as well as from the bottom of the via opening. As a result, the via opening may be completely filled through electrolytic plating, forming a filled via with a reduction in faulty connections.
摘要翻译：一种制造印刷线路板的方法，其中形成了具有减少连接故障的填充过孔，并且提供了这种印刷线路板。在通孔开口的内壁上形成无电镀膜后，对绝缘性树脂基材进行电解电镀; 通孔开口填充有电镀金属，并形成填充的通孔。因此，在电解电镀期间，电化学金属由通孔开口的侧壁以及通孔开口的底部的无电镀膜沉积。结果，通孔开口可以通过电解电镀完全填充，形成填充的通孔，同时减少连接错误。

8. 发明授权

US07816268B2 Semiconductor device and manufacturing method of semiconductor device 有权
公开(公告)号：US07816268B2
公开(公告)日：2010-10-19
申请号：US12714039
申请日：2010-02-26
申请人： Takeshi Furusawa , Daisuke Kodama , Masahiro Matsumoto , Hiroshi Miyazaki
发明人： Takeshi Furusawa , Daisuke Kodama , Masahiro Matsumoto , Hiroshi Miyazaki
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/76805 , H01L21/76844 , H01L21/76877 , H01L21/76886 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： To provide a semiconductor device having a structure in which a barrier metal film containing nitrogen is formed in a connection surface between a copper alloy wiring and a via, in which the electric resistance between the copper alloy wiring and the via can be prevented from rising, and the electric resistance can be prevented from varying. A semiconductor device according to the present invention comprises a first copper alloy wiring, a via and a first barrier metal film. The first copper alloy wiring is formed in an interlayer insulation film and contains a predetermined additive element in a main component Cu. The via is formed in an interlayer insulation film and electrically connected to the upper surface of the first copper alloy wiring. The first barrier metal film is formed so as to be in contact with the first copper alloy wiring in the connection part between the first copper alloy wiring and the via and contains nitrogen. The predetermined additive element reacts with nitrogen to form a high-resistance part. In addition, the concentration of the predetermined additive element is not more than 0.04 wt %.

9. 发明申请

US20100078213A1 METHOD FOR MANUFACTURING PRINTED WIRING BOARD AND PRINTED WIRING BOARD 有权
标题翻译：制造印刷电路板和印刷电路板的方法
公开(公告)号：US20100078213A1
公开(公告)日：2010-04-01
申请号：US12533454
申请日：2009-07-31
申请人： Toshiki FURUTANI , Takeshi Furusawa
发明人： Toshiki FURUTANI , Takeshi Furusawa
IPC分类号： H05K1/11 , H05K3/46 , C23F1/02 , C25D5/02
CPC分类号： H05K1/113 , H01L21/486 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/15311 , H05K1/0269 , H05K3/0035 , H05K3/107 , H05K3/205 , H05K3/421 , H05K3/423 , H05K3/428 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0542 , H05K2203/166 , H05K2203/167 , Y10T29/49117 , Y10T29/49124 , Y10T29/49155 , Y10T29/49165 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A method for manufacturing a printed wiring board, in which filled vias with a reduction in faulty connections are formed, and providing such a printed wiring board. After an electroless plated film is formed on an inner wall of a via opening, electrolytic plating is performed on insulative resin base material; the via opening is filled with plating metal and a filled via is formed. Therefore, during electrolytic plating, a plating metal is deposited from electroless plated film on the side wall of the via opening as well as from the bottom of the via opening. As a result, the via opening may be completely filled through electrolytic plating, forming a filled via with a reduction in faulty connections.
摘要翻译：一种制造印刷线路板的方法，其中形成了具有减少连接故障的填充过孔，并且提供了这种印刷线路板。在通孔开口的内壁上形成无电镀膜后，对绝缘性树脂基材进行电解电镀; 通孔开口填充有电镀金属，并形成填充的通孔。因此，在电解电镀期间，电化学金属由通孔开口的侧壁以及通孔开口的底部的无电镀膜沉积。结果，通孔开口可以通过电解电镀完全填充，形成填充的通孔，同时减少连接错误。

10. 发明申请

US20090184424A1 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090184424A1
公开(公告)日：2009-07-23
申请号：US12350268
申请日：2009-01-08
申请人： Takeshi Furusawa , Takao Kamoshima , Masatsugu Amishiro
发明人： Takeshi Furusawa , Takao Kamoshima , Masatsugu Amishiro
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/535 , H01L22/32 , H01L23/522 , H01L23/562 , H01L23/585 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/48 , H01L2224/02126 , H01L2224/02166 , H01L2224/0392 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05095 , H01L2224/05166 , H01L2224/05187 , H01L2224/05548 , H01L2224/05553 , H01L2224/05624 , H01L2224/05647 , H01L2224/45015 , H01L2224/48463 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/20753 , H01L2924/30105 , H01L2924/00 , H01L2224/45099
摘要： The production of a crack in an insulating film under an external terminal of a semiconductor device due to external force applied to the external terminal is suppressed or prevented. Over the principal surface of a semiconductor substrate, there are formed multiple wiring layers. In the fifth wiring layer directly under the uppermost wiring layer of the wiring layers, the following measure is taken: a conductor pattern (fifth wiring, dummy wiring, and plug) is not formed directly under the probe contact area of each bonding pad PD in the uppermost wiring layer. In the fifth wiring layer, conductor patterns (fifth wiring, dummy wirings, and plugs) are formed in the areas other than directly under the probe contact area of each bonding pad in the uppermost wiring layer.
摘要翻译：抑制或防止由于施加到外部端子的外力而在半导体器件的外部端子下的绝缘膜中产生裂纹。在半导体衬底的主表面上形成多个布线层。在配线层的最上层布线层的正下方的第五布线层中，采取以下措施：在每个焊盘PD的探针接触区域的正下方不形成导体图案（第五布线，虚拟布线和插头）最上面的布线层。在第五布线层中，在最上层配线层的各接合焊盘的探针接触区域的正下方的区域形成有导体图案（第五布线，虚拟布线和插头）。

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