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1. 发明申请

US20110001246A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110001246A1
公开(公告)日：2011-01-06
申请号：US12883031
申请日：2010-09-15
申请人： Takeshi FURUSAWA , Takao Kamoshima , Masatsugu Amishiro , Naohito Suzumura , Shoichi Fukui , Masakazu Okada
发明人： Takeshi FURUSAWA , Takao Kamoshima , Masatsugu Amishiro , Naohito Suzumura , Shoichi Fukui , Masakazu Okada
IPC分类号： H01L23/48
CPC分类号： H01L21/76832 , H01L21/76834 , H01L21/76883
摘要： The reliability of a semiconductor device having an embedded wire in the lowest layer wire is improved. In a main surface of a semiconductor substrate, MISFETs are formed and over the main surface, insulating films 10, 11 are formed. In the insulating films 10, 11 a contact hole is formed and a plug is embedded therein. Over the insulating film 11 in which the plug is embedded, insulating films 14, 15, 16 are formed and an opening is formed in the insulating films 14, 15, 16 and a wire is embedded therein. The insulating film 15 is an etching stopper film when etching the insulating film 16 in order to form the opening, containing silicon and carbon. The insulating film 11 has a high hygroscopicity and the insulating film 15 has a low moisture resistance, however, by interposing the insulating film 14 therebetween and making the insulating film 14 have a higher density of the number of Si (silicon) atoms than that of the insulating film 11, an electrically weak interface is prevented from being formed.
摘要翻译：提高了在最低层布线中具有嵌入线的半导体器件的可靠性。在半导体衬底的主表面中，形成MISFET，并且在主表面上形成绝缘膜10,11。在绝缘膜10,11中形成有接触孔，并且插入插头。在插入插头的绝缘膜11上形成绝缘膜14,15,16，并且在绝缘膜14,15,16中形成开口，并且在其中嵌入线。绝缘膜15是在蚀刻绝缘膜16以形成包含硅和碳的开口时的蚀刻停止膜。绝缘膜11具有高的吸湿性，绝缘膜15具有低的耐湿性，然而，通过在其间插入绝缘膜14，使得绝缘膜14具有比Si（硅）原子数更高的Si（硅）原子数绝缘膜11，电阻弱的界面被防止形成。

2. 发明申请

US20090184424A1 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090184424A1
公开(公告)日：2009-07-23
申请号：US12350268
申请日：2009-01-08
申请人： Takeshi Furusawa , Takao Kamoshima , Masatsugu Amishiro
发明人： Takeshi Furusawa , Takao Kamoshima , Masatsugu Amishiro
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/535 , H01L22/32 , H01L23/522 , H01L23/562 , H01L23/585 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/48 , H01L2224/02126 , H01L2224/02166 , H01L2224/0392 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05095 , H01L2224/05166 , H01L2224/05187 , H01L2224/05548 , H01L2224/05553 , H01L2224/05624 , H01L2224/05647 , H01L2224/45015 , H01L2224/48463 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/20753 , H01L2924/30105 , H01L2924/00 , H01L2224/45099
摘要： The production of a crack in an insulating film under an external terminal of a semiconductor device due to external force applied to the external terminal is suppressed or prevented. Over the principal surface of a semiconductor substrate, there are formed multiple wiring layers. In the fifth wiring layer directly under the uppermost wiring layer of the wiring layers, the following measure is taken: a conductor pattern (fifth wiring, dummy wiring, and plug) is not formed directly under the probe contact area of each bonding pad PD in the uppermost wiring layer. In the fifth wiring layer, conductor patterns (fifth wiring, dummy wirings, and plugs) are formed in the areas other than directly under the probe contact area of each bonding pad in the uppermost wiring layer.
摘要翻译：抑制或防止由于施加到外部端子的外力而在半导体器件的外部端子下的绝缘膜中产生裂纹。在半导体衬底的主表面上形成多个布线层。在配线层的最上层布线层的正下方的第五布线层中，采取以下措施：在每个焊盘PD的探针接触区域的正下方不形成导体图案（第五布线，虚拟布线和插头）最上面的布线层。在第五布线层中，在最上层配线层的各接合焊盘的探针接触区域的正下方的区域形成有导体图案（第五布线，虚拟布线和插头）。

3. 发明申请

US20080230847A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080230847A1
公开(公告)日：2008-09-25
申请号：US12014078
申请日：2008-01-14
申请人： Takeshi Furusawa , Takao Kamoshima , Masatsugu Amishiro , Naohito Suzumura , Shoichi Fukui , Masakazu Okada
发明人： Takeshi Furusawa , Takao Kamoshima , Masatsugu Amishiro , Naohito Suzumura , Shoichi Fukui , Masakazu Okada
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/76832 , H01L21/76834 , H01L21/76883
摘要： The reliability of a semiconductor device having an embedded wire in the lowest layer wire is improved. In a main surface of a semiconductor substrate, MISFETs are formed and over the main surface, insulating films 10, 11 are formed. In the insulating films 10, 11 a contact hole is formed and a plug is embedded therein. Over the insulating film 11 in which the plug is embedded, insulating films 14, 15, 16 are formed and an opening is formed in the insulating films 14, 15, 16 and a wire is embedded therein. The insulating film 15 is an etching stopper film when etching the insulating film 16 in order to form the opening, containing silicon and carbon. The insulating film 11 has a high hygroscopicity and the insulating film 15 has a low moisture resistance, however, by interposing the insulating film 14 therebetween and making the insulating film 14 have a higher density of the number of Si (silicon) atoms than that of the insulating film 11, an electrically weak interface is prevented from being formed.
摘要翻译：提高了在最低层布线中具有嵌入线的半导体器件的可靠性。在半导体衬底的主表面中，形成MISFET，并且在主表面上形成绝缘膜10,11。在绝缘膜10,11中形成有接触孔，并且插入插头。在插入插头的绝缘膜11上形成绝缘膜14,15,16，并且在绝缘膜14,15,16中形成开口，并且在其中嵌入线。绝缘膜15是在蚀刻绝缘膜16以形成包含硅和碳的开口时的蚀刻停止膜。绝缘膜11具有高的吸湿性，绝缘膜15具有低的耐湿性，然而，通过在其间插入绝缘膜14，使得绝缘膜14具有比Si（硅）原子数更高的Si（硅）原子数绝缘膜11，电阻弱的界面被防止形成。

4. 发明授权

US08203210B2 Semiconductor device having metal contacts formed in an interlayer dielectric film comprising four silicon-containing layers 失效
标题翻译：具有形成在包含四个含硅层的层间电介质膜中的金属触点的半导体器件
公开(公告)号：US08203210B2
公开(公告)日：2012-06-19
申请号：US12883031
申请日：2010-09-15
申请人： Takeshi Furusawa , Takao Kamoshima , Masatsugu Amishiro , Naohito Suzumura , Shoichi Fukui , Masakazu Okada
发明人： Takeshi Furusawa , Takao Kamoshima , Masatsugu Amishiro , Naohito Suzumura , Shoichi Fukui , Masakazu Okada
IPC分类号： H01L23/48
CPC分类号： H01L21/76832 , H01L21/76834 , H01L21/76883
摘要： The reliability of a semiconductor device having an embedded wire in the lowest layer wire is improved. In a main surface of a semiconductor substrate, MISFETs are formed and over the main surface, insulating films 10, 11 are formed. In the insulating films 10, 11 a contact hole is formed and a plug is embedded therein. Over the insulating film 11 in which the plug is embedded, insulating films 14, 15, 16 are formed and an opening is formed in the insulating films 14, 15, 16 and a wire is embedded therein. The insulating film 15 is an etching stopper film when etching the insulating film 16 in order to form the opening, containing silicon and carbon. The insulating film 11 has a high hygroscopicity and the insulating film 15 has a low moisture resistance, however, by interposing the insulating film 14 therebetween and making the insulating film 14 have a higher density of the number of Si (silicon) atoms than that of the insulating film 11, an electrically weak interface is prevented from being formed.
摘要翻译：提高了在最低层布线中具有嵌入线的半导体器件的可靠性。在半导体衬底的主表面中，形成MISFET，并且在主表面上形成绝缘膜10,11。在绝缘膜10,11中形成有接触孔，并且插入插头。在插入插头的绝缘膜11上形成绝缘膜14,15,16，并且在绝缘膜14,15,16中形成开口，并且在其中嵌入线。绝缘膜15是在蚀刻绝缘膜16以形成包含硅和碳的开口时的蚀刻停止膜。绝缘膜11具有高的吸湿性，绝缘膜15具有低的耐湿性，然而，通过在其间插入绝缘膜14，使得绝缘膜14具有比Si（硅）原子数更高的Si（硅）原子数绝缘膜11，电阻弱的界面被防止形成。

5. 发明申请

US20100314620A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20100314620A1
公开(公告)日：2010-12-16
申请号：US12794739
申请日：2010-06-05
申请人： Takeshi FURUSAWA , Takao Kamoshima , Hiroki Takewaka
发明人： Takeshi FURUSAWA , Takao Kamoshima , Hiroki Takewaka
IPC分类号： H01L23/48
CPC分类号： H01L22/32 , H01L21/768 , H01L23/53223 , H01L23/53238 , H01L24/05 , H01L2224/02166 , H01L2224/04042 , H01L2224/05073 , H01L2224/05093 , H01L2224/05166 , H01L2224/05187 , H01L2224/05624 , H01L2224/05647 , H01L2224/45147 , H01L2224/48847 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01082 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/1306 , H01L2924/3011 , H01L2924/351 , H01L2924/00014 , H01L2224/48824 , H01L2924/00
摘要： To suppress or prevent the generation of a crack in an insulating film below an external terminal which could be caused by an external force added to the external terminal of a semiconductor device. A top wiring layer MH of wiring layers formed on a main surface of a silicon substrate has a pad comprising a conductor pattern containing aluminum. On an undersurface of the pad, there are arranged a barrier conductor film formed by laminating, from below, a first barrier conductor film and a second barrier conductor film. Of a fifth wiring layer which is one layer lower than the top wiring layer, in an area overlapping with a probe contact area of the pad in a plane, the conductor pattern is not arranged. Further, the first and second barrier conductor films are the conductor films including titanium and titanium nitride as principal components, respectively. Also, the first barrier conductor film is thicker than the second barrier conductor film.
摘要翻译：抑制或防止在外部端子下面的绝缘膜中产生裂纹，该绝缘膜可能由于加到半导体器件的外部端子上的外力引起。形成在硅衬底的主表面上的布线层的顶部布线层MH具有包括含有铝的导体图案的衬垫。在焊盘的下表面上，设置有由第一阻挡导体膜和第二阻挡导体膜从下方层叠形成的阻挡导体膜。在比顶部布线层低一层的第五布线层中，在与平面中的焊盘的探针接触区域重叠的区域中，不布置导体图案。此外，第一和第二阻挡导体膜分别是包括钛和氮化钛作为主要成分的导体膜。此外，第一阻挡导体膜比第二阻挡导体膜厚。

6. 发明授权

US06740564B2 Method for manufacturing a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US06740564B2
公开(公告)日：2004-05-25
申请号：US10192629
申请日：2002-07-11
申请人： Takao Kamoshima , Takeru Matsuoka , Takashi Yamashita
发明人： Takao Kamoshima , Takeru Matsuoka , Takashi Yamashita
IPC分类号： H01L23544
CPC分类号： H01L21/76847 , H01L21/76849 , H01L21/76877
摘要： A method for manufacturing a semiconductor device wherein a contact hole formed in an interlayer insulating film on a semiconductor substrate is filled with a plug for electrically connecting an overlying conductor layer with an underlying conductor layer. The plug fills the contact hole, and comprised a tungsten film the upper end whereof is positioned below the upper surface of the interlayer insulating film, and a tungsten film which is filled on the tungsten film in the contact hole and the upper surface whereof is on substantially the same level as the upper surface of the interlayer insulating film.
摘要翻译：一种制造半导体器件的方法，其中形成在半导体衬底上的层间绝缘膜中的接触孔填充有用于将上覆导体层与下面的导体层电连接的插头。插头填充接触孔，并且包括其上端位于层间绝缘膜的上表面下方的钨膜，以及填充在接触孔中的钨膜上的钨膜和其上表面与层间绝缘膜的上表面基本相同的水平。

7. 发明授权

US06645863B2 Method of manufacturing semiconductor device and semiconductor device 失效
标题翻译：制造半导体器件和半导体器件的方法
公开(公告)号：US06645863B2
公开(公告)日：2003-11-11
申请号：US09986001
申请日：2001-11-07
申请人： Hiroki Takewaka , Takao Kamoshima , Junko Izumitani
发明人： Hiroki Takewaka , Takao Kamoshima , Junko Izumitani
IPC分类号： H01L2100
CPC分类号： H01L21/7684 , H01L21/28556 , H01L21/3212 , H01L21/76877 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： The invention provides a method of manufacturing a semiconductor device which can reduce or prevent abrasive material from remaining in an indentation in a surface after a CMP process. After forming a titanium nitride film (5), a tungsten film (6) is formed on an entire surface. The temperature is set at approximately 430° C. for the reaction and, first, 50 sccm of WF6, 10 sccm of SiH4 and 1000 sccm of H2 are used in the atmosphere of 30 Torr of Ar, N2 so as to form a seed layer with a film thickness of approximately 100 nm. After that, in the atmosphere of 80 Torr of Ar, N2, 75 sccm of WF6 and 500 sccm of H2 are used as a reactive gas so as to layer a film with a thickness of approximately 300 nm. The tungsten film (6) has grains (6a) in a pillar form of which the grain diameter is small to the degree that the abrasive material (50) used in the CMP process does not easily become caught in the gaps between the grains. Concretely, the tungsten film (6) has grains (6a) of which the diameter is approximately 10 nm to 20 nm.
摘要翻译：本发明提供一种半导体器件的制造方法，其可以在CMP工艺之后减少或防止研磨材料残留在表面的压痕中。在形成氮化钛膜（5）之后，形成钨膜（6）整个表面。对于反应，温度设定在约430℃，首先在30托的Ar，N2的气氛中使用50sccm的WF6，10sccm的SiH4和1000sccm的H 2，以形成种子层膜厚度约为100nm。之后，在80Torr的Ar，N2的气氛中，使用75sccm的WF6和500sccm的H 2作为反应气体，以便层厚约300nm的膜。钨膜（6）具有柱状晶粒（6a），其晶粒直径小到在CMP工艺中使用的研磨材料（50）不容易被捕获在晶粒之间的间隙中的程度。具体地说，钨膜（6）具有直径约为10nm〜20nm的晶粒（6a）。

8. 发明授权

US06503836B2 Method and apparatus for manufacturing semiconductor device 失效
公开(公告)号：US06503836B2
公开(公告)日：2003-01-07
申请号：US09782281
申请日：2001-02-14
申请人： Takeru Matsuoka , Takashi Yamashita , Takao Kamoshima
发明人： Takeru Matsuoka , Takashi Yamashita , Takao Kamoshima
IPC分类号： H01L21302
CPC分类号： H01L21/31053 , H01L21/31625 , H01L21/76825 , H01L21/76828
摘要： A method and apparatus for manufacturing a semiconductor device having an interlayer insulating film of improved flatness after a CMP process are obtained. The method includes the steps of: heat-treating a semiconductor device having an interlayer insulating film containing impurities; conducting a process for making an impurity-concentration distribution at an upper layer portion of the interlayer insulating film substantially uniform after the heat treatment; and polishing the interlayer insulating film by a CMP process after the process for making the impurity-concentration distribution substantially uniform.

9. 发明授权

US06214723B1 Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06214723B1
公开(公告)日：2001-04-10
申请号：US09391388
申请日：1999-09-08
申请人： Takao Kamoshima , Hiroki Takewaka , Takashi Yamashita
发明人： Takao Kamoshima , Hiroki Takewaka , Takashi Yamashita
IPC分类号： H01L2144
CPC分类号： H01L23/53223 , H01L21/32051 , H01L21/76885 , H01L2924/0002 , Y10S438/978 , H01L2924/00
摘要： A method of manufacturing a semiconductor device with high reliability is provided in which an insulating property of an insulating layer is high and connection failure is prevented. The semiconductor device includes: a silicon substrate; a low-temperature aluminum film formed on silicon substrate and including a polycrystal; and a high-temperature aluminum film. An opening is formed in a surface of a high-temperature aluminum film by a crystal grain boundary. A distance between side walls of the opening becomes small as closer to silicon substrate.
摘要翻译：提供一种制造具有高可靠性的半导体器件的方法，其中绝缘层的绝缘性能高并且防止了连接故障。半导体器件包括：硅衬底; 在硅衬底上形成的包含多晶的低温铝膜; 和高温铝膜。通过晶界在高温铝膜的表面形成开口。开口的侧壁之间的距离变得越小，越接近硅衬底。

10. 发明申请

US20070029677A1 Interconnection structure 审中-公开
标题翻译：互连结构
公开(公告)号：US20070029677A1
公开(公告)日：2007-02-08
申请号：US11488634
申请日：2006-07-19
申请人： Takao Kamoshima , Yasuhisa Fujii , Takeshi Masamitsu
发明人： Takao Kamoshima , Yasuhisa Fujii , Takeshi Masamitsu
IPC分类号： H01L23/48
CPC分类号： H01L21/76843 , H01L21/76844 , H01L21/76877 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An interconnection structure includes a lower interconnection layer formed on a substrate and composed of a copper layer, an interlayer insulating layer formed on the lower interconnection layer and having a via reaching the lower interconnection layer, an upper interconnection layer electrically connected to the lower interconnection layer through the via, and composed of a copper layer formed in the interlayer insulating layer, and a barrier metal layer formed between the upper interconnection layer and the interlayer insulating layer. The barrier metal layer has an opening in a bottom portion of the via, and through that opening, the upper interconnection layer comes in direct contact with the lower interconnection layer in the bottom portion of the via. Thus, an interconnection structure suppressing concentration of voids in an interconnection under a via due to stress migration can be attained.
摘要翻译：互连结构包括形成在基板上并由铜层构成的下互连层，形成在下布线层上并具有到达下互连层的通孔的层间绝缘层，与互连层下电连接的上互连层并且由形成在层间绝缘层中的铜层构成，以及形成在上互连层和层间绝缘层之间的阻挡金属层。阻挡金属层在通孔的底部具有开口，并且通过该开口，上互连层与通孔的底部中的下互连层直接接触。因此，可以获得抑制由于应力迁移导致的通孔内的互连中的空隙浓度的互连结构。

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