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1. 发明授权

US08513808B2 Semiconductor device having trench-isolated element formation region 有权
标题翻译：具有沟槽隔离元件形成区域的半导体器件
公开(公告)号：US08513808B2
公开(公告)日：2013-08-20
申请号：US13095735
申请日：2011-04-27
申请人： Katsuhiko Hotta , Takeshi Furusawa , Toshikazu Matsui , Takuro Homma
发明人： Katsuhiko Hotta , Takeshi Furusawa , Toshikazu Matsui , Takuro Homma
IPC分类号： H01L23/522 , H01L21/768 , H01L23/525
CPC分类号： H01L24/03 , H01L23/522 , H01L23/53223 , H01L23/585 , H01L24/05 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05093 , H01L2224/05096 , H01L2224/05166 , H01L2224/05187 , H01L2224/05554 , H01L2224/05567 , H01L2224/05571 , H01L2224/05624 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01021 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/04941 , H01L2924/1306 , H01L2924/14 , H01L2924/04953 , H01L2924/00014 , H01L2924/00 , H01L2224/05552
摘要： Provided is a technique capable of improving the reliability of a semiconductor device having a slit made over a main surface of a semiconductor substrate, so as to surround each element formation region. In the technique, a second passivation film covers the side surface of an opening made to make the upper surface of a sixth-layer interconnection M6 used for bonding pads naked, and the inner walls (the side surfaces and the bottom surface) of a slit made to surround the circumference of a guard ring and made in a first passivation film, an insulating film for bonding, and an interlayer dielectric, so as to cause the bottom thereof not to penetrate through a barrier insulating film.
摘要翻译：提供了一种能够提高半导体器件的半导体器件的可靠性的技术，该半导体器件具有在半导体衬底的主表面上形成的狭缝，以便围绕每个元件形成区域。在该技术中，第二钝化膜覆盖开口的侧表面，使得用于接合焊盘的第六层互连M6的上表面裸露，狭缝的内壁（侧表面和底表面）围绕保护环的周围并制成第一钝化膜，用于接合的绝缘膜和层间电介质，以使其底部不穿透阻挡绝缘膜。

2. 发明申请

US20110266679A1 SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件和半导体器件的制造方法
公开(公告)号：US20110266679A1
公开(公告)日：2011-11-03
申请号：US13095735
申请日：2011-04-27
申请人： Katsuhiko Hotta , Takeshi Furusawa , Toshikazu Matsui , Takuro Homma
发明人： Katsuhiko Hotta , Takeshi Furusawa , Toshikazu Matsui , Takuro Homma
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L24/03 , H01L23/522 , H01L23/53223 , H01L23/585 , H01L24/05 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05093 , H01L2224/05096 , H01L2224/05166 , H01L2224/05187 , H01L2224/05554 , H01L2224/05567 , H01L2224/05571 , H01L2224/05624 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01021 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/04941 , H01L2924/1306 , H01L2924/14 , H01L2924/04953 , H01L2924/00014 , H01L2924/00 , H01L2224/05552
摘要： Provided is a technique capable of improving the reliability of a semiconductor device having a slit made over a main surface of a semiconductor substrate, so as to surround each element formation region. In the technique, a second passivation film covers the side surface of an opening made to make the upper surface of a sixth-layer interconnection M6 used for bonding pads naked, and the inner walls (the side surfaces and the bottom surface) of a slit made to surround the circumference of a guard ring and made in a first passivation film, an insulating film for bonding, and an interlayer dielectric, so as to cause the bottom thereof not to penetrate through a barrier insulating film.
摘要翻译：提供了一种能够提高半导体器件的半导体器件的可靠性的技术，该半导体器件具有在半导体衬底的主表面上形成的狭缝，以便围绕每个元件形成区域。在该技术中，第二钝化膜覆盖开口的侧表面，使得用于接合焊盘的第六层互连M6的上表面裸露，并且狭缝的内壁（侧表面和底表面）围绕保护环的周围并制成第一钝化膜，用于接合的绝缘膜和层间电介质，以使其底部不穿透阻挡绝缘膜。

3. 发明申请

US20100237404A1 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100237404A1
公开(公告)日：2010-09-23
申请号：US12718002
申请日：2010-03-05
申请人： KOICHI TOBA , Yasushi Ishii , Yoshiyuki Kawashima , Satoru Machida , Munekatsu Nakagawa , Kentaro Saito , Toshikazu Matsui , Takashi Hashimoto , Kosuke Okuyama
发明人： KOICHI TOBA , Yasushi Ishii , Yoshiyuki Kawashima , Satoru Machida , Munekatsu Nakagawa , Kentaro Saito , Toshikazu Matsui , Takashi Hashimoto , Kosuke Okuyama
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/42324 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11526 , H01L27/11531 , H01L29/66825 , H01L29/66833 , H01L29/7885
摘要： A semiconductor device having a non-volatile memory is disclosed, whose disturb defect can be diminished or prevented. A memory cell of the non-volatile memory has a memory gate electrode formed over a main surface of a semiconductor substrate through an insulating film for charge storage. A first side wall is formed on a side face of the memory gate electrode, and at a side face of the first side wall, a second side wall is formed. On an upper surface of an n+-type semiconductor region for source in the memory cell there is formed a silicide layer whose end portion on the memory gate electrode MG side is defined by the second side wall.
摘要翻译：公开了一种具有非易失性存储器的半导体器件，其干扰缺陷可被减弱或防止。非易失性存储器的存储单元具有通过用于电荷存储的绝缘膜形成在半导体衬底的主表面上的存储栅电极。第一侧壁形成在存储栅电极的侧面上，在第一侧壁的侧面形成有第二侧壁。在存储单元中用于源极的n +型半导体区域的上表面上形成硅化物层，其存储栅极电极MG侧的端部由第二侧壁限定。

4. 发明申请

US20100144108A1 METHOD OF MANUFACTURING A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE, AND A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：制造非易失性半导体存储器件的方法和非易失性半导体存储器件
公开(公告)号：US20100144108A1
公开(公告)日：2010-06-10
申请号：US12706668
申请日：2010-02-16
申请人： Takeshi SAKAI , Yasushi Ishii , Tsutomu Okazaki , Masaru Nakamichi , Toshikazu Matsui , Kyoya Nitta , Satoru Machida , Munekatsu Nakagawa , Yuichi Tsukada
发明人： Takeshi SAKAI , Yasushi Ishii , Tsutomu Okazaki , Masaru Nakamichi , Toshikazu Matsui , Kyoya Nitta , Satoru Machida , Munekatsu Nakagawa , Yuichi Tsukada
IPC分类号： H01L21/8246
CPC分类号： H01L27/11568 , H01L21/823842 , H01L21/82385 , H01L21/823857 , H01L21/823864 , H01L27/105 , H01L27/1052 , H01L27/11573
摘要： For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.
摘要翻译：为了增强具有MONOS型晶体管的非易失性半导体存储器件的高性能，非易失性半导体存储器件被提供有具有改进性能的MONOS型晶体管，其中MONOS非易失性存储器的存储单元包括控制晶体管和存储晶体管。控制晶体管的控制栅极包括n型多晶硅膜，并且形成在包括氧化硅膜的栅极绝缘膜上。存储晶体管的存储栅极包括n型多晶硅膜，并设置在控制栅极的一个侧壁上。存储器栅极包括具有低于控制栅极的薄层电阻的掺杂多晶硅膜，其包括通过将杂质离子注入未掺杂的硅膜形成的多晶硅膜。

5. 发明授权

US07245531B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07245531B2
公开(公告)日：2007-07-17
申请号：US11198191
申请日：2005-08-08
申请人： Tsutomu Okazaki , Daisuke Okada , Kyoya Nitta , Toshihiro Tanaka , Akira Kato , Toshikazu Matsui , Yasushi Ishii , Digh Hisamoto , Kan Yasui
发明人： Tsutomu Okazaki , Daisuke Okada , Kyoya Nitta , Toshihiro Tanaka , Akira Kato , Toshikazu Matsui , Yasushi Ishii , Digh Hisamoto , Kan Yasui
IPC分类号： G11C11/34
CPC分类号： H01L27/1157 , G11C16/0425 , H01L21/28282 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L29/0649 , H01L29/4234 , H01L29/42344 , H01L29/518 , H01L29/66833 , H01L29/792
摘要： Memory cells are disposed in plural array form. Select gate electrodes of the memory cells arranged in an X direction are connected to one another by select gate lines respectively. Memory gate electrodes are connected by memory gate lines respectively. The memory gate lines respectively connected to the memory gate electrodes of the memory cells adjacent to one another through source regions interposed therebetween are not electrically connected to one another. Each of the select gate lines has a first portion that extends in the X direction, and a second portion 9b of which one end is connected to the first portion and extends in a Y direction. The memory gate line is formed on its corresponding sidewall of the select gate line with an insulating film interposed therebetween. The memory gate line has a contact section that extends in the X direction from over a second portion of the select gate line to over an element isolation region, and is connected to its corresponding wiring through a plug that buries a contact hole formed over the contact section.
摘要翻译：存储单元以多个阵列形式布置。选择沿X方向布置的存储单元的选择栅电极分别通过选择栅极线彼此连接。存储器栅极电极分别由存储器栅极线连接。分别连接到彼此相邻的存储单元的存储器栅极的存储栅极线通过其间的源极区域彼此不电连接。每个选择栅极线具有在X方向上延伸的第一部分和其一端连接到第一部分并沿Y方向延伸的第二部分9b。存储栅极线在其选择栅线的相应侧壁上形成有介于其间的绝缘膜。存储栅极线具有接触部分，该接触部分在选择栅极线的第二部分上方在X方向上延伸到元件隔离区域上方，并且通过塞子连接到其对应的布线，所述插头埋设形成在触点上的接触孔部分。

6. 发明申请

US20060028868A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060028868A1
公开(公告)日：2006-02-09
申请号：US11198191
申请日：2005-08-08
申请人： Tsutomu Okazaki , Daisuke Okada , Kyoya Nitta , Toshihiro Tanaka , Akira Kato , Toshikazu Matsui , Yasushi Ishii , Digh Hisamoto , Kan Yasui
发明人： Tsutomu Okazaki , Daisuke Okada , Kyoya Nitta , Toshihiro Tanaka , Akira Kato , Toshikazu Matsui , Yasushi Ishii , Digh Hisamoto , Kan Yasui
IPC分类号： G11C11/34 , G11C5/06
CPC分类号： H01L27/1157 , G11C16/0425 , H01L21/28282 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L29/0649 , H01L29/4234 , H01L29/42344 , H01L29/518 , H01L29/66833 , H01L29/792
摘要： Memory cells are disposed in plural array form. Select gate electrodes of the memory cells arranged in an X direction are connected to one another by select gate lines respectively. Memory gate electrodes are connected by memory gate lines respectively. The memory gate lines respectively connected to the memory gate electrodes of the memory cells adjacent to one another through source regions interposed therebetween are not electrically connected to one another. Each of the select gate lines has a first portion that extends in the X direction, and a second portion 9b of which one end is connected to the first portion and extends in a Y direction. The memory gate line is formed on its corresponding sidewall of the select gate line with an insulating film interposed therebetween. The memory gate line has a contact section that extends in the X direction from over a second portion of the select gate line to over an element isolation region, and is connected to its corresponding wiring through a plug that buries a contact hole formed over the contact section.
摘要翻译：存储单元以多个阵列形式布置。选择沿X方向布置的存储单元的选择栅电极分别通过选择栅极线彼此连接。存储器栅极电极分别由存储器栅极线连接。分别连接到彼此相邻的存储单元的存储器栅极的存储栅极线通过其间的源极区域彼此不电连接。每个选择栅极线具有在X方向上延伸的第一部分和其一端连接到第一部分并沿Y方向延伸的第二部分9b。存储栅极线在其选择栅线的相应侧壁上形成有介于其间的绝缘膜。存储栅极线具有接触部分，该接触部分在选择栅极线的第二部分上方在X方向上延伸到元件隔离区域上方，并且通过塞子连接到其对应的布线，所述插头埋设形成在触点上的接触孔部分。

7. 发明授权

US5668648A Computer-assisted holographic display apparatus 失效
标题翻译：计算机辅助全息显示装置
公开(公告)号：US5668648A
公开(公告)日：1997-09-16
申请号：US261709
申请日：1994-06-17
申请人： Tutomu Saito , Toshikazu Matsui
发明人： Tutomu Saito , Toshikazu Matsui
IPC分类号： G03H1/08 , G03H1/04
CPC分类号： G03H1/0841 , G03H1/08 , Y10S359/90
摘要： A computer-assisted holographic-display apparatus comprises a diffraction image generator which receives an input image signal representing an object and computes corresponding diffraction pattern with a first sampling density. An interpolation processor is connected to the diffraction image generator via an intermediate page memory. The interpolation processor subjects the diffraction pattern to the interpolation process to create an interpolated diffraction pattern with an increased second sampling density. An interference pattern generator is connected to the interpolation processor to compute an interference caused pattern between the interpolated diffraction pattern and a reference wave by converting amplitude and phase distributions of the input image signal into the intensity distribution. The interference pattern is displayed on a previously selected displaying device.
摘要翻译：计算机辅助全息显示装置包括：衍射图像生成器，其接收表示对象的输入图像信号，并以第一采样密度计算相应的衍射图案。内插处理器经由中间页存储器连接到衍射图像生成器。内插处理器将衍射图案进行插值处理，以产生具有增加的第二采样密度的内插衍射图案。干涉图案发生器连接到内插处理器，通过将输入图像信号的幅度和相位分布转换成强度分布来计算内插衍射图案和参考波之间的干涉引起的图形。干扰图案显示在先前选择的显示设备上。

8. 发明授权

US5305994A Sorter with rotary spirals and guide rails 失效
标题翻译：带旋转螺旋和导轨的分拣机
公开(公告)号：US5305994A
公开(公告)日：1994-04-26
申请号：US912460
申请日：1992-07-13
申请人： Toshikazu Matsui , Takatoshi Nishimura , Kenichi Honda , Shoichiro Tajima , Keiichi Asano , Hiroyuki Nagai , Nobukazu Ootsuka
发明人： Toshikazu Matsui , Takatoshi Nishimura , Kenichi Honda , Shoichiro Tajima , Keiichi Asano , Hiroyuki Nagai , Nobukazu Ootsuka
IPC分类号： B65H39/11 , G03G15/00 , B65H39/10 , B65H39/05 , G03G21/00
CPC分类号： G03G15/6541 , B65H39/11 , B65H2403/511 , B65H2408/113 , G03G2215/00818 , G03G2215/00827
摘要： A sorter includes a sheet processing device, a plurality of bin trays arranged in a vertical direction, each bin tray having a specified width and length and adapted for bearing a sheet, shifting means for shifting the plurality of bin trays in the vertical direction, and moving means for moving the bin tray in a predetermined position in a lengthwise direction of the bin tray so that the sheet on the bin tray is processed by the sheet processing device. The bin tray can be moved to a position where sheet processing is to be applied by the sheet processing device.
摘要翻译：分拣机包括纸张处理装置，沿垂直方向布置的多个纸盘托架，每个纸盘托盘具有指定的宽度和长度并适于承载纸张;移位装置，用于在垂直方向上移动多个纸盘托盘;以及移动装置，用于沿纸箱托盘的长度方向移动箱托盘，使得纸盘处理装置处理纸盘托盘上的纸张。纸盒托盘可以移动到纸张处理装置应用纸张处理的位置。

9. 发明授权

US5175635A Picture printing apparatus using multivalued patterns, binary patterns and dither patterns selectively 失效
标题翻译：图像打印装置选择性地使用多值图案，二进制图案和抖动图案
公开(公告)号：US5175635A
公开(公告)日：1992-12-29
申请号：US703052
申请日：1991-05-17
申请人： Kiyoshi Yamada , Shuzo Hirahara , Toshikazu Matsui , Kazuhiko Higuchi
发明人： Kiyoshi Yamada , Shuzo Hirahara , Toshikazu Matsui , Kazuhiko Higuchi
IPC分类号： H04N1/40 , H04N1/403 , H04N1/405
CPC分类号： H04N1/403 , H04N1/40062 , H04N1/40087 , H04N1/4051
摘要： A picture printing apparatus is disclosed which includes a picture type judgement means, and a best mode printing system is determined according to the judging result. A mixed mode picture including a binary picture element and a gradational picture element is printed to utilize selectively the binary method, multivalence concentration pattern method and the dither method.
摘要翻译：公开了一种图像打印装置，其包括图像类型判断装置，并且根据判断结果确定最佳模式打印系统。打印包括二进制图像元素和等级图像元素的混合模式图像以选择性地利用二值法，多值浓度图案法和抖动法。

10. 发明授权

US4884080A Color image printing apparatus 失效
标题翻译：彩色图像打印设备
公开(公告)号：US4884080A
公开(公告)日：1989-11-28
申请号：US56763
申请日：1987-06-02
申请人： Shuzo Hirahara , Hitoshi Nagato , Kazuhiko Higuchi , Kiyoshi Yamada , Tadayoshi Ohno , Tsutomu Kanai , Toshikazu Matsui
发明人： Shuzo Hirahara , Hitoshi Nagato , Kazuhiko Higuchi , Kiyoshi Yamada , Tadayoshi Ohno , Tsutomu Kanai , Toshikazu Matsui
IPC分类号： G01D15/10 , H04N1/40 , H04N1/405 , H04N1/52
CPC分类号： H04N1/52 , G01D15/10 , H04N1/40087 , H04N1/4058
摘要： A color image printing apparatus prints one pixel by superposing a predetermined dots of three colors within a 3.times.3 dot matrix in accordance with a density of the pixel. The positions of the printed dots within the dot matrix are stored as a dot pattern for each color. One dot pattern is used for each of a plurality of densities included in one density range. The printing energy for each of the dots included in the dot pattern is controlled in accordance with the density level of the pixel. The dot pattern is different for each color and three dot patterns are stored for each color and for each density range. These three dot patterns are repeatedly used for every three pixels which are continuous in the horizontal direction. These three dot patterns have two or three texture directions. The texture direction other than the vertical direction is different for each color.
摘要翻译：彩色图像打印设备根据像素的密度，通过在3×3点阵中叠加三种颜色的预定点来打印一个像素。点阵内的打印点的位置被存储为每种颜色的点阵图形。一个点图案用于包括在一个密度范围内的多个密度中的每一个。根据像素的浓度水平来控制点图案中包括的每个点的打印能量。点阵图案对于每种颜色是不同的，并且针对每个颜色和每个浓度范围存储三个点图案。对于在水平方向上连续的每三个像素重复使用这三个点图案。这三个点图案具有两个或三个纹理方向。垂直方向以外的纹理方向对于每种颜色都是不同的。

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