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    • 1. 发明授权
    • Method of product performance improvement by selective feature sizing of semiconductor devices
    • 通过半导体器件的选择特征尺寸来改善产品性能的方法
    • US08302064B1
    • 2012-10-30
    • US12401450
    • 2009-03-10
    • Sharmin SadoughiPrabhuram GopalanMichael J. HartJohn CookseyZhiyuan Wu
    • Sharmin SadoughiPrabhuram GopalanMichael J. HartJohn CookseyZhiyuan Wu
    • G06F9/455G06F17/50
    • G06F17/5072
    • Device features, such as gate lengths and channel widths, are selectively altered by first identifying those devices within a semiconductor die that exhibit physical attributes, e.g., leakage current and threshold voltage magnitude, that are different than previously verified by a design/simulation tool used to design the devices. The identified, non-conforming devices are then further identified by the amount of deviation from the original design goal that is exhibited by each non-conforming device. The non-conforming devices are then mathematically categorized into bins, where each bin is tagged with a magnitude of deviation from a design goal. The mask layers defining the features of the non-conforming devices are then selectively modified by an amount that is commensurate with the tagged deviation. The selectively modified mask layers are then used to generate a new semiconductor die that exhibits improved performance.
    • 选择性地改变诸如栅极长度和沟道宽度的器件特征,首先识别半导体管芯内的这些器件,其显示物理属性,例如泄漏电流和阈值电压幅度,其不同于先前使用的设计/仿真工具验证 设计设备。 然后,通过与每个不合格设备展示的原始设计目标的偏差量进一步识别所识别的不合格设备。 然后将不合格的设备数学分类成箱体,其中每个箱体标记有与设计目标的偏差幅度。 然后,限定不合格装置的特征的掩模层被选择性地修改与标记偏差相当的量。 然后使用选择性修改的掩模层来产生表现出改善的性能的新的半导体管芯。
    • 2. 发明授权
    • Semiconductor device and method for making the same
    • 半导体装置及其制造方法
    • US08329568B1
    • 2012-12-11
    • US12772969
    • 2010-05-03
    • Jae-Gyung AhnMyongseob KimPing-Chin YehZhiyuan WuJohn Cooksey
    • Jae-Gyung AhnMyongseob KimPing-Chin YehZhiyuan WuJohn Cooksey
    • H01L21/425
    • H01L29/665H01L29/6656H01L29/78H01L29/7843H01L29/7848
    • In one embodiment of the present invention, a field effect transistor device is provided. The field effect transistor device comprises an active area, including a first semiconductor material of a first conductivity type. A channel region is included within the active area. A gate region overlays the channel region, and the first source/drain region and the second source/drain region are embedded in the active area and spaced from each other by the channel region. The first source/drain region and the second source/drain region each include a second semiconductor material of a second conductivity type opposite of the first conductivity type. A well-tap region is embedded in the active area and spaced from the first source/drain region by the channel region and the second source/drain region. The well-tap region includes the second semiconductor material of the first conductivity type. The first source/drain region and the second source/drain region and the well-tap region are epitaxial deposits.
    • 在本发明的一个实施例中,提供了场效应晶体管器件。 场效应晶体管器件包括有源区,包括第一导电类型的第一半导体材料。 通道区域包括在有效区域内。 栅极区域覆盖沟道区域,并且第一源极/漏极区域和第二源极/漏极区域被嵌入有源区域中并且被沟道区域彼此间隔开。 第一源极/漏极区域和第二源极/漏极区域各自包括与第一导电类型相反的第二导电类型的第二半导体材料。 阱区域嵌入有源区域中,并且通过沟道区域和第二源极/漏极区域与第一源极/漏极区域间隔开。 阱抽头区域包括第一导电类型的第二半导体材料。 第一源极/漏极区域和第二源极/漏极区域以及阱阱区域是外延沉积物。
    • 4. 发明授权
    • Diffusion regions having different depths
    • 具有不同深度的扩散区域
    • US08299564B1
    • 2012-10-30
    • US12559457
    • 2009-09-14
    • Yun WuBei ZhuZhiyuan WuMichael J. Hart
    • Yun WuBei ZhuZhiyuan WuMichael J. Hart
    • H01L21/336H01L21/8234
    • H01L21/823807H01L21/823814
    • Formation of transistors, such as, e.g., PMOS transistors, with diffusion regions having different depths for equalization of performance among transistors of an integrated circuit is described. Shallow-trench isolation structures are formed in a substrate formed at least in part of silicon for providing the transistors with at least substantially equivalent channel widths and lengths. A series of masks and etches is performed to form first recesses and second recesses defined in the silicon having different depths and respectively associated with first and second transistors. The second recesses are deeper than the first recesses. A silicon germanium film is formed in the first recesses and the second recesses. The silicon germanium film in the second recesses is thicker than the silicon germanium film in the first recesses, in order to increase performance of the second transistor so it is closer to the performance of the first transistor.
    • 描述了具有扩散区域的诸如PMOS晶体管的晶体管的形成,其具有用于集成电路的晶体管之间的性能均衡的不同深度。 浅沟槽隔离结构形成在至少部分硅中形成的衬底中,用于为晶体管提供至少基本相当的沟道宽度和长度。 执行一系列掩模和蚀刻以形成在具有不同深度并且分别与第一和第二晶体管相关联的硅中限定的第一凹部和第二凹部。 第二凹部比第一凹部更深。 在第一凹部和第二凹部中形成硅锗膜。 第二凹部中的硅锗膜比第一凹部中的硅锗膜厚,以便增加第二晶体管的性能,使得其更接近于第一晶体管的性能。