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1. 发明授权

US08329568B1 Semiconductor device and method for making the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08329568B1
公开(公告)日：2012-12-11
申请号：US12772969
申请日：2010-05-03
申请人： Jae-Gyung Ahn , Myongseob Kim , Ping-Chin Yeh , Zhiyuan Wu , John Cooksey
发明人： Jae-Gyung Ahn , Myongseob Kim , Ping-Chin Yeh , Zhiyuan Wu , John Cooksey
IPC分类号： H01L21/425
CPC分类号： H01L29/665 , H01L29/6656 , H01L29/78 , H01L29/7843 , H01L29/7848
摘要： In one embodiment of the present invention, a field effect transistor device is provided. The field effect transistor device comprises an active area, including a first semiconductor material of a first conductivity type. A channel region is included within the active area. A gate region overlays the channel region, and the first source/drain region and the second source/drain region are embedded in the active area and spaced from each other by the channel region. The first source/drain region and the second source/drain region each include a second semiconductor material of a second conductivity type opposite of the first conductivity type. A well-tap region is embedded in the active area and spaced from the first source/drain region by the channel region and the second source/drain region. The well-tap region includes the second semiconductor material of the first conductivity type. The first source/drain region and the second source/drain region and the well-tap region are epitaxial deposits.
摘要翻译：在本发明的一个实施例中，提供了场效应晶体管器件。场效应晶体管器件包括有源区，包括第一导电类型的第一半导体材料。通道区域包括在有效区域内。栅极区域覆盖沟道区域，并且第一源极/漏极区域和第二源极/漏极区域被嵌入有源区域中并且被沟道区域彼此间隔开。第一源极/漏极区域和第二源极/漏极区域各自包括与第一导电类型相反的第二导电类型的第二半导体材料。阱区域嵌入有源区域中，并且通过沟道区域和第二源极/漏极区域与第一源极/漏极区域间隔开。阱抽头区域包括第一导电类型的第二半导体材料。第一源极/漏极区域和第二源极/漏极区域以及阱阱区域是外延沉积物。

2. 发明授权

US06583016B1 Doped spacer liner for improved transistor performance 有权
标题翻译：掺杂间隔衬垫，用于改善晶体管性能
公开(公告)号：US06583016B1
公开(公告)日：2003-06-24
申请号：US10105522
申请日：2002-03-26
申请人： Andy C. Wei , Mark B. Fuselier , Ping-Chin Yeh
发明人： Andy C. Wei , Mark B. Fuselier , Ping-Chin Yeh
IPC分类号： H01L21336
CPC分类号： H01L29/66772 , H01L21/265 , H01L21/2652 , H01L29/6656 , H01L29/6659 , H01L29/66659 , H01L29/78603 , H01L29/78624
摘要： Semiconductor devices with improved transistor performance are fabricated by ion-implanting a dopant into the oxide liner to prevent or substantially reduce dopant out-diffusion from the shallow source/drain extensions. Embodiments include ion implanting a P-type dopant, such as B or BF2, using the gate electrode as a mask, to form shallow source/drain extensions, depositing a conformal oxide liner, and ion implanting the P-type impurity into the oxide liner at substantially the same dopant concentration as in the shallow source/drain extensions. Subsequent processing includes depositing a spacer layer, etching to form sidewall spacers, ion implanting to form deep moderate or heavy source/drain implants and activation annealing.
摘要翻译：具有改善的晶体管性能的半导体器件通过将掺杂剂离子注入到氧化物衬垫中来制造，以防止或基本上减少来自浅源极/漏极延伸部的掺杂剂扩散。实施例包括使用栅电极作为掩模离子注入诸如B或BF 2的P型掺杂剂，以形成浅源极/漏极延伸部，沉积共形氧化物衬垫，以及将P型杂质注入氧化物衬垫在与浅源极/漏极延伸部分基本上相同的掺杂剂浓度下。随后的处理包括沉积间隔层，蚀刻以形成侧壁间隔物，离子注入以形成深度中等或重的源/漏植入物和活化退火。

3. 发明授权

US08350253B1 Integrated circuit with stress inserts 有权
标题翻译：集成电路与应力插入
公开(公告)号：US08350253B1
公开(公告)日：2013-01-08
申请号：US12697027
申请日：2010-01-29
申请人： Bei Zhu , Hong-Tze Pan , Bang-Thu Nguyen , Qi Lin , Zhiyuan Wu , Ping-Chin Yeh , Jae-Gyung Ahn , Yun Wu
发明人： Bei Zhu , Hong-Tze Pan , Bang-Thu Nguyen , Qi Lin , Zhiyuan Wu , Ping-Chin Yeh , Jae-Gyung Ahn , Yun Wu
IPC分类号： H01L29/06
CPC分类号： H01L29/66636 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/6653 , H01L29/7848
摘要： An integrated circuit (“IC”) fabricated on a semiconductor substrate has an active gate structure formed over a channel region in the semiconductor substrate. A dummy gate structure is formed on a dielectric isolation structure. The dummy gate structure and the active gate structure have the same width. A sidewall spacer on the dummy gate structure overlies a semiconductor portion between a strain-inducing insert and the dielectric isolation structure.
摘要翻译：在半导体衬底上制造的集成电路（IC）具有形成在半导体衬底中的沟道区上的有源栅极结构。在绝缘隔离结构上形成虚拟栅极结构。虚拟栅极结构和有源栅极结构具有相同的宽度。虚拟栅极结构上的侧壁间隔物覆盖在应变诱导插入件和介电隔离结构之间的半导体部分。

4. 发明授权

US07211473B1 Method and structure for controlling floating body effects 有权
标题翻译：控制浮体效应的方法和结构
公开(公告)号：US07211473B1
公开(公告)日：2007-05-01
申请号：US10756585
申请日：2004-01-12
申请人： Mario M. Pelella , William George En , Ping-Chin Yeh
发明人： Mario M. Pelella , William George En , Ping-Chin Yeh
IPC分类号： H01L21/00
CPC分类号： H01L29/78612 , H01L29/66772
摘要： A method for forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate adjacent the gate. A facet is formed in at least one of the source/drain junctions of the integrated circuit.
摘要翻译：提供了一种用于形成具有半导体衬底的集成电路的方法。在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。源极/漏极结形成在与栅极相邻的半导体衬底中。在集成电路的源极/漏极结中的至少一个上形成刻面。

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