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1. 发明授权

US08350253B1 Integrated circuit with stress inserts 有权
标题翻译：集成电路与应力插入
公开(公告)号：US08350253B1
公开(公告)日：2013-01-08
申请号：US12697027
申请日：2010-01-29
申请人： Bei Zhu , Hong-Tze Pan , Bang-Thu Nguyen , Qi Lin , Zhiyuan Wu , Ping-Chin Yeh , Jae-Gyung Ahn , Yun Wu
发明人： Bei Zhu , Hong-Tze Pan , Bang-Thu Nguyen , Qi Lin , Zhiyuan Wu , Ping-Chin Yeh , Jae-Gyung Ahn , Yun Wu
IPC分类号： H01L29/06
CPC分类号： H01L29/66636 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/6653 , H01L29/7848
摘要： An integrated circuit (“IC”) fabricated on a semiconductor substrate has an active gate structure formed over a channel region in the semiconductor substrate. A dummy gate structure is formed on a dielectric isolation structure. The dummy gate structure and the active gate structure have the same width. A sidewall spacer on the dummy gate structure overlies a semiconductor portion between a strain-inducing insert and the dielectric isolation structure.
摘要翻译：在半导体衬底上制造的集成电路（IC）具有形成在半导体衬底中的沟道区上的有源栅极结构。在绝缘隔离结构上形成虚拟栅极结构。虚拟栅极结构和有源栅极结构具有相同的宽度。虚拟栅极结构上的侧壁间隔物覆盖在应变诱导插入件和介电隔离结构之间的半导体部分。

2. 发明授权

US08329568B1 Semiconductor device and method for making the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08329568B1
公开(公告)日：2012-12-11
申请号：US12772969
申请日：2010-05-03
申请人： Jae-Gyung Ahn , Myongseob Kim , Ping-Chin Yeh , Zhiyuan Wu , John Cooksey
发明人： Jae-Gyung Ahn , Myongseob Kim , Ping-Chin Yeh , Zhiyuan Wu , John Cooksey
IPC分类号： H01L21/425
CPC分类号： H01L29/665 , H01L29/6656 , H01L29/78 , H01L29/7843 , H01L29/7848
摘要： In one embodiment of the present invention, a field effect transistor device is provided. The field effect transistor device comprises an active area, including a first semiconductor material of a first conductivity type. A channel region is included within the active area. A gate region overlays the channel region, and the first source/drain region and the second source/drain region are embedded in the active area and spaced from each other by the channel region. The first source/drain region and the second source/drain region each include a second semiconductor material of a second conductivity type opposite of the first conductivity type. A well-tap region is embedded in the active area and spaced from the first source/drain region by the channel region and the second source/drain region. The well-tap region includes the second semiconductor material of the first conductivity type. The first source/drain region and the second source/drain region and the well-tap region are epitaxial deposits.
摘要翻译：在本发明的一个实施例中，提供了场效应晶体管器件。场效应晶体管器件包括有源区，包括第一导电类型的第一半导体材料。通道区域包括在有效区域内。栅极区域覆盖沟道区域，并且第一源极/漏极区域和第二源极/漏极区域被嵌入有源区域中并且被沟道区域彼此间隔开。第一源极/漏极区域和第二源极/漏极区域各自包括与第一导电类型相反的第二导电类型的第二半导体材料。阱区域嵌入有源区域中，并且通过沟道区域和第二源极/漏极区域与第一源极/漏极区域间隔开。阱抽头区域包括第一导电类型的第二半导体材料。第一源极/漏极区域和第二源极/漏极区域以及阱阱区域是外延沉积物。

3. 发明授权

US07956385B1 Circuit for protecting a transistor during the manufacture of an integrated circuit device 有权
标题翻译：用于在制造集成电路器件期间保护晶体管的电路
公开(公告)号：US07956385B1
公开(公告)日：2011-06-07
申请号：US12847957
申请日：2010-07-30
申请人： Yuhao Luo , Shuxian Wu , Xin X. Wu , Jae-Gyung Ahn , Deepak K. Nayak , Daniel Gitlin
发明人： Yuhao Luo , Shuxian Wu , Xin X. Wu , Jae-Gyung Ahn , Deepak K. Nayak , Daniel Gitlin
IPC分类号： H01L23/525
CPC分类号： H01L27/0251
摘要： A circuit for protecting a transistor during the manufacture of an integrated circuit device is disclosed. The circuit comprises a transistor having a gate formed over an active region formed in a die of the integrated circuit device; a protection element formed in the die of the integrated circuit device; and a programmable interconnect coupled between the gate of the transistor and the protection element, the programmable interconnect enabling the protection element to be decoupled from the transistor.
摘要翻译：公开了一种用于在制造集成电路器件期间保护晶体管的电路。该电路包括晶体管，其晶体管具有形成在集成电路器件的管芯中的有源区上的栅极; 形成在集成电路器件的管芯中的保护元件; 以及耦合在所述晶体管的栅极和所述保护元件之间的可编程互连，所述可编程互连使得所述保护元件能够与所述晶体管分离。

4. 发明授权

US06518135B1 Method for forming localized halo implant regions 失效
标题翻译：形成局部晕圈植入区的方法
公开(公告)号：US06518135B1
公开(公告)日：2003-02-11
申请号：US09961484
申请日：2001-09-24
申请人： Jae-Gyung Ahn
发明人： Jae-Gyung Ahn
IPC分类号： H01L21336
CPC分类号： H01L29/66492 , H01L21/26586 , H01L29/41783
摘要： A method for forming a localized halo implant region, comprises: implanting a first dosage of ions of a first type toward a surface of a substrate having a gate electrode formed thereon, so as to form a lightly doped region adjacent to the gate electrode; forming a disposable spacer on a sidewall of the gate electrode; forming an elevated source/drain structure adjacent to the disposable spacer; implanting a second dosage of ions of the first type toward the surface of the substrate so as to form a heavily doped region adjacent to the disposable spacer; removing the disposable spacer; and tilt-angle implanting at least one dosage of ions of a second type toward a gap created by the disposable spacer having been removed so as to form a localized halo implant region in the substrate, preferably by utilizing shadow effects of the gate electrode and the elevated source/drain structure.
摘要翻译：一种用于形成局部晕圈注入区域的方法，包括：将第一类型离子的第一剂量注入到其上形成有栅电极的衬底的表面上，以形成与栅电极相邻的轻掺杂区域; 在所述栅电极的侧壁上形成一次性间隔件; 形成与所述一次性间隔件相邻的升高的源极/漏极结构; 将第一类型的离子的第二剂量植入衬底的表面，以便形成与一次性衬垫相邻的重掺杂区域; 去除一次性间隔件; 并且倾斜角度将至少一次剂量的第二类型的离子注入由已被去除的一次性间隔物产生的间隙，以在衬底中形成局部的晕圈注入区域，优选地通过利用栅电极和源/排水结构较高。

5. 发明授权

US06730572B2 Method of forming silicide 有权
标题翻译：形成硅化物的方法
公开(公告)号：US06730572B2
公开(公告)日：2004-05-04
申请号：US10347230
申请日：2003-01-21
申请人： Key-Min Lee , Jae-Gyung Ahn
发明人： Key-Min Lee , Jae-Gyung Ahn
IPC分类号： H01L21331
CPC分类号： H01L21/823842 , H01L21/28052 , H01L21/823835
摘要： A method of forming silicide, especially in a CMOS device in which polysilicon grains in a p-type gate are re-doped with n-type impurities such as As and the like at a critical implantation dose. This increases the grain size of the polysilicon, which also reduces sheet resistance by securing thermal stability in subsequent process steps thereof. The present invention generally includes forming an undoped polysilicon layer, doping the polysilicon layer with p-type impurity ions, doping the p-doped polysilicon layer with ions that increase the grain size of the polysilicon layer by being heated, forming a metal layer on the twice-doped polysilicon layer, and forming a silicide layer by reacting a portion of the twice-doped polysilicon layer with the metal layer.
摘要翻译：一种形成硅化物的方法，特别是在其中p型栅极中的多晶硅晶粒以临界注入剂量重新掺杂诸如As等的n型杂质的CMOS器件中。这增加了多晶硅的晶粒尺寸，这也通过在其随后的工艺步骤中确保热稳定性而降低了薄层电阻。本发明通常包括形成未掺杂的多晶硅层，用p型杂质离子掺杂多晶硅层，用掺杂p掺杂多晶硅层的离子掺杂，所述离子通过加热而增加多晶硅层的晶粒尺寸，在双掺杂多晶硅层，并且通过使二掺杂多晶硅层的一部分与金属层反应而形成硅化物层。

6. 发明授权

US06528381B2 Method of forming silicide 有权
公开(公告)号：US06528381B2
公开(公告)日：2003-03-04
申请号：US09770449
申请日：2001-01-29
申请人： Key-Min Lee , Jae-Gyung Ahn
发明人： Key-Min Lee , Jae-Gyung Ahn
IPC分类号： H01L21331
CPC分类号： H01L21/823842 , H01L21/28052 , H01L21/823835
摘要： A method of forming silicide, especially in a CMOS device in which polysilicon grains in a p-type gate are re-doped with n-type impurities such as As and the like at a critical implantation dose. This increases the grain size of the polysilicon, which also reduces sheet resistance by securing thermal stability in subsequent process steps thereof. The present invention generally includes forming an undoped polysilicon layer, doping the polysilicon layer with p-type impurity ions, doping the p-doped polysilicon layer with ions that increase the grain size of the polysilicon layer by being heated, forming a metal layer on the twice-doped polysilicon layer, and forming a silicide layer by reacting a portion of the twice-doped polysilicon layer with the metal layer.

7. 发明授权

US06337254B1 Method of forming trench isolation structure with dummy active regions and overlying discriminately doped conduction layer 有权
标题翻译：形成具有虚拟有源区和覆盖区分掺杂导电层的沟槽隔离结构的方法
公开(公告)号：US06337254B1
公开(公告)日：2002-01-08
申请号：US09286670
申请日：1999-04-06
申请人： Jae-Gyung Ahn
发明人： Jae-Gyung Ahn
IPC分类号： H01L2176
CPC分类号： H01L21/765 , H01L21/76224
摘要： A device isolation structure and a method thereof including a semiconductor substrate wherein a field isolation region including a plurality of dummy active regions and an active region are defined, a plurality of trenches formed among the regions, a filling layer filled in the plurality of trenches, a gate insulation layer formed on the semiconductor substrate having the filling layer, and a second conduction layer formed on the gate insulation layer, is capable of preventing a dishing from being generated in etching by forming the plurality of dummy active regions in the field isolation region and basically preventing the wide trenches from being formed, minimizing a parasitic capacitance generated in the dummy active-gate insulation layer-gate insulation layer in the field isolation region, and simplifying an isolation process by using the dummy active pattern.
摘要翻译：一种器件隔离结构及其方法，包括：半导体衬底，其中限定包括多个虚设有源区和有源区的场隔离区，在所述区之间形成多个沟槽，填充层填充在所述多个沟槽中，在具有填充层的半导体衬底上形成的栅极绝缘层和形成在栅极绝缘层上的第二导电层能够通过在场隔离区域中形成多个虚拟有源区域来防止在蚀刻中产生凹陷并且基本上防止形成宽沟槽，使得在场隔离区域中的伪有源栅极绝缘层 - 栅极绝缘层中产生的寄生电容最小化，并且通过使用伪有源图案来简化隔离处理。

8. 发明授权

US6110771A Fabrication method of a semiconductor device using self-aligned silicide CMOS having a dummy gate electrode 有权
标题翻译：使用具有伪栅电极的自对准硅化物CMOS的半导体器件的制造方法
公开(公告)号：US6110771A
公开(公告)日：2000-08-29
申请号：US335048
申请日：1999-06-16
申请人： Jae-Gyung Ahn
发明人： Jae-Gyung Ahn
IPC分类号： H01L21/8238
CPC分类号： H01L21/823835
摘要： A semiconductor device and a fabrication method therefor improve electrostatic discharge (ESD) protecting property of an ESD protecting device in a fabrication method of a semiconductor device using a self-aligned silicide CMOS process. The semiconductor device has a silicide blocking portion which prevents a self-aligned silicified reaction by forming a gate electrode on drain and/or source of an ESD protecting device and simultaneously forming a dummy gate electrode which is separated from the gate electrode.
摘要翻译：一种使用自对准硅化物CMOS工艺的半导体器件制造方法中的ESD保护器件的静电放电（ESD）保护性的半导体器件及其制造方法。半导体器件具有硅化物阻挡部分，其通过在ESD保护器件的漏极和/或源极上形成栅电极并同时形成与栅电极分离的虚拟栅极电极来防止自对准的硅化反应。

9. 发明授权

US08354671B1 Integrated circuit with adaptive VGG setting 有权
标题翻译：具有自适应VGG设置的集成电路
公开(公告)号：US08354671B1
公开(公告)日：2013-01-15
申请号：US12781627
申请日：2010-05-17
申请人： Hsung Jai Im , Henley Liu , Jae-Gyung Ahn , Tony Le , Patrick J. Crotty
发明人： Hsung Jai Im , Henley Liu , Jae-Gyung Ahn , Tony Le , Patrick J. Crotty
IPC分类号： H01L23/58 , H01L29/10 , H01L21/66 , G01R31/26 , G01N27/00
CPC分类号： H01L22/34 , H01L29/42364
摘要： A technique for setting Vgg in an IC is disclosed. The technique includes specifying a design reliability lifetime for the IC, and a relationship between maximum gate bias and gate dielectric thickness for the IC sufficient to achieve the design reliability lifetime is established. The IC is fabricated and the gate dielectric thickness is measured. A maximum gate bias voltage is determined according to the gate dielectric thickness and the relationship between maximum gate bias and gate dielectric thickness, and a Vgg trim circuit of the IC is set to provide Vgg having the maximum gate bias voltage that will achieve the design reliability lifetime according to the measured gate dielectric thickness.
摘要翻译：公开了一种在IC中设置Vgg的技术。该技术包括指定IC的设计可靠性寿命，并建立足以实现设计可靠性寿命的IC的最大栅极偏置和栅极电介质厚度之间的关系。制造IC并测量栅介质厚度。根据栅极介电厚度和最大栅极偏置与栅极介质厚度之间的关系确定最大栅极偏置电压，并且设置IC的Vgg微调电路以提供具有最大栅极偏置电压的Vgg，其将实现设计可靠性根据测量的栅极介电厚度的寿命。

10. 发明申请

US20120229203A1 CALIBRATING DEVICE PERFORMANCE WITHIN AN INTEGRATED CIRCUIT 有权
标题翻译：在集成电路中校准器件性能
公开(公告)号：US20120229203A1
公开(公告)日：2012-09-13
申请号：US13042122
申请日：2011-03-07
申请人： Sharmin Sadoughi , Jae-Gyung Ahn
发明人： Sharmin Sadoughi , Jae-Gyung Ahn
IPC分类号： H03H2/00
CPC分类号： H03K17/18 , H01L22/22 , H01L2924/0002 , H03K17/12 , H01L2924/00
摘要： A multi-fingered device can be calibrated for performance. The multi-fingered device can include a first finger configured to remain active and a second finger that is initially deactivated concurrent with the first finger being active. A measure of degradation for the multi-fingered device within an IC can be determined. The measure of degradation can be compared with a degradation threshold. Responsive to determining that the measure of degradation meets the degradation threshold, a finger of the multi-fingered device can be activated.
摘要翻译：可以根据性能对多指装置进行校准。多指装置可以包括被配置为保持活动的第一手指和最初与第一手指同时激活的第二手指有效。可以确定IC内的多指装置的劣化度量。降解的量度可以与降解阈值进行比较。响应于确定降解度量达到降解阈值，可以激活多指装置的手指。

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