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1. 发明授权

US08302064B1 Method of product performance improvement by selective feature sizing of semiconductor devices 有权
标题翻译：通过半导体器件的选择特征尺寸来改善产品性能的方法
公开(公告)号：US08302064B1
公开(公告)日：2012-10-30
申请号：US12401450
申请日：2009-03-10
申请人： Sharmin Sadoughi , Prabhuram Gopalan , Michael J. Hart , John Cooksey , Zhiyuan Wu
发明人： Sharmin Sadoughi , Prabhuram Gopalan , Michael J. Hart , John Cooksey , Zhiyuan Wu
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5072
摘要： Device features, such as gate lengths and channel widths, are selectively altered by first identifying those devices within a semiconductor die that exhibit physical attributes, e.g., leakage current and threshold voltage magnitude, that are different than previously verified by a design/simulation tool used to design the devices. The identified, non-conforming devices are then further identified by the amount of deviation from the original design goal that is exhibited by each non-conforming device. The non-conforming devices are then mathematically categorized into bins, where each bin is tagged with a magnitude of deviation from a design goal. The mask layers defining the features of the non-conforming devices are then selectively modified by an amount that is commensurate with the tagged deviation. The selectively modified mask layers are then used to generate a new semiconductor die that exhibits improved performance.
摘要翻译：选择性地改变诸如栅极长度和沟道宽度的器件特征，首先识别半导体管芯内的这些器件，其显示物理属性，例如泄漏电流和阈值电压幅度，其不同于先前使用的设计/仿真工具验证设计设备。然后，通过与每个不合格设备展示的原始设计目标的偏差量进一步识别所识别的不合格设备。然后将不合格的设备数学分类成箱体，其中每个箱体标记有与设计目标的偏差幅度。然后，限定不合格装置的特征的掩模层被选择性地修改与标记偏差相当的量。然后使用选择性修改的掩模层来产生表现出改善的性能的新的半导体管芯。

2. 发明授权

US07256087B1 Techniques for improving negative bias temperature instability (NBTI) lifetime of field effect transistors 有权
标题翻译：改善场效应晶体管负偏压温度不稳定性（NBTI）寿命的技术
公开(公告)号：US07256087B1
公开(公告)日：2007-08-14
申请号：US11018422
申请日：2004-12-21
申请人： Sharmin Sadoughi , Krishnaswamy Ramkumar , Ravindra Kapre , Igor Polishchuk , Maroun Khoury
发明人： Sharmin Sadoughi , Krishnaswamy Ramkumar , Ravindra Kapre , Igor Polishchuk , Maroun Khoury
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823842
摘要： In one embodiment, an integrated circuit includes a PMOS transistor having a gate stack comprising a P+ doped gate polysilicon layer and a nitrided gate oxide (NGOX) layer. The NGOX layer may be over a silicon substrate. The integrated circuit further includes an interconnect line formed over the transistor. The interconnect line includes a hydrogen getter material and may comprise a single material or stack of materials. The interconnect line advantageously getters hydrogen (e.g., H2 or H2O) that would otherwise be trapped in the NGOX layer/silicon substrate interface, thereby improving the negative bias temperature instability (NBTI) lifetime of the transistor.
摘要翻译：在一个实施例中，集成电路包括具有包括P +掺杂栅极多晶硅层和氮化栅极氧化物（NGOX）层的栅极堆叠的PMOS晶体管。 NGOX层可以在硅衬底之上。集成电路还包括形成在晶体管上的互连线。互连线包括吸氢材料，并且可以包括单一材料或材料堆。互连线有利地吸收否则将被捕获在NGOX层/硅衬底界面中的氢（例如，H 2 H 2或H 2 O 2），从而提高负偏压温度晶体管的不稳定性（NBTI）寿命。

3. 发明授权

US6033991A Isolation scheme based on recessed locos using a sloped Si etch and dry field oxidation 失效
标题翻译：基于使用倾斜Si蚀刻和干场氧化的凹陷区域的隔离方案
公开(公告)号：US6033991A
公开(公告)日：2000-03-07
申请号：US939838
申请日：1997-09-29
申请人： Krishnaswamy Ramkumar , Pamela Trammel , Sharmin Sadoughi
发明人： Krishnaswamy Ramkumar , Pamela Trammel , Sharmin Sadoughi
IPC分类号： H01L21/3065 , H01L21/311 , H01L21/316 , H01L21/762 , H01L21/302
CPC分类号： H01L21/76202 , H01L21/7621 , H01L21/3065 , H01L21/31116 , H01L21/31662
摘要： A method of forming a field oxide or an isolation region in a semiconductor die. An oxidation mask layer (over an oxide layer disposed over the substrate) is patterned and subsequently etched, preferably so that the oxidation mask layer may have a nearly vertical sidewall. The oxide layer and the substrate in the isolation region are etched to form a recess in the substrate having a sloped surface with respect to the sidewall of the oxidation mask layer. A field oxide is then grown in the recess using a dry oxidizing atmosphere. The sloped sidewall of the substrate recess effectively moves the face of the exposed substrate away from the edge of the oxidation mask layer sidewall. Compared to non-sloped techniques, the oxidation appears to start with a built-in offset from the patterned etch. This leads to a reduction of oxide encroachment and less field oxide thinning. The preferred range of slopes for the substrate sidewall is from approximately 10.degree. to 40.degree. with respect to the oxidation mask layer sidewall.
摘要翻译：在半导体管芯中形成场氧化物或隔离区域的方法。对氧化掩模层（位于衬底上方的氧化物层上方）进行构图并随后进行蚀刻，优选地使得氧化掩模层可具有几乎垂直的侧壁。蚀刻隔离区域中的氧化物层和衬底，以在衬底中形成相对于氧化掩模层的侧壁具有倾斜表面的凹部。然后使用干燥的氧化气氛将场氧化物生长在凹槽中。衬底凹槽的倾斜侧壁有效地将暴露的衬底的表面远离氧化掩模层侧壁的边缘移动。与非倾斜技术相比，氧化似乎从图案化蚀刻的内置偏移开始。这导致氧化物侵蚀减少和较少的场氧化物稀化。衬底侧壁的斜率的优选范围相对于氧化掩模层侧壁约为10°至40°。

4. 发明授权

US07629653B1 Techniques for improving negative bias temperature instability (NBTI) lifetime of field effect transistors 有权
标题翻译：改善场效应晶体管负偏压温度不稳定性（NBTI）寿命的技术
公开(公告)号：US07629653B1
公开(公告)日：2009-12-08
申请号：US11827765
申请日：2007-07-13
申请人： Sharmin Sadoughi , Krishnaswamy Ramkumar , Ravindra Kapre , Igor Polishchuk , Maroun Khoury
发明人： Sharmin Sadoughi , Krishnaswamy Ramkumar , Ravindra Kapre , Igor Polishchuk , Maroun Khoury
IPC分类号： H01L29/78
CPC分类号： H01L21/823857 , H01L21/823842
摘要： In one embodiment, an integrated circuit includes a PMOS transistor having a gate stack comprising a P+ doped gate polysilicon layer and a nitrided gate oxide (NGOX) layer. The NGOX layer may be over a silicon substrate. The integrated circuit further includes an interconnect line formed over the transistor. The interconnect line includes a hydrogen getter material and may comprise a single material or stack of materials. The interconnect line advantageously getters hydrogen (e.g., H2 or H2O) that would otherwise be trapped in the NGOX layer/silicon substrate interface, thereby improving the negative bias temperature instability (NBTI) lifetime of the transistor.
摘要翻译：在一个实施例中，集成电路包括具有包括P +掺杂栅极多晶硅层和氮化栅极氧化物（NGOX）层的栅极堆叠的PMOS晶体管。 NGOX层可以在硅衬底之上。集成电路还包括形成在晶体管上的互连线。互连线包括吸氢材料，并且可以包括单一材料或材料堆。互连线有利地吸收否则将被捕获在NGOX层/硅衬底界面中的氢（例如，H 2或H 2 O），从而改善晶体管的负偏压温度不稳定性（NBTI）寿命。

5. 发明授权

US07192839B1 Semiconductor structure having alignment marks with shallow trench isolation 有权
标题翻译：半导体结构具有浅沟槽隔离的对准标记
公开(公告)号：US07192839B1
公开(公告)日：2007-03-20
申请号：US10848638
申请日：2004-05-19
申请人： Krishnaswamy Ramkumar , Sharmin Sadoughi
发明人： Krishnaswamy Ramkumar , Sharmin Sadoughi
IPC分类号： H01L23/544
CPC分类号： H01L21/76229 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure including a semiconductor substrate, an isolation trench in the semiconductor substrate, and an alignment trench in the semiconductor substrate is disclosed. The structure also includes a dielectric layer and a metallic layer. The dielectric layer is on the semiconductor substrate and in both the isolation trench and the alignment trench. The dielectric layer fills the isolation trench and does not fill the alignment trench. The metallic layer is on the dielectric layer.
摘要翻译：公开了一种包括半导体衬底，半导体衬底中的隔离沟槽和半导体衬底中的对准沟槽的半导体结构。该结构还包括电介质层和金属层。介电层位于半导体衬底上并且在隔离沟槽和对准沟槽中。电介质层填充隔离沟槽并且不填充对准沟槽。金属层位于电介质层上。

6. 发明授权

US06713831B1 Borderless contact architecture 有权
标题翻译：无边界联络体系
公开(公告)号：US06713831B1
公开(公告)日：2004-03-30
申请号：US10010837
申请日：2001-12-04
申请人： Sharmin Sadoughi , Mira Ben-Tzur , Michal E. Fastow , Saurabh Dutta Chowdhury
发明人： Sharmin Sadoughi , Mira Ben-Tzur , Michal E. Fastow , Saurabh Dutta Chowdhury
IPC分类号： H01L310232
CPC分类号： H01L21/76829 , H01L21/0276 , H01L21/31144 , H01L21/3212 , H01L21/76897 , H01L23/5226 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method and a system are provided for forming a borderless contact structure. In particular, a method is provided which includes using an inorganic anti-reflective coating layer as an etch stop to form a borderless contact structure. In some embodiments, the method may include patterning an interconnect line above an inorganic layer with anti-reflective properties and depositing an upper interlevel dielectric layer above the interconnect line. A trench may then be etched within the upper interlevel dielectric layer such that a borderless contact structure may be formed in contact with said interconnect line. Consequently, a semiconductor topography is provided, in such an embodiment, which includes an inorganic anti-reflective coating layer arranged below an interconnect line and a contact structure arranged upon the interconnect line. In some embodiments, a width of the contact structure may be greater than a width of the interconnect line.
摘要翻译：提供了一种用于形成无边界接触结构的方法和系统。特别地，提供了一种方法，其包括使用无机抗反射涂层作为蚀刻停止物以形成无边界接触结构。在一些实施例中，该方法可以包括以具有抗反射特性的方式对无机层上方的互连线进行图案化，并且在互连线上方沉积上部层间电介质层。然后可以在上层间介质层内蚀刻沟槽，使得可以形成与所述互连线接触的无边界接触结构。因此，在这样的实施例中，提供半导体形貌，其包括布置在互连线下方的无机抗反射涂层和布置在互连线上的接触结构。在一些实施例中，接触结构的宽度可以大于互连线的宽度。

7. 发明申请

US20120229203A1 CALIBRATING DEVICE PERFORMANCE WITHIN AN INTEGRATED CIRCUIT 有权
标题翻译：在集成电路中校准器件性能
公开(公告)号：US20120229203A1
公开(公告)日：2012-09-13
申请号：US13042122
申请日：2011-03-07
申请人： Sharmin Sadoughi , Jae-Gyung Ahn
发明人： Sharmin Sadoughi , Jae-Gyung Ahn
IPC分类号： H03H2/00
CPC分类号： H03K17/18 , H01L22/22 , H01L2924/0002 , H03K17/12 , H01L2924/00
摘要： A multi-fingered device can be calibrated for performance. The multi-fingered device can include a first finger configured to remain active and a second finger that is initially deactivated concurrent with the first finger being active. A measure of degradation for the multi-fingered device within an IC can be determined. The measure of degradation can be compared with a degradation threshold. Responsive to determining that the measure of degradation meets the degradation threshold, a finger of the multi-fingered device can be activated.
摘要翻译：可以根据性能对多指装置进行校准。多指装置可以包括被配置为保持活动的第一手指和最初与第一手指同时激活的第二手指有效。可以确定IC内的多指装置的劣化度量。降解的量度可以与降解阈值进行比较。响应于确定降解度量达到降解阈值，可以激活多指装置的手指。

8. 发明授权

US08183105B2 Integrated circuit device with stress reduction layer 有权
标题翻译：具减压层的集成电路装置
公开(公告)号：US08183105B2
公开(公告)日：2012-05-22
申请号：US13228884
申请日：2011-09-09
申请人： Sharmin Sadoughi
发明人： Sharmin Sadoughi
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L22/20 , H01L29/7843
摘要： An integrated circuit device is disclosed that includes a dual stress liner NMOS device having a tensile stress layer that overlies a NMOS gate film stack, a dual stress liner PMOS device having a compressive stress layer that overlies a PMOS gate film stack, a reduced-stress dual stress liner NMOS device having a stress reduction layer that extends between the tensile stress layer and the NMOS gate film stack, and a reduced-stress dual stress liner PMOS device having a stress reduction layer that extends between the compressive stress layer and the PMOS gate film stack. In embodiments of the invention additional reduced-stress dual stress liner NMOS devices and reduced-stress PMOS devices are formed by altering the thickness and/or the material properties of the stress reduction layer.
摘要翻译：公开了一种集成电路器件，其包括具有覆盖在NMOS栅极膜堆叠上的拉伸应力层的双重应力衬底NMOS器件，具有覆盖在PMOS栅极膜堆叠上的压应力层的双应力衬底PMOS器件，具有在拉伸应力层和NMOS栅极膜叠层之间延伸的应力减小层的双应力衬垫NMOS器件，以及具有在压应力层和PMOS栅极之间延伸的应力减小层的应力减小的双应力衬垫PMOS器件电影堆在本发明的实施例中，通过改变应力降低层的厚度和/或材料性质来形成附加的还原应力双应力衬底NMOS器件和还原应力PMOS器件。

9. 发明授权

US06399462B1 Method and structure for isolating integrated circuit components and/or semiconductor active devices 失效
标题翻译：用于隔离集成电路部件和/或半导体有源器件的方法和结构
公开(公告)号：US06399462B1
公开(公告)日：2002-06-04
申请号：US08885046
申请日：1997-06-30
申请人： Krishnaswamy Ramkumar , Sang S. Kim , Sharmin Sadoughi , Pamela Trammel , Avner Shelem
发明人： Krishnaswamy Ramkumar , Sang S. Kim , Sharmin Sadoughi , Pamela Trammel , Avner Shelem
IPC分类号： H01L2176
CPC分类号： H01L21/7621
摘要： A method of forming a field oxide or isolation region in a semiconductor die. A nitride layer (over an oxide layer disposed over a substrate) is patterned and subsequently etched so that the nitride layer has a nearly vertical sidewall. The oxide layer and the substrate in the isolation region are etched to form a recess in the substrate having a sloped surface with respect to the nearly vertical sidewall of the nitride layer. A field oxide is then grown in the recess using a high pressure, dry oxidizing atmosphere. The sloped sidewall of the substrate effectively moves the face of the exposed substrate away from the edge of the nitride layer sidewall. Compared to non-sloped techniques, the oxidation appears to start with a built-in offset from the patterned etch. This leads to a reduction of oxide encroachment and a nearly non-existent bird's beak. The desirable range of slopes for the substrate sidewall is approximately 50°-80° with respect to a nearly planar surface of the substrate in the recess.
摘要翻译：一种在半导体管芯中形成场氧化物或隔离区域的方法。对氮化物层（在衬底上方的氧化物层上方）进行构图并随后进行蚀刻，使得氮化物层具有几乎垂直的侧壁。蚀刻隔离区域中的氧化物层和衬底，以在衬底中形成相对于氮化物层的几乎垂直侧壁具有倾斜表面的凹部。然后使用高压，干燥的氧化气氛将场氧化物生长在凹陷中。衬底的倾斜侧壁有效地将暴露的衬底的表面远离氮化物层侧壁的边缘移动。与非倾斜技术相比，氧化似乎从图案化蚀刻的内置偏移开始。这导致氧化物侵蚀的减少和几乎不存在的鸟的喙。相对于凹部中的基板的几乎平坦的表面，衬底侧壁的期望的斜率范围大约为50°-80°。

10. 发明授权

US08035166B2 Integrated circuit device with stress reduction layer 有权
标题翻译：具减压层的集成电路装置
公开(公告)号：US08035166B2
公开(公告)日：2011-10-11
申请号：US12420672
申请日：2009-04-08
申请人： Sharmin Sadoughi
发明人： Sharmin Sadoughi
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823807 , H01L22/20 , H01L29/7843
摘要： An integrated circuit device is disclosed that includes a dual stress liner NMOS device having a tensile stress layer that overlies a NMOS gate film stack, a dual stress liner PMOS device having a compressive stress layer that overlies a PMOS gate film stack, a reduced-stress dual stress liner NMOS device having a stress reduction layer that extends between the tensile stress layer and the NMOS gate film stack, and a reduced-stress dual stress liner PMOS device having a stress reduction layer that extends between the compressive stress layer and the PMOS gate film stack. In embodiments of the invention additional reduced-stress dual stress liner NMOS devices and reduced-stress PMOS devices are formed by altering the thickness and/or the material properties of the stress reduction layer.
摘要翻译：公开了一种集成电路器件，其包括具有覆盖在NMOS栅极膜堆叠上的拉伸应力层的双重应力衬底NMOS器件，具有覆盖在PMOS栅极膜堆叠上的压应力层的双应力衬底PMOS器件，具有在拉伸应力层和NMOS栅极膜叠层之间延伸的应力减小层的双应力衬垫NMOS器件，以及具有在压应力层和PMOS栅极之间延伸的应力减小层的应力减小的双应力衬垫PMOS器件电影堆在本发明的实施例中，通过改变应力降低层的厚度和/或材料性质来形成附加的还原应力双应力衬底NMOS器件和还原应力PMOS器件。

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