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1. 发明授权

US08350253B1 Integrated circuit with stress inserts 有权
标题翻译：集成电路与应力插入
公开(公告)号：US08350253B1
公开(公告)日：2013-01-08
申请号：US12697027
申请日：2010-01-29
申请人： Bei Zhu , Hong-Tze Pan , Bang-Thu Nguyen , Qi Lin , Zhiyuan Wu , Ping-Chin Yeh , Jae-Gyung Ahn , Yun Wu
发明人： Bei Zhu , Hong-Tze Pan , Bang-Thu Nguyen , Qi Lin , Zhiyuan Wu , Ping-Chin Yeh , Jae-Gyung Ahn , Yun Wu
IPC分类号： H01L29/06
CPC分类号： H01L29/66636 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/6653 , H01L29/7848
摘要： An integrated circuit (“IC”) fabricated on a semiconductor substrate has an active gate structure formed over a channel region in the semiconductor substrate. A dummy gate structure is formed on a dielectric isolation structure. The dummy gate structure and the active gate structure have the same width. A sidewall spacer on the dummy gate structure overlies a semiconductor portion between a strain-inducing insert and the dielectric isolation structure.
摘要翻译：在半导体衬底上制造的集成电路（IC）具有形成在半导体衬底中的沟道区上的有源栅极结构。在绝缘隔离结构上形成虚拟栅极结构。虚拟栅极结构和有源栅极结构具有相同的宽度。虚拟栅极结构上的侧壁间隔物覆盖在应变诱导插入件和介电隔离结构之间的半导体部分。

2. 发明授权

US08890164B1 Apparatus and method for reducing plasma-induced damage in pMOSFETS 有权
标题翻译：用于降低pMOSFETS中等离子体诱导的损伤的装置和方法
公开(公告)号：US08890164B1
公开(公告)日：2014-11-18
申请号：US13416297
申请日：2012-03-09
申请人： Hong-Tsz Pan , Qi Lin , Yun Wu , Bang-Thu Nguyen
发明人： Hong-Tsz Pan , Qi Lin , Yun Wu , Bang-Thu Nguyen
IPC分类号： H01L27/108
CPC分类号： H01L27/0928 , H01L21/823493 , H01L21/823892 , H01L27/0255 , H01L27/088
摘要： A metal oxide semiconductor field effect transistor (MOSFET) for an integrated circuit includes a substrate of a first conductivity type, a first well region of a second conductivity type located in the substrate, and a second well region of the second conductivity type located within the substrate. The second well region is functionally connected to the first well region, and the second well region has a surface area greater than a surface area of the first well region. The MOSFET further includes a source of the first conductivity type located in the first well region, a drain of the first conductivity type located in the first well region, a substrate terminal of the second conductivity type located in the first well region, a gate oxide on a top surface of the first well region, and a gate electrode located on a top surface of the gate oxide.
摘要翻译：用于集成电路的金属氧化物半导体场效应晶体管（MOSFET）包括第一导电类型的衬底，位于衬底中的第二导电类型的第一阱区和位于衬底内的第二导电类型的第二阱区基质。第二阱区域功能上连接到第一阱区域，并且第二阱区域具有大于第一阱区域的表面积的表面积。 MOSFET还包括位于第一阱区域中的第一导电类型的源极，位于第一阱区域中的第一导电类型的漏极，位于第一阱区域中的第二导电类型的衬底端子，栅极氧化物在第一阱区的顶表面上，以及栅电极，位于栅极氧化物的顶表面上。

3. 发明授权

US08350365B1 Mitigation of well proximity effect in integrated circuits 有权
标题翻译：减轻集成电路中的良好邻近效应
公开(公告)号：US08350365B1
公开(公告)日：2013-01-08
申请号：US13005680
申请日：2011-01-13
申请人： Yun Wu , Hong-Tsz Pan , Qi Lin , Bang-Thu Nguyen
发明人： Yun Wu , Hong-Tsz Pan , Qi Lin , Bang-Thu Nguyen
IPC分类号： H01L21/4763
CPC分类号： H01L21/266 , H01L21/26513
摘要： A hard implantation mask layer is formed on a semiconductor wafer. An etch mask layer is formed on the hard implantation mask layer and patterned. The hard implantation mask layer is etched to form a well implantation pattern and ions are implanted into the semiconductor wafer to form wells in the semiconductor wafer, in areas where the semiconductor wafer is not covered by the well implantation mask.
摘要翻译：在半导体晶片上形成硬注入掩模层。在硬注入掩模层上形成蚀刻掩模层并进行图案化。蚀刻硬注入掩模层以形成良好注入图案，并且在半导体晶片未被阱注入掩模覆盖的区域中，将离子注入到半导体晶片中以在半导体晶片中形成阱。

4. 发明授权

US08878337B1 Integrated circuit structure having a capacitor structured to reduce dishing of metal layers 有权
标题翻译：具有电容器的集成电路结构，其构造为减少金属层的凹陷
公开(公告)号：US08878337B1
公开(公告)日：2014-11-04
申请号：US13186279
申请日：2011-07-19
申请人： Hong-Tsz Pan , Yun Wu , Shuxian Wu , Qi Lin , Bang-Thu Nguyen
发明人： Hong-Tsz Pan , Yun Wu , Shuxian Wu , Qi Lin , Bang-Thu Nguyen
IPC分类号： H01L21/02
CPC分类号： H01L29/94 , H01L21/3212 , H01L21/823842 , H01L27/0629 , H01L29/66181 , H01L29/66545 , H01L29/78
摘要： A method and integrated circuit structure for mitigating metal gate dishing resulting from chemical mechanical polishing. The integrated circuit structure comprises a first area comprising at least one first type device; a second area comprising at least one second type device; a third area comprising at least one capacitor having an uppermost layer of polysilicon, where the capacitor area is greater than a sum of the first and second areas. The method utilizes the polysilicon of the capacitor to mitigate metal gate dishing of a metal gate of at least one device.
摘要翻译：一种用于减轻由化学机械抛光引起的金属栅极凹陷的方法和集成电路结构。集成电路结构包括包括至少一个第一类型装置的第一区域; 第二区域，包括至少一个第二类型装置; 第三区域包括至少一个具有多晶硅最上层的电容器，其中电容器面积大于第一和第二区域的总和。该方法利用电容器的多晶硅来减轻至少一个器件的金属栅极的金属栅极凹陷。

5. 发明授权

US07673270B1 Method and apparatus for compensating an integrated circuit layout for mechanical stress effects 有权
标题翻译：用于补偿机械应力影响的集成电路布局的方法和装置
公开(公告)号：US07673270B1
公开(公告)日：2010-03-02
申请号：US11717811
申请日：2007-03-13
申请人： Yan Wang , Nui Chong , Hong-Tsz Pan , Bang-Thu Nguyen , Jonathan Jung-Ching Ho , Qi Lin , Yuhao Luo , Hing Yee Angela Wong , Xin X. Wu , Yuezhen Fan
发明人： Yan Wang , Nui Chong , Hong-Tsz Pan , Bang-Thu Nguyen , Jonathan Jung-Ching Ho , Qi Lin , Yuhao Luo , Hing Yee Angela Wong , Xin X. Wu , Yuezhen Fan
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： Method and apparatus for compensating an integrated circuit design for mechanical stress effects. One aspect of the invention relates to designing an integrated circuit. Layout data is obtained that describes layers of the integrated circuit. At least one of the layers is analyzed to detect at least one structure susceptible to damage from mechanical stress. A bias is automatically added to each of the at least one structure to reduce mechanical stress of the at least one structure as fabricated. Augmented layout data is then provided for the integrated circuit.
摘要翻译：用于补偿机械应力作用的集成电路设计的方法和装置。本发明的一个方面涉及集成电路的设计。获得描述集成电路层的布局数据。分析至少一层以检测易受机械应力破坏的至少一种结构。偏置被自动地添加到至少一个结构中的每个结构中，以减少所制造的至少一个结构的机械应力。然后为集成电路提供增强的布局数据。

6. 发明授权

US08473681B2 Atomic-operation coalescing technique in multi-chip systems 有权
标题翻译：原子操作合并技术在多芯片系统中的应用
公开(公告)号：US08473681B2
公开(公告)日：2013-06-25
申请号：US13143993
申请日：2010-02-02
申请人： Qi Lin , Liang Peng , Craig E. Hampel , Thomas J. Sheffler , Steven C. Woo , Bohuslav Rychlik
发明人： Qi Lin , Liang Peng , Craig E. Hampel , Thomas J. Sheffler , Steven C. Woo , Bohuslav Rychlik
IPC分类号： G06F13/00
CPC分类号： G06F12/00 , G06F9/3004 , G06F9/3834 , G06F12/0815
摘要： A cache-coherence protocol distributes atomic operations among multiple processors (or processor cores) that share a memory space. When an atomic operation that includes an instruction to modify data stored in the shared memory space is directed to a first processor that does not have control over the address(es) associated with the data, the first processor sends a request, including the instruction to modify the data, to a second processor. Then, the second processor, which already has control of the address(es), modifies the data. Moreover, the first processor can immediately proceed to another instruction rather than waiting for the address(es) to become available.
摘要翻译：缓存相干协议在共享内存空间的多个处理器（或处理器核心）之间分配原子操作。当包括修改存储在共享存储器空间中的数据的指令的原子操作被引导到不具有与数据相关联的地址的控制的第一处理器时，第一处理器发送包括指令的请求修改数据到第二个处理器。然后，已经具有对地址的控制的第二处理器修改数据。此外，第一处理器可以立即进行另一个指令，而不是等待地址变得可用。

7. 发明申请

US20110142112A1 Signaling with Superimposed Clock and Data Signals 有权
标题翻译：信号与叠加的时钟和数据信号
公开(公告)号：US20110142112A1
公开(公告)日：2011-06-16
申请号：US12739936
申请日：2008-10-28
申请人： Qi Lin , Jaeha Kim , Brian S. Leibowitz , Jared L. Zerbe , Jihong Ren
发明人： Qi Lin , Jaeha Kim , Brian S. Leibowitz , Jared L. Zerbe , Jihong Ren
IPC分类号： H04L7/00 , H04B17/00
CPC分类号： H04L7/0008 , H04L7/065 , H04L25/0276 , H04L25/14
摘要： A data transmission circuit includes a clock driver to obtain a clock signal having a first rate and to drive the clock signal onto one or more transmission lines. The data transmission circuit also includes a timing circuit to obtain the clock signal and to generate a symbol clock having a second rate. The first rate is a multiple of the second rate, wherein the multiple is greater than one. The data transmission circuit further includes a data driver synchronized to the symbol clock. The data driver obtains a data signal and drives the data signal onto the one or more transmission lines at the second rate. The data signal and the clock signal are driven onto the one or more transmission lines simultaneously.
摘要翻译：数据传输电路包括时钟驱动器，以获得具有第一速率的时钟信号并将时钟信号驱动到一条或多条传输线上。数据传输电路还包括一个定时电路以获得时钟信号并产生具有第二速率的符号时钟。第一速率是第二速率的倍数，其中倍数大于1。数据传输电路还包括与符号时钟同步的数据驱动器。数据驱动器获得数据信号，并以第二速率将数据信号驱动到一条或多条传输线上。数据信号和时钟信号同时被驱动到一个或多个传输线上。

8. 发明申请

US20110119425A1 DETACHABLE INTERCONNECT FOR CONFIGURABLE WIDTH MEMORY SYSTEM 审中-公开
标题翻译：可配置的宽度存储器系统的可互连的互连
公开(公告)号：US20110119425A1
公开(公告)日：2011-05-19
申请号：US12675105
申请日：2008-06-30
申请人： Ravindranath Kollipara , Xingchao Yuan , Frank Lambrecht , Ming Li , Richard E. Perego , Qi Lin , David Nguyen , Kyung Suk Oh
发明人： Ravindranath Kollipara , Xingchao Yuan , Frank Lambrecht , Ming Li , Richard E. Perego , Qi Lin , David Nguyen , Kyung Suk Oh
IPC分类号： G06F13/40 , G06F13/20
CPC分类号： G06F13/1668 , H01L2224/16225 , H01L2924/15174 , H01L2924/15311 , H05K1/0237 , H05K1/0295 , H05K1/14 , H05K1/141 , H05K1/147 , H05K3/222 , H05K2201/044 , H05K2201/09954 , H05K2201/10159 , H05K2201/10356
摘要： The disclosure relates to a detachable signalling interconnect apparatus that provides connectivity between two or more components of a memory system in conjunction with different modes of operation of the components. The memory system comprises: a first socket to receive a first memory module; a second socket to receive a second memory module; a detachable signal-interconnect; and a memory controller coupled to the detachable signal-interconnect and configured to define a first mode of operation and a second mode of operation, wherein in the first mode of operation the detachable signal-interconnect is to couple the memory-controller to the first memory module and in the second mode of operation the detachable signal-interconnect is to couple the memory controller to the first memory module and the second memory module.
摘要翻译：本公开涉及一种可拆卸信令互连装置，其提供存储器系统的两个或更多个组件与组件的不同操作模式之间的连接。存储器系统包括：第一插座，用于接收第一存储器模块; 用于接收第二存储器模块的第二插座; 可拆卸的信号互连; 以及存储器控制器，其耦合到所述可拆卸信号互连并且被配置为限定第一操作模式和第二操作模式，其中在所述第一操作模式中，所述可拆卸信号互连将所述存储器控制器耦合到所述第一存储器模块，并且在第二操作模式中，可拆卸信号互连将存储器控制器耦合到第一存储器模块和第二存储器模块。

9. 发明授权

US06593779B2 Tunable circuit for detection of negative voltages 有权
公开(公告)号：US06593779B2
公开(公告)日：2003-07-15
申请号：US10238214
申请日：2002-09-09
申请人： Farshid Shokouhi , Ben Y. Sheen , Qi Lin
发明人： Farshid Shokouhi , Ben Y. Sheen , Qi Lin
IPC分类号： H03K522
CPC分类号： G11C16/30 , G01R19/0084 , G11C5/145
摘要： The present invention provides a tunable circuit for quickly optimizing an electrical field generated by the F-N tunneling operation. To optimize this electrical field, the charging of a positive charge pump is begun after the charging of a negative charge pump. The tunable circuit of the present invention provides a means to detect the optimal negative voltage at which pumping of the positive voltage should begin. The tunable circuit includes a resistor chain coupled between a first reference voltage and a negative voltage from the negative charge pump. When charging of the negative charge pump begins, a comparator compares the voltage at a node within the resistor chain to a second reference voltage. In accordance with the present invention, the node voltage within the resistor chain is equal to the second reference voltage when the negative voltage is equal to the voltage to be detected. Thus, the comparator generates a trigger signal when the voltage at the node decreases to the second reference voltage. This output signal triggers the pumping of the positive charge pump. By changing the resistance within the resistor chain, the positive charge pumping may be initiated at varying negative voltages. In the present invention, additional resistance is added to or removed from the resistor chain via metal options or switches.

10. 发明授权

US06212103B1 Method for operating flash memory 有权
标题翻译：操作闪存的方法
公开(公告)号：US06212103B1
公开(公告)日：2001-04-03
申请号：US09363075
申请日：1999-07-28
申请人： Michael G. Ahrens , Anders T. Dejenfelt , Qi Lin , Robert A. Olah
发明人： Michael G. Ahrens , Anders T. Dejenfelt , Qi Lin , Robert A. Olah
IPC分类号： G11C1604
CPC分类号： H01L27/11519 , G11C16/14 , G11C16/26 , H01L27/115
摘要： A plurality of flash electrically erasable programmable read only memory (EEPROM) cells is disclosed wherein metal lines couple both the sources and the drains of the flash cells. Reading of these flash cells is accomplished by applying a positive voltage to the source and reading from the associated metal source line. A soft erase scheme for increasing the threshold voltage of over-programmed flash cells is provided that prevents the leakage caused by applying a positive voltage to the drain.
摘要翻译：公开了多个闪存电可擦除可编程只读存储器（EEPROM）单元，其中金属线耦合闪存单元的源极和漏极。这些闪存单元的读取是通过向源极施加正电压并从相关联的金属源极线读取来实现的。提供了用于增加过度编程的闪存单元的阈值电压的软擦除方案，其防止通过向漏极施加正电压而引起的泄漏。

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