专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06286128B1 Method for design optimization using logical and physical information 失效
标题翻译：使用逻辑和物理信息进行设计优化的方法
公开(公告)号：US06286128B1
公开(公告)日：2001-09-04
申请号：US09097299
申请日：1998-06-12
申请人： Lawrence Pileggi , Majid Sarrafzadeh , Sharad Malik , Abhijeet Chakraborty , Archie Li , Robert Eugene Shortt , Christopher Dunn , David Gluss , Dennis Yamamoto , Dinesh Gaitonde , Douglas B. Boyle , Emre Tuncer , Eric McCaughrin , Feroze Peshotan Taraporevala , Gary K. Yeap , James S. Koford , Joseph T. Rahmeh , Lilly Shieh , Salil R. Raje , Sam Jung Kim , Satamurthy Pullela , Yau-Tsun Steven Li , Tong Gao
发明人： Lawrence Pileggi , Majid Sarrafzadeh , Sharad Malik , Abhijeet Chakraborty , Archie Li , Robert Eugene Shortt , Christopher Dunn , David Gluss , Dennis Yamamoto , Dinesh Gaitonde , Douglas B. Boyle , Emre Tuncer , Eric McCaughrin , Feroze Peshotan Taraporevala , Gary K. Yeap , James S. Koford , Joseph T. Rahmeh , Lilly Shieh , Salil R. Raje , Sam Jung Kim , Satamurthy Pullela , Yau-Tsun Steven Li , Tong Gao
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F17/5068 , G06F2217/78
摘要： A method for design optimization using logical and physical information is provided. In one embodiment, a method for design optimization using logical and physical information, includes receiving a behavioral description of an integrated circuit or a portion of an integrated circuit, optimizing placement of circuit elements in accordance with a first cost function, and optimizing logic of the circuit elements in accordance with a second cost function, in which the optimizing placement of the circuit elements and the optimizing logic of the circuit elements are performed concurrently. The method can further include optimizing routing in accordance with a third cost function, in which the optimizing routing, the optimizing placement of the circuit elements, and the optimizing logic of the circuit elements are performed concurrently.
摘要翻译：提供了使用逻辑和物理信息进行设计优化的方法。在一个实施例中，使用逻辑和物理信息的设计优化的方法包括接收集成电路或集成电路的一部分的行为描述，根据第一成本函数优化电路元件的布局，以及优化逻辑根据第二成本函数的电路元件，其中同时执行电路元件的优化布置和电路元件的优化逻辑。该方法可以进一步包括根据第三成本函数优化路由，其中同时执行优化路由，电路元件的优化布局和电路元件的优化逻辑。

2. 发明授权

US06961916B2 Placement method for integrated circuit design using topo-clustering 有权
公开(公告)号：US06961916B2
公开(公告)日：2005-11-01
申请号：US10136161
申请日：2002-05-01
申请人： Majid Sarrafzadeh , Lawrence Pileggi , Sharad Malik , Feroze Peshotan Taraporevala , Abhijeet Chakraborty , Gary K. Yeap , Salil R. Raje , Lilly Shieh , Douglas B. Boyle , Dennis Yamamoto
发明人： Majid Sarrafzadeh , Lawrence Pileggi , Sharad Malik , Feroze Peshotan Taraporevala , Abhijeet Chakraborty , Gary K. Yeap , Salil R. Raje , Lilly Shieh , Douglas B. Boyle , Dennis Yamamoto
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： The present invention, generally speaking, provides a placement method for the physical design of integrated circuits in which natural topological feature clusters (topo-clusters) are discovered and exploited during the placement process. Topo-clusters may be formed based on various criteria including, for example, functional similarity, proximity (in terms of number of nets), and genus. Genus refers to a representation of a netlist in terms of a number of planar netlists—netlists in which no crossing of nets occurs. Topo-clusters drive initial placement, with all of the gates of a topo-cluster being placed initially in a single bin of the placement layout or within a group of positionally-related bins. The portion of a topo-cluster placed within a given bin is called a quanto-cluster. An iterative placement refinement process then follows, using a technique referred to herein as Geometrically-Bounded FM (GBFM), and in particular Dual GBFM. In GBFM, FM is applied on a local basis to windows encompassing some number of bins. From iteration to iteration, windows may shift position and vary in size. When a region bounded by a window meets a specified cost threshold in terms of a specified cost function, that region does not participate. The cost function takes account of actual physical metrics—delay, area, congestion, power, etc. “Dual” refers to the fact that each iteration has two phases. During a first phase, FM is performed within a region on a quanto-cluster basis. During a second phase, FM is performed within the region on a gate basis. GBFM occurs in the context of recursive quadrisection. Hence, after GBFM has been completed, a further quadrisection step is performed in which each bin is divided into four bins, with a quarter of the gates of the original bin being placed in the center of each of the resulting bins. GBFM then follows, and the cycle repeats until each bin contains a fairly small number of gates. Following the foregoing global placement process, the circuit is then ready for detailed placement in which cells are assigned to placement rows.

3. 发明授权

US06192508B1 Method for logic optimization for improving timing and congestion during placement in integrated circuit design 失效
标题翻译：用于在集成电路设计中放置时改善时序和拥塞的逻辑优化方法
公开(公告)号：US06192508B1
公开(公告)日：2001-02-20
申请号：US09097076
申请日：1998-06-12
申请人： Sharad Malik , Lawrence Pileggi , Abhijeet Chakraborty , Gary K. Yeap , Douglas B. Boyle
发明人： Sharad Malik , Lawrence Pileggi , Abhijeet Chakraborty , Gary K. Yeap , Douglas B. Boyle
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F17/5072
摘要： This invention recognizes the ability of logic optimization to help placement relieve congestion. Different types of logic optimizations are used to help placement relieve congestion. In one type of optimization, the speed of parts of the circuit is improved by selecting faster cells. In another type of optimization, the topology of the circuit is changed such that placement can now move cells, which could not have been moved before, to reduce congestion and thus enable routing. A distinguishing feature of this methodology is that it not only uses the placement information for interconnection delay/area estimates during logic optimization, but also uses logic optimization to aid the physical placement steps by providing support to placement so that the congestion of the circuit is improved. The aim is to avoid getting into a situation where the placed circuit cannot be routed.
摘要翻译：本发明认识到逻辑优化能够帮助放置缓解拥塞。使用不同类型的逻辑优化来帮助放置缓解拥塞。在一种类型的优化中，通过选择更快的单元来提高电路部分的速度。在另一种类型的优化中，改变电路的拓扑结构，使得放置现在可以移动以前不能被移动的单元，以减少拥塞并由此实现路由。该方法的一个突出特点是，它不仅在逻辑优化期间使用放置信息进行互连延迟/面积估计，而且还通过为放置提供支持来使用逻辑优化来辅助物理放置步骤，从而改善电路的拥塞。目的是避免进入放置的电路不能路由的情况。

4. 发明授权

US06442743B1 Placement method for integrated circuit design using topo-clustering 失效
标题翻译：使用拓扑聚类的集成电路设计的放置方法
公开(公告)号：US06442743B1
公开(公告)日：2002-08-27
申请号：US09097107
申请日：1998-06-12
申请人： Majid Sarrafzadeh , Lawrence Pileggi , Sharad Malik , Feroze Peshotan Taraporevala , Abhijeet Chakraborty , Gary K. Yeap , Salil R. Raje , Lilly Shieh , Douglas B. Boyle , Dennis Yamamoto
发明人： Majid Sarrafzadeh , Lawrence Pileggi , Sharad Malik , Feroze Peshotan Taraporevala , Abhijeet Chakraborty , Gary K. Yeap , Salil R. Raje , Lilly Shieh , Douglas B. Boyle , Dennis Yamamoto
IPC分类号： G06F1750
CPC分类号： G06F17/5072
摘要： The disclosure describes a placement method for the physical design of integrated circuits in which natural topological feature clusters are discovered and exploited during the placement process is disclosed. Topo-clusters drive initial placement, with all of the gates of a topo-cluster being placed initially in a single bin of the placement layout or within a group of positionally-related bins. An iterative placement refinement process is done using a technique referred to as Dual Geometrically-Bounded FM (GBFM). GBFM is applied on a local basis to windows encompassing a number of bins. From iteration to iteration, windows may shift position and vary in size. When a region bounded by a window meets a specified cost threshold in terms of a specified cost function, that region stops participating. Following the foregoing global placement process the circuit is then ready for detailed placement in which cells are assigned to placement rows.
摘要翻译：本公开描述了用于集成电路的物理设计的放置方法，其中公开了在放置过程期间发现和利用自然拓扑特征簇。拓扑群集驱动初始位置，其中所有的拓扑群集的门最初都放置在放置布局的一个bin或一组位置相关的区域中。使用称为双重几何限幅FM（GBFM）的技术完成迭代放置细化过程。 GBFM在本地基础上应用于包含多个分区的窗口。从迭代到迭代，窗口可能会改变位置并且大小变化。当由窗口界定的区域在指定的成本函数方面满足指定的成本阈值时，该区域停止参与。按照上述全局放置过程，电路准备好进行详细的放置，其中将单元格分配给放置行。

5. 发明授权

US06449756B1 Method for accurate and efficient updates of timing information logic synthesis, placement and routing for integrated circuit design 失效
标题翻译：准确高效地更新定时信息逻辑综合，集成电路设计布局和路由的方法
公开(公告)号：US06449756B1
公开(公告)日：2002-09-10
申请号：US09094542
申请日：1998-06-12
申请人： Sharad Malik , Lawrence Pileggi , Eric McCaughrin , Abhijeet Chakraborty , Douglas B. Boyle
发明人： Sharad Malik , Lawrence Pileggi , Eric McCaughrin , Abhijeet Chakraborty , Douglas B. Boyle
IPC分类号： G06F1750
CPC分类号： G06F17/5031
摘要： A timing graph representing timing information of an integrated circuit design may change after modifications are made to the integrated circuit design. The modifications change timing parameters for edges in the timing graph. The measure of these changes may be computed at a computed measure compared to a threshold. In the event the measure exceeds the threshold, the edges in the timing graph that need to change in response to the modifications are updated. Otherwise, the current edges in the timing graph are continued to be used. The threshold is set in accordance with the accuracy and efficiency requirements of an electronic design automation tool.
摘要翻译：表示集成电路设计的定时信息的时序图可以在对集成电路设计进行修改之后改变。修改改变时序图中边缘的时序参数。可以在与阈值相比较的计算措施下计算这些变化的度量。在度量超过阈值的情况下，更新需要更改的时序图中的边缘。否则，继续使用定时图中的当前边。阈值是根据电子设计自动化工具的精度和效率要求设定的。

6. 发明授权

US06367051B1 System and method for concurrent buffer insertion and placement of logic gates 失效
标题翻译：并行缓冲区插入和放置逻辑门的系统和方法
公开(公告)号：US06367051B1
公开(公告)日：2002-04-02
申请号：US09096810
申请日：1998-06-12
申请人： Lawrence Pileggi , Sharad Malik , Emre Tuncer , Abhijeet Chakraborty , Satyamurthy Pullela , Altan Odabasioglu , Douglas B. Boyle
发明人： Lawrence Pileggi , Sharad Malik , Emre Tuncer , Abhijeet Chakraborty , Satyamurthy Pullela , Altan Odabasioglu , Douglas B. Boyle
IPC分类号： G06F1750
CPC分类号： G06F17/505
摘要： A design tool for integrated circuits includes a placement tool which concurrently places logic gates and interconnect. In one embodiment, the logic gates are placed into bins and virtual buffers are inserted between logic gates mapped to different bins. Placement and interconnect wire lengths and densities are successively improved leading to removal of some buffers and actualization of the virtual buffers.
摘要翻译：用于集成电路的设计工具包括同时放置逻辑门和互连的放置工具。在一个实施例中，逻辑门被放置到存储区中，并且虚拟缓冲器被插入映射到不同仓的逻辑门之间。放置和互连线长度和密度被连续改善，导致一些缓冲器的移除和虚拟缓冲器的实现。

7. 发明授权

US06385760B2 System and method for concurrent placement of gates and associated wiring 失效
标题翻译：门和相关布线同时放置的系统和方法
公开(公告)号：US06385760B2
公开(公告)日：2002-05-07
申请号：US09096804
申请日：1998-06-12
申请人： Lawrence Pileggi , Majid Sarrafzadeh , Gary K. Yeap , Feroze Peshotan Taraporevala , Tong Gao , Douglas B. Boyle
发明人： Lawrence Pileggi , Majid Sarrafzadeh , Gary K. Yeap , Feroze Peshotan Taraporevala , Tong Gao , Douglas B. Boyle
IPC分类号： G06F1750
CPC分类号： G06F17/5072
摘要： A design tool for integrated circuits includes a placement tool which places logic gates and interconnect components concurrently. Probabilistic interconnect models are used to represent the collection of possible interconnect routings that provide acceptable circuit performance and routing area.
摘要翻译：用于集成电路的设计工具包括同时放置逻辑门和互连组件的放置工具。概率互连模型用于表示提供可接受的电路性能和路由区域的可能的互连路由的集合。

8. 发明授权

US07487486B2 Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations 有权
标题翻译：定义具有大规模工艺和环境变化的逻辑电路的时序优化的统计灵敏度
公开(公告)号：US07487486B2
公开(公告)日：2009-02-03
申请号：US11629445
申请日：2005-06-11
申请人： Mustafa Celik , Jiayong Le , Lawrence Pileggi , Xin Li
发明人： Mustafa Celik , Jiayong Le , Lawrence Pileggi , Xin Li
IPC分类号： G06F17/50 , G06F7/60 , G06F7/52
CPC分类号： G06F17/5031 , G06F2217/10
摘要： The large-scale process and environmental variations for today's nano-scale ICs are requiring statistical approaches for timing analysis and optimization (1). Significant research has been recently focused on developing new statistical timing analysis algorithms (2), but often without consideration for how one should interpret the statistical timing results for optimization. The invention provides a sensitivity-based metric (2) to assess the criticality of each path and/or arc in the statistical timing graph (4). The statistical sensitivities for both paths and arcs are defined. It is shown that path sensitivity is equivalent to the probability that a path is critical, and arc sensitivity is equivalent to the probability that an arc sits on the critical path. An efficient algorithm with incremental analysis capability (2) is described for fast sensitivity computation that has a linear runtime complexity in circuit size. The efficacy of the proposed sensitivity analysis is demonstrated on both standard benchmark circuits and large industry examples.
摘要翻译：目前的纳米尺度IC的大规模工艺和环境变化需要用于时序分析和优化的统计方法（1）。最近重点研究重点是开发新的统计时序分析算法（2），但往往不考虑如何解释统计时序结果进行优化。本发明提供了一种基于灵敏度的度量（2）来评估统计时序图（4）中每个路径和/或弧的关键性。定义了路径和弧线的统计灵敏度。显示路径灵敏度等于路径关键的概率，弧敏感度等于弧位于关键路径上的概率。描述了具有增量分析能力的有效算法（2），用于快速灵敏度计算，其电路尺寸具有线性运行时间复杂度。提出的灵敏度分析的功效在标准基准电路和大型行业实例中得到证明。

9. 发明申请

US20070019447A1 Active resistors for reduction of transient power grid noise 审中-公开
标题翻译：用于减少瞬态电网噪声的有源电阻
公开(公告)号：US20070019447A1
公开(公告)日：2007-01-25
申请号：US11176055
申请日：2005-07-07
申请人： Gokce Keskin , Xin Li , Lawrence Pileggi
发明人： Gokce Keskin , Xin Li , Lawrence Pileggi
IPC分类号： H02H7/10
CPC分类号： H03K19/00361 , H01L27/0288 , H03K17/165
摘要： Active resistors for reduction of transient power grid noise. An active resistance added in parallel to the operating circuit blocks of a semiconductor device. This resistance increases the damping ratio of the power grid, which in turn decreases the number and the magnitude of oscillations and/or noise resulting from step disturbances of the power supply current. The active resistance can implemented by a transistor connected to a bias voltage. Alternatively, the active resistance can be implemented by a drive transistor with a gain stage, or two active resistors where one responds to overshoots in the current flow and the second active resistor responds to droops in the current flow.
摘要翻译：用于减少瞬态电网噪声的有源电阻。与半导体器件的工作电路块并联的有源电阻。该电阻增加了电力网的阻尼比，而电网的阻尼比又降低了由电源电流的阶跃扰动引起的振荡和/或噪声的数量和幅度。有源电阻可以由连接到偏置电压的晶体管实现。或者，有源电阻可以由具有增益级的驱动晶体管或两个有源电阻器来实现，其中一个响应于电流中的过冲而第二有效电阻器响应电流中的下降。

10. 发明申请

US20080072198A1 Defining Statistical Sensitivity for Timing Optimization of Logic Circuits with Large-Scale Process and Environmental Variations 有权
标题翻译：定义具有大规模过程和环境变化的逻辑电路的时序优化的统计灵敏度
公开(公告)号：US20080072198A1
公开(公告)日：2008-03-20
申请号：US11629445
申请日：2005-06-11
申请人： Mustafa Celik , Jiayong Le , Lawrence Pileggi , Xin Li
发明人： Mustafa Celik , Jiayong Le , Lawrence Pileggi , Xin Li
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/10
摘要： The large-scale process and environmental variations for today's nano-scale ICs are requiring statistical approaches for timing analysis and optimization (1). Significant research has been recently focused on developing new statistical timing analysis algorithms (2), but often without consideration for how one should interpret the statistical timing results for optimization. The invention provides a sensitivity-based metric (2) to assess the criticality of each path and/or arc in the statistical timing graph (4). The statistical sensitivities for both paths and arcs are defined. It is shown that path sensitivity is equivalent to the probability that a path is critical, and arc sensitivity is equivalent to the probability that an arc sits on the critical path. An efficient algorithm with incremental analysis capability (2) is described for fast sensitivity computation that has a linear runtime complexity in circuit size. The efficacy of the proposed sensitivity analysis is demonstrated on both standard benchmark circuits and large industry examples.
摘要翻译：目前的纳米尺度IC的大规模工艺和环境变化需要用于时序分析和优化的统计方法（1）。最近重点研究重点是开发新的统计时序分析算法（2），但往往不考虑如何解释统计时序结果进行优化。本发明提供了一种基于灵敏度的度量（2）来评估统计时序图（4）中每个路径和/或弧的关键性。定义了路径和弧线的统计灵敏度。显示路径灵敏度等于路径关键的概率，弧敏感度等于弧位于关键路径上的概率。描述了具有增量分析能力的有效算法（2），用于快速灵敏度计算，其电路尺寸具有线性运行时间复杂度。提出的灵敏度分析的功效在标准基准电路和大型行业实例中得到证明。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式