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1. 发明授权

US06367051B1 System and method for concurrent buffer insertion and placement of logic gates 失效
标题翻译：并行缓冲区插入和放置逻辑门的系统和方法
公开(公告)号：US06367051B1
公开(公告)日：2002-04-02
申请号：US09096810
申请日：1998-06-12
申请人： Lawrence Pileggi , Sharad Malik , Emre Tuncer , Abhijeet Chakraborty , Satyamurthy Pullela , Altan Odabasioglu , Douglas B. Boyle
发明人： Lawrence Pileggi , Sharad Malik , Emre Tuncer , Abhijeet Chakraborty , Satyamurthy Pullela , Altan Odabasioglu , Douglas B. Boyle
IPC分类号： G06F1750
CPC分类号： G06F17/505
摘要： A design tool for integrated circuits includes a placement tool which concurrently places logic gates and interconnect. In one embodiment, the logic gates are placed into bins and virtual buffers are inserted between logic gates mapped to different bins. Placement and interconnect wire lengths and densities are successively improved leading to removal of some buffers and actualization of the virtual buffers.
摘要翻译：用于集成电路的设计工具包括同时放置逻辑门和互连的放置工具。在一个实施例中，逻辑门被放置到存储区中，并且虚拟缓冲器被插入映射到不同仓的逻辑门之间。放置和互连线长度和密度被连续改善，导致一些缓冲器的移除和虚拟缓冲器的实现。

2. 发明授权

US06286128B1 Method for design optimization using logical and physical information 失效
标题翻译：使用逻辑和物理信息进行设计优化的方法
公开(公告)号：US06286128B1
公开(公告)日：2001-09-04
申请号：US09097299
申请日：1998-06-12
申请人： Lawrence Pileggi , Majid Sarrafzadeh , Sharad Malik , Abhijeet Chakraborty , Archie Li , Robert Eugene Shortt , Christopher Dunn , David Gluss , Dennis Yamamoto , Dinesh Gaitonde , Douglas B. Boyle , Emre Tuncer , Eric McCaughrin , Feroze Peshotan Taraporevala , Gary K. Yeap , James S. Koford , Joseph T. Rahmeh , Lilly Shieh , Salil R. Raje , Sam Jung Kim , Satamurthy Pullela , Yau-Tsun Steven Li , Tong Gao
发明人： Lawrence Pileggi , Majid Sarrafzadeh , Sharad Malik , Abhijeet Chakraborty , Archie Li , Robert Eugene Shortt , Christopher Dunn , David Gluss , Dennis Yamamoto , Dinesh Gaitonde , Douglas B. Boyle , Emre Tuncer , Eric McCaughrin , Feroze Peshotan Taraporevala , Gary K. Yeap , James S. Koford , Joseph T. Rahmeh , Lilly Shieh , Salil R. Raje , Sam Jung Kim , Satamurthy Pullela , Yau-Tsun Steven Li , Tong Gao
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F17/5068 , G06F2217/78
摘要： A method for design optimization using logical and physical information is provided. In one embodiment, a method for design optimization using logical and physical information, includes receiving a behavioral description of an integrated circuit or a portion of an integrated circuit, optimizing placement of circuit elements in accordance with a first cost function, and optimizing logic of the circuit elements in accordance with a second cost function, in which the optimizing placement of the circuit elements and the optimizing logic of the circuit elements are performed concurrently. The method can further include optimizing routing in accordance with a third cost function, in which the optimizing routing, the optimizing placement of the circuit elements, and the optimizing logic of the circuit elements are performed concurrently.
摘要翻译：提供了使用逻辑和物理信息进行设计优化的方法。在一个实施例中，使用逻辑和物理信息的设计优化的方法包括接收集成电路或集成电路的一部分的行为描述，根据第一成本函数优化电路元件的布局，以及优化逻辑根据第二成本函数的电路元件，其中同时执行电路元件的优化布置和电路元件的优化逻辑。该方法可以进一步包括根据第三成本函数优化路由，其中同时执行优化路由，电路元件的优化布局和电路元件的优化逻辑。

3. 发明授权

US06442743B1 Placement method for integrated circuit design using topo-clustering 失效
标题翻译：使用拓扑聚类的集成电路设计的放置方法
公开(公告)号：US06442743B1
公开(公告)日：2002-08-27
申请号：US09097107
申请日：1998-06-12
申请人： Majid Sarrafzadeh , Lawrence Pileggi , Sharad Malik , Feroze Peshotan Taraporevala , Abhijeet Chakraborty , Gary K. Yeap , Salil R. Raje , Lilly Shieh , Douglas B. Boyle , Dennis Yamamoto
发明人： Majid Sarrafzadeh , Lawrence Pileggi , Sharad Malik , Feroze Peshotan Taraporevala , Abhijeet Chakraborty , Gary K. Yeap , Salil R. Raje , Lilly Shieh , Douglas B. Boyle , Dennis Yamamoto
IPC分类号： G06F1750
CPC分类号： G06F17/5072
摘要： The disclosure describes a placement method for the physical design of integrated circuits in which natural topological feature clusters are discovered and exploited during the placement process is disclosed. Topo-clusters drive initial placement, with all of the gates of a topo-cluster being placed initially in a single bin of the placement layout or within a group of positionally-related bins. An iterative placement refinement process is done using a technique referred to as Dual Geometrically-Bounded FM (GBFM). GBFM is applied on a local basis to windows encompassing a number of bins. From iteration to iteration, windows may shift position and vary in size. When a region bounded by a window meets a specified cost threshold in terms of a specified cost function, that region stops participating. Following the foregoing global placement process the circuit is then ready for detailed placement in which cells are assigned to placement rows.
摘要翻译：本公开描述了用于集成电路的物理设计的放置方法，其中公开了在放置过程期间发现和利用自然拓扑特征簇。拓扑群集驱动初始位置，其中所有的拓扑群集的门最初都放置在放置布局的一个bin或一组位置相关的区域中。使用称为双重几何限幅FM（GBFM）的技术完成迭代放置细化过程。 GBFM在本地基础上应用于包含多个分区的窗口。从迭代到迭代，窗口可能会改变位置并且大小变化。当由窗口界定的区域在指定的成本函数方面满足指定的成本阈值时，该区域停止参与。按照上述全局放置过程，电路准备好进行详细的放置，其中将单元格分配给放置行。

4. 发明授权

US06449756B1 Method for accurate and efficient updates of timing information logic synthesis, placement and routing for integrated circuit design 失效
标题翻译：准确高效地更新定时信息逻辑综合，集成电路设计布局和路由的方法
公开(公告)号：US06449756B1
公开(公告)日：2002-09-10
申请号：US09094542
申请日：1998-06-12
申请人： Sharad Malik , Lawrence Pileggi , Eric McCaughrin , Abhijeet Chakraborty , Douglas B. Boyle
发明人： Sharad Malik , Lawrence Pileggi , Eric McCaughrin , Abhijeet Chakraborty , Douglas B. Boyle
IPC分类号： G06F1750
CPC分类号： G06F17/5031
摘要： A timing graph representing timing information of an integrated circuit design may change after modifications are made to the integrated circuit design. The modifications change timing parameters for edges in the timing graph. The measure of these changes may be computed at a computed measure compared to a threshold. In the event the measure exceeds the threshold, the edges in the timing graph that need to change in response to the modifications are updated. Otherwise, the current edges in the timing graph are continued to be used. The threshold is set in accordance with the accuracy and efficiency requirements of an electronic design automation tool.
摘要翻译：表示集成电路设计的定时信息的时序图可以在对集成电路设计进行修改之后改变。修改改变时序图中边缘的时序参数。可以在与阈值相比较的计算措施下计算这些变化的度量。在度量超过阈值的情况下，更新需要更改的时序图中的边缘。否则，继续使用定时图中的当前边。阈值是根据电子设计自动化工具的精度和效率要求设定的。

5. 发明授权

US06961916B2 Placement method for integrated circuit design using topo-clustering 有权
公开(公告)号：US06961916B2
公开(公告)日：2005-11-01
申请号：US10136161
申请日：2002-05-01
申请人： Majid Sarrafzadeh , Lawrence Pileggi , Sharad Malik , Feroze Peshotan Taraporevala , Abhijeet Chakraborty , Gary K. Yeap , Salil R. Raje , Lilly Shieh , Douglas B. Boyle , Dennis Yamamoto
发明人： Majid Sarrafzadeh , Lawrence Pileggi , Sharad Malik , Feroze Peshotan Taraporevala , Abhijeet Chakraborty , Gary K. Yeap , Salil R. Raje , Lilly Shieh , Douglas B. Boyle , Dennis Yamamoto
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： The present invention, generally speaking, provides a placement method for the physical design of integrated circuits in which natural topological feature clusters (topo-clusters) are discovered and exploited during the placement process. Topo-clusters may be formed based on various criteria including, for example, functional similarity, proximity (in terms of number of nets), and genus. Genus refers to a representation of a netlist in terms of a number of planar netlists—netlists in which no crossing of nets occurs. Topo-clusters drive initial placement, with all of the gates of a topo-cluster being placed initially in a single bin of the placement layout or within a group of positionally-related bins. The portion of a topo-cluster placed within a given bin is called a quanto-cluster. An iterative placement refinement process then follows, using a technique referred to herein as Geometrically-Bounded FM (GBFM), and in particular Dual GBFM. In GBFM, FM is applied on a local basis to windows encompassing some number of bins. From iteration to iteration, windows may shift position and vary in size. When a region bounded by a window meets a specified cost threshold in terms of a specified cost function, that region does not participate. The cost function takes account of actual physical metrics—delay, area, congestion, power, etc. “Dual” refers to the fact that each iteration has two phases. During a first phase, FM is performed within a region on a quanto-cluster basis. During a second phase, FM is performed within the region on a gate basis. GBFM occurs in the context of recursive quadrisection. Hence, after GBFM has been completed, a further quadrisection step is performed in which each bin is divided into four bins, with a quarter of the gates of the original bin being placed in the center of each of the resulting bins. GBFM then follows, and the cycle repeats until each bin contains a fairly small number of gates. Following the foregoing global placement process, the circuit is then ready for detailed placement in which cells are assigned to placement rows.

6. 发明授权

US06192508B1 Method for logic optimization for improving timing and congestion during placement in integrated circuit design 失效
标题翻译：用于在集成电路设计中放置时改善时序和拥塞的逻辑优化方法
公开(公告)号：US06192508B1
公开(公告)日：2001-02-20
申请号：US09097076
申请日：1998-06-12
申请人： Sharad Malik , Lawrence Pileggi , Abhijeet Chakraborty , Gary K. Yeap , Douglas B. Boyle
发明人： Sharad Malik , Lawrence Pileggi , Abhijeet Chakraborty , Gary K. Yeap , Douglas B. Boyle
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F17/5072
摘要： This invention recognizes the ability of logic optimization to help placement relieve congestion. Different types of logic optimizations are used to help placement relieve congestion. In one type of optimization, the speed of parts of the circuit is improved by selecting faster cells. In another type of optimization, the topology of the circuit is changed such that placement can now move cells, which could not have been moved before, to reduce congestion and thus enable routing. A distinguishing feature of this methodology is that it not only uses the placement information for interconnection delay/area estimates during logic optimization, but also uses logic optimization to aid the physical placement steps by providing support to placement so that the congestion of the circuit is improved. The aim is to avoid getting into a situation where the placed circuit cannot be routed.
摘要翻译：本发明认识到逻辑优化能够帮助放置缓解拥塞。使用不同类型的逻辑优化来帮助放置缓解拥塞。在一种类型的优化中，通过选择更快的单元来提高电路部分的速度。在另一种类型的优化中，改变电路的拓扑结构，使得放置现在可以移动以前不能被移动的单元，以减少拥塞并由此实现路由。该方法的一个突出特点是，它不仅在逻辑优化期间使用放置信息进行互连延迟/面积估计，而且还通过为放置提供支持来使用逻辑优化来辅助物理放置步骤，从而改善电路的拥塞。目的是避免进入放置的电路不能路由的情况。

7. 发明授权

US5841673A System and method for processing graphic delay data of logic circuit to reduce topological redundancy 失效
标题翻译：用于处理逻辑电路的图形延迟数据以减少拓扑冗余的系统和方法
公开(公告)号：US5841673A
公开(公告)日：1998-11-24
申请号：US593569
申请日：1996-01-30
申请人： Noriya Kobayashi , Sharad Malik
发明人： Noriya Kobayashi , Sharad Malik
IPC分类号： G06F17/50 , G06F17/00
CPC分类号： G06F17/5031
摘要： A delay network of logic circuit delay data composed of a first set of vertices containing first to fourth vertices, and a first set of weighted directional edges containing a first directional edge extending from the first vertex to the fourth vertex, a second directional edge extending from the second vertex to the third vertex, a third directional edge extending from the first vertex to the third vertex, and a fourth directional edge extending from the second vertex to the fourth vertex, is converted into a delay network composed of a second set of vertices containing the first to fourth vertices and an added fifth vertex, and a second set of weighted directional edges containing a fifth directional edge extending from the first vertex to the fifth vertex, a sixth directional edge extending from the second vertex to the fifth vertex, a seventh directional edge extending from the fifth vertex to the third vertex, and an eighth directional edge extending from the fifth vertex to the fourth vertex.
摘要翻译：由包含第一至第四顶点的第一组顶点组成的逻辑电路延迟数据的延迟网络以及包含从第一顶点延伸到第四顶点的第一方向边缘的第一组加权方向边缘，第二方向边缘从第二顶点到第三顶点，从第一顶点延伸到第三顶点的第三方向边缘和从第二顶点延伸到第四顶点的第四方向边缘被转换成由第二组顶点组成的延迟网络包含第一至第四顶点和第五顶点，以及包含从第一顶点延伸到第五顶点的第五方向边缘的第二组加权方向边缘，从第二顶点延伸到第五顶点的第六方向边缘，从第五顶点延伸到第三顶点的第七方向边缘以及从第五顶点延伸到f的第八方向边缘神话顶点

8. 发明授权

US5522063A Method of finding minimum-cost feedback-vertex sets for a graph for partial scan testing without exhaustive cycle enumeration 失效
标题翻译：寻找用于部分扫描测试的图的最小成本反馈顶点集的方法，而没有详尽的循环枚举
公开(公告)号：US5522063A
公开(公告)日：1996-05-28
申请号：US127681
申请日：1993-09-27
申请人： Pranav N. Ashar , Sharad Malik
发明人： Pranav N. Ashar , Sharad Malik
IPC分类号： G01R31/3183 , G01R31/3185 , G06F15/00
CPC分类号： G01R31/318371 , G01R31/318586
摘要： In partial scan testing of integrated circuits, for an arbitrary graph of an integrated circuit, a Boolean function is derived whose satisfying assignments directly correspond to feedback vertex sets of the graph. The Boolean function is then used for determining the minimum cost feedback vertex set. Boolean function representation using Binary Decision Diagrams (BDI)) in logic synthesis is used to solve the problem of representing the Boolean function efficiently, even for large graphs. The determined minimum cost feedback vertex set is used to select those memory elements in the integrated circuit comprising the scan chain.
摘要翻译：在集成电路的部分扫描测试中，对于集成电路的任意图形，导出其满意分配直接对应于图的反馈顶点集的布尔函数。然后使用布尔函数来确定最小成本反馈顶点集。逻辑综合中使用二进制决策图（BDI）的布尔函数表示法用于解决即使对于大图形也能有效地表示布尔函数的问题。确定的最小成本反馈顶点组用于选择包括扫描链的集成电路中的那些存储器元件。

9. 发明授权

US07418369B2 Method and system for efficient implementation of boolean satisfiability 有权
标题翻译：有效实现布尔可满足性的方法和系统
公开(公告)号：US07418369B2
公开(公告)日：2008-08-26
申请号：US10238125
申请日：2002-09-09
申请人： Matthew Moskewicz , Conor Madigan , Sharad Malik
发明人： Matthew Moskewicz , Conor Madigan , Sharad Malik
IPC分类号： G06F17/11
CPC分类号： G06F17/504
摘要： Disclosed is a complete SAT solver, Chaff, which is one to two orders of magnitude faster than existing SAT solvers. Using the Davis-Putnam (DP) backtrack search strategy, Chaff employs efficient Boolean Constraint Propagation (BCP), termed two literal watching, and a low overhead decision making strategy, termed Variable State Independent Decaying Sum (VSIDS). During BCP, Chaff watches two literals not assigned to zero. The literals can be specifically ordered or randomly selected. VSIDS ranks variables, the highest-ranking literal having the highest counter value, where counter value is incremented by one for each occurrence of a literal in a clause. Periodically, the counters are divided by a constant to favor literals included in recently created conflict clauses. VSIDS can also be used to select watched literals, the literal least likely to be set (i.e., lowest VSIDS rank, or lowest VSIDS rank combined with last decision level) being selected to watch.
摘要翻译：披露了一个完整的SAT求解器，Chaff，比现有的SAT解算器快一到两个数量级。 Chaff采用戴维斯 - 普特南（DP）回溯搜索策略，采用高效的布尔约束传播（BCP），称为两个文字观看，以及称为可变状态独立衰减（VSIDS）的低开销决策策略。在BCP期间，Chaff观察到两个文字未分配到零。文字可以特别订购或随机选择。 VSIDS排列变量，最高排名的文字具有最高的计数器值，其中计数器值在子句中每次出现文字时增加1。定期地，计数器除以常数，以支持最近创建的冲突条款中包括的文字。 VSIDS也可以用于选择观看的文字，被选择观看的文字最少可能设置（即，最低的VSIDS等级或最后的VSIDS等级与最后的决定级别相结合）。

10. 发明授权

US6038392A Implementation of boolean satisfiability with non-chronological backtracking in reconfigurable hardware 失效
标题翻译：在可重配置硬件中实现具有非时序回溯的布尔可满足性
公开(公告)号：US6038392A
公开(公告)日：2000-03-14
申请号：US85646
申请日：1998-05-27
申请人： Pranav Ashar , Sharad Malik , Margaret Martonosi , Peixin Zhong
发明人： Pranav Ashar , Sharad Malik , Margaret Martonosi , Peixin Zhong
IPC分类号： G06F9/44 , G06F17/10 , G06F17/50 , G06N5/04
CPC分类号： G06F17/5054
摘要： A Boolean SAT solver uses reconfigurable hardware to solve a specific input problem. Each of the plurality of ordered variables has a corresponding one of a plurality of state machines. Each state machine has an implication circuit for its respective variable, and operates in parallel according to an identical state machine. One state machine implements the Davis-Putnam method in hardware and provides improved performance over software by virtue of the parallel checking of direct and transitive implications. Another state machine implements a novel non-chronological backtracking method that takes advantage of the parallel implication checking and avoids the need to maintain or to traverse a GRASP type implication graph in the event of backtracking. The novel non-chronological backtracking provides for setting a blocking variable as a leaf variable and for changing only the value of the leaf variable, but possibly changing both the value and identity of a backtracking variable.
摘要翻译：布尔SAT求解器使用可重构硬件来解决特定的输入问题。多个有序变量中的每一个具有多个状态机中的对应的一个。每个状态机具有用于其各自变量的含义电路，并且根据相同的状态机并行操作。一个状态机通过硬件实现Davis-Putnam方法，并通过并行检查直接和传递的影响，提高了软件性能。另一种状态机实现了一种新颖的非时间回溯方法，其利用并行含义检查的优点，并避免在回溯事件中维护或遍历GRASP类型含义图。新颖的非时间回溯提供将阻塞变量设置为叶变量，并且仅改变叶变量的值，但可能改变回溯变量的值和身份。

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