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1. 发明授权

US6038385A Physical design automation system and process for designing integrated circuit chip using "chessboard" and "jiggle" optimization 失效
标题翻译：物理设计自动化系统和使用“棋盘”和“抖动”优化设计集成电路芯片的过程
公开(公告)号：US6038385A
公开(公告)日：2000-03-14
申请号：US609397
申请日：1996-03-01
申请人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev , Ivan Pavisic
发明人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev , Ivan Pavisic
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A cell placement for an integrated circuit chip is divided into two "chessboard" patterns or "jiggles". Each pattern resembles a chessboard in that it consists of alternating regions of different types or "colors" such that no region of a given color has an edge common with another region of the same color. The jiggles are offset relative to each other such that the regions of one jiggle partially overlap at least two regions of the other jiggle. A placement improvement operation such as simulated annealing is performed sequentially for each color of each jiggle. During each operation, a plurality of parallel processors operate on the regions simultaneously using a previous copy of the entire chip, with one processor being assigned to one or more regions. At the end of each operation, the copy of the chip is updated. The chessboard patterns eliminate unproductive cell moves resulting from adjacent regions having a common edge. The jiggles enable cells to move to their optimal positions from their initial region to any other region on the chip. The regions can have rectangular, triangular or hexagonal shapes.
摘要翻译：集成电路芯片的单元布局分为两个“棋盘”图案或“跳棋”。每个图案类似于棋盘，其由不同类型或“颜色”的交替区域组成，使得给定颜色的区域不具有与相同颜色的另一区域相同的边缘。跳块相对于彼此偏移，使得一个颤动的区域部分地与另一个摇摆的至少两个区域重叠。针对每个抖动的每个颜色顺序地执行诸如模拟退火的放置改善操作。在每个操作期间，多个并行处理器使用整个芯片的先前副本同时在该区域上操作，一个处理器被分配给一个或多个区域。在每个操作结束时，更新芯片的副本。棋盘图案消除由具有共同边缘的相邻区域产生的非生产性细胞移动。这些跳跃使得电池从它们的初始区域移动到其最佳位置到芯片上的任何其它区域。这些区域可以具有矩形，三角形或六边形形状。

2. 发明授权

US5971588A Advanced modular cell placement system with optimization of cell neighborhood system 失效
标题翻译：先进的模块化放置系统，优化了小区邻域系统
公开(公告)号：US5971588A
公开(公告)日：1999-10-26
申请号：US672423
申请日：1996-06-28
申请人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev
发明人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5072
摘要： A system for providing an optimal cluster of cells on the surface of a semiconductor chip is provided herein. The system collects a predetermined quantity of cells, this predetermined quantity containing a center cell, and all cells are assigned a distance value from the center cell. A coordinate is assigned to each cell based on its associated distance value, and new cell positions are calculated based on related cell positions and weights associated with each cell.
摘要翻译：本文提供了一种用于在半导体芯片的表面上提供最佳的单元簇的系统。系统收集预定量的单元，该预定量包含一个中心单元，并且从中心单元分配所有单元的距离值。基于其相关联的距离值将坐标分配给每个小区，并且基于与每个小区相关联的相关小区位置和权重来计算新的小区位置。

3. 发明授权

US5963455A Advanced modular cell placement system with functional sieve optimization technique 失效
标题翻译：先进的模块化电池放置系统，具有功能筛选优化技术
公开(公告)号：US5963455A
公开(公告)日：1999-10-05
申请号：US672936
申请日：1996-06-28
申请人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev
发明人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A system for optimizing placement of a cell on a surface of a semiconductor chip is disclosed herein. The cells may belong to nets and may belong to neighborhoods. The system initially calculates affinities based on repositioning the cell. The system then combines affinities and repositions cells based on these combined affinities. The system then computes a cost function and repeats the combining, repositioning, and computing functions a predetermined number of times.
摘要翻译：本文公开了一种用于优化半导体芯片的表面上的单元的布置的系统。这些小区可能属于网络，可能属于邻居。系统最初基于重新定位单元格计算亲和度。然后，该系统基于这些组合的亲和力结合亲和力和重新定位细胞。然后，系统计算成本函数并重复组合，重新定位和计算功能预定次数。

4. 发明授权

US5892688A Advanced modular cell placement system with iterative one dimensional preplacement optimization 失效
标题翻译：先进的模块化放置系统，具有迭代一维预置位优化
公开(公告)号：US5892688A
公开(公告)日：1999-04-06
申请号：US672335
申请日：1996-06-28
申请人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev
发明人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A system for providing an optimal preplacement of cells on a bounded surface of a semiconductor chip is disclosed herein. A percentage of the cells have predetermined interconnections with other cells. The system initially locates the cells on said surface, then computes coordinates for interconnected cells, determines a weight associated with each cell, and calculates a new cell coordinate for each cell based on the coordinates and weights from said determining step.
摘要翻译：本文公开了一种用于在半导体芯片的有界表面上提供单元的最佳预置位的系统。细胞的百分比具有与其他细胞的预定互连。系统首先将单元定位在所述表面上，然后计算互连单元的坐标，确定与每个单元相关联的重量，并且基于来自所述确定步骤的坐标和权重来计算每个单元的新单元坐标。

5. 发明授权

US5872718A Advanced modular cell placement system 失效
标题翻译：先进的模块化放置系统
公开(公告)号：US5872718A
公开(公告)日：1999-02-16
申请号：US672535
申请日：1996-06-28
申请人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev
发明人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A system for optimally locating cells on the surface of an integrated circuit chip is presented herein. The system comprises constructing a plurality of neighborhoods containing elements positionally related to one another; initially evaluating the lowest level of region hierarchy; iteratively developing a logical one-dimensional preplacement of elements on said surface; performing an affinity driven discrete preplacement optimization; evaluating whether a highest level of regional hierarchy has been attained; iteratively performing a dispersion driven spring system to levelize cell density and an unconstrained sinusoidal optimization; executing a density levelizing procedure; iteratively optimizing while controlling element densities; removing element overlap; iteratively optimizing for desired spacing between elements, adjusting element spacing, and permuting elements; locating elements on grid lines; and iteratively performing a functional sieve crystallization.
摘要翻译：本文提供了用于在集成电路芯片的表面上最佳地定位单元的系统。该系统包括构成包含彼此位置相关的元素的多个邻域; 初步评估区域层次的最低水平; 迭代地开发所述表面上的元件的逻辑一维预置位; 执行亲和力驱动的离散预置位优化; 评估是否实现了最高层次的区域层级; 迭代地执行色散驱动弹簧系统来平衡细胞密度和无约束正弦优化; 执行密度调整程序; 迭代优化，同时控制元件密度; 去除元件重叠; 迭代地优化元件之间的期望间隔，调整元件间距和排列元件; 在网格线上定位元素; 并迭代进行功能筛结晶。

6. 发明授权

US5812740A Advanced modular cell placement system with neighborhood system driven optimization 失效
标题翻译：具有邻域系统驱动优化的高级模块化放置系统
公开(公告)号：US5812740A
公开(公告)日：1998-09-22
申请号：US674605
申请日：1996-06-28
申请人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev
发明人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev
IPC分类号： G06F17/50 , G06F15/00
CPC分类号： G06F17/5072 , Y10S706/921
摘要： A system for computing an affinity for relocating a cell on a surface of a semiconductor chip is disclosed herein. The cell is located within a region and belongs to a net of cells. The system initially computes a weight associated with all cells in the net. The sytem then sums the weights of all cells in the net containing the cell for all cells located inside the region and at positions greater than and less than edges of the region and computes the affinity for moving the cell to points on the surface greater than, equal to, and less than the current position of the cell based on the weight sums from said summing function. The computing function further comprises combining the affinities determined based on weight sums with other affinities. The summing function further comprises computing a relationship between the amount of rows and columns of regions on the semiconductor chip surface, and the affinity computation function comprises combining the relationship with the weight sums.
摘要翻译：本文公开了一种用于计算在半导体芯片的表面上重新定位单元的亲和度的系统。细胞位于一个区域内，属于细胞网。系统最初计算与网中所有单元相关联的权重。系统然后将位于该区域内部以及大于和小于该区域边缘的位置的所有单元格的网格中包含单元格的所有单元格的权重相加，并计算将单元格移动到表面上的点的亲和力大于，基于来自所述求和函数的权重和，等于并小于小区的当前位置。计算功能还包括将基于权重和确定的亲和力与其他亲和度组合。求和功能还包括计算半导体芯片表面上的行数和列数之间的关系，并且亲和度计算功能包括将关系与权重和组合。

7. 发明授权

US5808899A Advanced modular cell placement system with cell placement crystallization 失效
标题翻译：先进的模块化电池放置系统，具有电池放置结晶
公开(公告)号：US5808899A
公开(公告)日：1998-09-15
申请号：US672235
申请日：1996-06-28
申请人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev
发明人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A system for optimizing placement of a plurality of cells located on a surface of a semiconductor chip divided into regions by grid lines is disclosed herein. The system first increases the size associated with each cell by a fixed amount. The system then performs various density equalization routines to all cells, and locates cells having a size greater than a predetermined quantity and fixes those cells. Finally, the system executes a plurality of optimal cell movement routines to crystallize cell placement.
摘要翻译：本文公开了一种用于优化位于通过网格线划分为区域的半导体芯片的表面上的多个单元的布置的系统。系统首先将与每个单元相关联的大小增加固定的量。然后，系统对所有单元执行各种密度均衡例程，并且定位具有大于预定量的大小的单元并且固定这些单元。最后，系统执行多个最优的单元移动程序以结晶单元放置。

8. 发明授权

US5742510A Simultaneous placement and routing (SPAR) method for integrated circuit physical design automation system 失效
标题翻译：用于集成电路物理设计自动化系统的同时放置和布线（SPAR）方法
公开(公告)号：US5742510A
公开(公告)日：1998-04-21
申请号：US604181
申请日：1996-02-21
申请人： Michael D. Rostoker , James S. Koford , Edwin R. Jones , Douglas B. Boyle , Ranko Scepanovic
发明人： Michael D. Rostoker , James S. Koford , Edwin R. Jones , Douglas B. Boyle , Ranko Scepanovic
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5072
摘要： In a physical design automation system for producing an optimized cell placement for an integrated circuit chip, a placement optimization methodology is decomposed into a plurality of cell placement optimization processes that are performed simultaneously by parallel processors on input data representing the chip. The results of the optimization processes are recomposed to produce an optimized cell placement. The fitness of the optimized cell placement is analyzed, and the parallel processors are controlled to selectively repeat performing the optimization processes for further optimizing the optimized cell placement if the fitness does not satisfy a predetermined criterion. The system can be applied to initial placement, routing, placement improvement and other problems. The processors can perform the same optimization process on different placements, or on areas of a single placement. Alternatively, the processors can perform different optimization processes simultaneously on a single initial placement, with the resulting processed placement having the highest fitness being selected as the optimized placement. The processors can further selectively reprocess areas of a placement having high cell interconnect congestion or other low fitness parameters.
摘要翻译：在用于生成用于集成电路芯片的优化的单元布置的物理设计自动化系统中，布局优化方法被分解成由并行处理器在表示芯片的输入数据上同时执行的多个单元布局优化处理。重组优化过程的结果以产生优化的细胞放置。分析优化的单元布局的适应性，并且如果适合度不满足预定标准，则并行处理器被控制以选择性地重复执行优化处理以进一步优化优化的单元布局。该系统可以应用于初始放置，布线，布局改进等问题。处理器可以对不同的展示位置或单个展示位置执行相同的优化过程。或者，处理器可以在单个初始放置上同时执行不同的优化过程，所得到的经处理的放置具有最佳适合度作为优化的位置。处理器可以进一步选择性地重新处理具有高单元互连拥塞或其他低适应度参数的位置的区域。

9. 发明授权

US5742086A Hexagonal DRAM array 失效
标题翻译：六角形DRAM阵列
公开(公告)号：US5742086A
公开(公告)日：1998-04-21
申请号：US517153
申请日：1995-08-21
申请人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
发明人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
IPC分类号： G06F17/50 , G11C5/02 , G11C5/06 , H01L23/522 , H01L23/528 , H01L27/02 , H01L27/092 , H01L27/108 , H01L27/11 , H01L27/118 , H01L29/06 , H03K19/0944 , H03K19/0948 , H01L29/78 , H01L29/41
CPC分类号： G06F17/5072 , G06F17/5077 , G11C5/025 , G11C5/063 , H01L23/5222 , H01L23/528 , H01L27/0207 , H01L27/0922 , H01L27/108 , H01L27/11 , H01L27/1104 , H01L27/11807 , H03K19/09441 , H03K19/0948 , H01L29/0657 , H01L2924/0002
摘要： Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a "tri-ister" is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.
摘要翻译：披露了几个发明。公开了一种使用六角形电池的电池结构。该体系结构不限于六角形细胞。单元可以由两个或更多个六边形的簇，通过三角形，平行四边形以及能够容纳各种单元格形状的其他多边形来定义。公开了多向非正交三层金属布线。该架构可以与三向路由组合以用于特别有利的设计。在三向布线布置中，集成电路的微电子单元的互连端的电导体优选地在三个方向上相互延伸60°。沿三个方向延伸的导体优选地以三个不同的层形成。公开了一种使半导体器件中的导线长度最小化的方法。公开了一种使半导体器件中的金属间电容最小化的方法。公开了一种称为“三元器件”的新型器件。公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。公开了三角形运算放大器和三极管。公开了三角形读出放大器。公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。公开了一种可编程可变驱动晶体管。公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。

10. 发明授权

US5568636A Method and system for improving a placement of cells using energetic placement with alternating contraction and expansion operations 失效
公开(公告)号：US5568636A
公开(公告)日：1996-10-22
申请号：US306385
申请日：1994-09-13
申请人： James S. Koford
发明人： James S. Koford
IPC分类号： G06F17/50 , G06F3/00 , G06F15/00
CPC分类号： G06F17/5072
摘要： A method of cell placement for an integrated circuit chip includes performing a contraction operation by which at least some of the cells are relocated to new positions that provide lower interconnect wirelength. For each cell, the centroid of the net of cells to which the cell is connected is computed. The cell is then moved toward the centroid by a distance that is equal to the distance from the current position of the cell to the centroid multiplied by a "chaos" factor. This process continues until a specific energy condition is met; then the `expansion` mode is entered. An expansion operation is then performed by which the net force exerted on each cell by other cells in the placement and a resulting altered velocity of the cell are calculated, and a new cell position is calculated based on the altered velocity over an incremental length of time. The system stays in expansion mode until another energy criterion is met. The contraction and expansion modes are repeated in alternation, with the expansion operation preventing the cells from being undesirably converged by the contraction operation. At the start of each expansion operation, a normalization operation is performed to prevent skewing of the cells along a particular axis.

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