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1. 发明授权

US06286128B1 Method for design optimization using logical and physical information 失效
标题翻译：使用逻辑和物理信息进行设计优化的方法
公开(公告)号：US06286128B1
公开(公告)日：2001-09-04
申请号：US09097299
申请日：1998-06-12
申请人： Lawrence Pileggi , Majid Sarrafzadeh , Sharad Malik , Abhijeet Chakraborty , Archie Li , Robert Eugene Shortt , Christopher Dunn , David Gluss , Dennis Yamamoto , Dinesh Gaitonde , Douglas B. Boyle , Emre Tuncer , Eric McCaughrin , Feroze Peshotan Taraporevala , Gary K. Yeap , James S. Koford , Joseph T. Rahmeh , Lilly Shieh , Salil R. Raje , Sam Jung Kim , Satamurthy Pullela , Yau-Tsun Steven Li , Tong Gao
发明人： Lawrence Pileggi , Majid Sarrafzadeh , Sharad Malik , Abhijeet Chakraborty , Archie Li , Robert Eugene Shortt , Christopher Dunn , David Gluss , Dennis Yamamoto , Dinesh Gaitonde , Douglas B. Boyle , Emre Tuncer , Eric McCaughrin , Feroze Peshotan Taraporevala , Gary K. Yeap , James S. Koford , Joseph T. Rahmeh , Lilly Shieh , Salil R. Raje , Sam Jung Kim , Satamurthy Pullela , Yau-Tsun Steven Li , Tong Gao
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F17/5068 , G06F2217/78
摘要： A method for design optimization using logical and physical information is provided. In one embodiment, a method for design optimization using logical and physical information, includes receiving a behavioral description of an integrated circuit or a portion of an integrated circuit, optimizing placement of circuit elements in accordance with a first cost function, and optimizing logic of the circuit elements in accordance with a second cost function, in which the optimizing placement of the circuit elements and the optimizing logic of the circuit elements are performed concurrently. The method can further include optimizing routing in accordance with a third cost function, in which the optimizing routing, the optimizing placement of the circuit elements, and the optimizing logic of the circuit elements are performed concurrently.
摘要翻译：提供了使用逻辑和物理信息进行设计优化的方法。在一个实施例中，使用逻辑和物理信息的设计优化的方法包括接收集成电路或集成电路的一部分的行为描述，根据第一成本函数优化电路元件的布局，以及优化逻辑根据第二成本函数的电路元件，其中同时执行电路元件的优化布置和电路元件的优化逻辑。该方法可以进一步包括根据第三成本函数优化路由，其中同时执行优化路由，电路元件的优化布局和电路元件的优化逻辑。

2. 发明授权

US07886256B1 Timing analysis of a mapped logic design using physical delays 有权
标题翻译：使用物理延迟的映射逻辑设计的时序分析
公开(公告)号：US07886256B1
公开(公告)日：2011-02-08
申请号：US12146507
申请日：2008-06-26
申请人： Pradip Kumar Jha , Dinesh D. Gaitonde , Yau-Tsun Steven Li
发明人： Pradip Kumar Jha , Dinesh D. Gaitonde , Yau-Tsun Steven Li
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5031 , G06F2217/84
摘要： Approaches for determining a static timing analysis of a logic design are disclosed. Physical delay arcs of a plurality of physical elements of an integrated circuit specify respective propagation delays from inputs of the physical elements to outputs of the physical elements. Logic components of the logic design are mapped to selected ones of the physical components of the physical elements. For each of the logic components, the logic delay arcs are determined from the physical delay arcs. Each logic delay arc for each logic component specifies a propagation delay from an input of the logic component to an output of the logic component. A static timing analysis of the logic components is performed using the logic delay arc, and data from the timing analysis is output.
摘要翻译：公开了用于确定逻辑设计的静态时序分析的方法。集成电路的多个物理元件的物理延迟弧指定从物理元件的输入到物理元件的输出的相应传播延迟。逻辑设计的逻辑组件被映射到物理元件的物理组件中的选定的一部分。对于每个逻辑组件，逻辑延迟弧由物理延迟弧确定。每个逻辑组件的每个逻辑延迟弧指定从逻辑组件的输入到逻辑组件的输出的传播延迟。使用逻辑延迟弧执行逻辑组件的静态时序分析，并输出来自定时分析的数据。

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