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1. 发明授权

US06286128B1 Method for design optimization using logical and physical information 失效
标题翻译：使用逻辑和物理信息进行设计优化的方法
公开(公告)号：US06286128B1
公开(公告)日：2001-09-04
申请号：US09097299
申请日：1998-06-12
申请人： Lawrence Pileggi , Majid Sarrafzadeh , Sharad Malik , Abhijeet Chakraborty , Archie Li , Robert Eugene Shortt , Christopher Dunn , David Gluss , Dennis Yamamoto , Dinesh Gaitonde , Douglas B. Boyle , Emre Tuncer , Eric McCaughrin , Feroze Peshotan Taraporevala , Gary K. Yeap , James S. Koford , Joseph T. Rahmeh , Lilly Shieh , Salil R. Raje , Sam Jung Kim , Satamurthy Pullela , Yau-Tsun Steven Li , Tong Gao
发明人： Lawrence Pileggi , Majid Sarrafzadeh , Sharad Malik , Abhijeet Chakraborty , Archie Li , Robert Eugene Shortt , Christopher Dunn , David Gluss , Dennis Yamamoto , Dinesh Gaitonde , Douglas B. Boyle , Emre Tuncer , Eric McCaughrin , Feroze Peshotan Taraporevala , Gary K. Yeap , James S. Koford , Joseph T. Rahmeh , Lilly Shieh , Salil R. Raje , Sam Jung Kim , Satamurthy Pullela , Yau-Tsun Steven Li , Tong Gao
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F17/5068 , G06F2217/78
摘要： A method for design optimization using logical and physical information is provided. In one embodiment, a method for design optimization using logical and physical information, includes receiving a behavioral description of an integrated circuit or a portion of an integrated circuit, optimizing placement of circuit elements in accordance with a first cost function, and optimizing logic of the circuit elements in accordance with a second cost function, in which the optimizing placement of the circuit elements and the optimizing logic of the circuit elements are performed concurrently. The method can further include optimizing routing in accordance with a third cost function, in which the optimizing routing, the optimizing placement of the circuit elements, and the optimizing logic of the circuit elements are performed concurrently.
摘要翻译：提供了使用逻辑和物理信息进行设计优化的方法。在一个实施例中，使用逻辑和物理信息的设计优化的方法包括接收集成电路或集成电路的一部分的行为描述，根据第一成本函数优化电路元件的布局，以及优化逻辑根据第二成本函数的电路元件，其中同时执行电路元件的优化布置和电路元件的优化逻辑。该方法可以进一步包括根据第三成本函数优化路由，其中同时执行优化路由，电路元件的优化布局和电路元件的优化逻辑。

2. 发明授权

US5825644A Method for encoding a state machine 失效
标题翻译：用于编码状态机的方法
公开(公告)号：US5825644A
公开(公告)日：1998-10-20
申请号：US610299
申请日：1996-03-04
申请人： Gary K. Yeap
发明人： Gary K. Yeap
IPC分类号： G06F7/00 , G06F17/50 , G06F3/00
CPC分类号： G06F7/00 , G06F17/5045
摘要： A method for encoding a state machine includes performing a state transition probability analysis (11) to identify hot states (12) and cold states. Then hot (13) and cold (14) states are encoded. The encoding minimizes the expected bit flip (EBF). In addition, a local encoding exploration may be performed to further optimize the encoding of the state machine for area and power consumption. The local encoding exploration preserves the EBF.
摘要翻译：一种用于编码状态机的方法包括执行状态转移概率分析（11）以识别热状态（12）和冷态。然后热（13）和冷（14）状态被编码。该编码使预期位翻转（EBF）最小化。此外，可以执行本地编码探索以进一步优化状态机的面积和功耗的编码。本地编码探索保留了EBF。

3. 发明授权

US08392870B2 Two-chip co-design and co-optimization in three-dimensional integrated circuit net assignment 有权
标题翻译：双芯片协同设计和协同优化三维集成电路网络分配
公开(公告)号：US08392870B2
公开(公告)日：2013-03-05
申请号：US13019280
申请日：2011-02-01
申请人： Yifan Zhang , Gary K. Yeap , Yonghua Liao , Dalei Wang
发明人： Yifan Zhang , Gary K. Yeap , Yonghua Liao , Dalei Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/86
摘要： A method of generating optimized input/output (IO) pair and inter-chip connection combinations for two chips is described. In this method, first and second designs for two chips can be specified. Then inter-chip signals based on the first and second designs can be specified. IO pairs for the first and second chips can be determined based on the inter-chip signals. At this point, electrical contacts between micro-bumps (MBs) of the first and second chips can be formed. Inter-chip paths with through-silicon-vias (TSVs) and MBs of the first and second chips can also be formed. At this point, the costs of assigning the IO pairs to the inter-chip paths can be determined. A cost matrix can be built based on these costs. A bipartite matching algorithm can be applied to the cost matrix to determine the optimized IO pair and inter-chip path combinations.
摘要翻译：描述了为两个芯片生成优化的输入/输出（IO）对和芯片间连接组合的方法。在该方法中，可以指定用于两个芯片的第一和第二设计。那么可以指定基于第一和第二设计的片间信号。可以基于芯片间信号来确定用于第一和第二芯片的IO对。此时，可以形成第一和第二芯片的微凸块（MB）之间的电接触。还可以形成具有第一和第二芯片的通硅通孔（TSV）和MB的芯片间路径。此时，可以确定将IO对分配给芯片间路径的成本。可以基于这些成本构建成本矩阵。二分法匹配算法可以应用于成本矩阵，以确定优化的IO对和芯片间路径组合。

4. 发明授权

US06442743B1 Placement method for integrated circuit design using topo-clustering 失效
标题翻译：使用拓扑聚类的集成电路设计的放置方法
公开(公告)号：US06442743B1
公开(公告)日：2002-08-27
申请号：US09097107
申请日：1998-06-12
申请人： Majid Sarrafzadeh , Lawrence Pileggi , Sharad Malik , Feroze Peshotan Taraporevala , Abhijeet Chakraborty , Gary K. Yeap , Salil R. Raje , Lilly Shieh , Douglas B. Boyle , Dennis Yamamoto
发明人： Majid Sarrafzadeh , Lawrence Pileggi , Sharad Malik , Feroze Peshotan Taraporevala , Abhijeet Chakraborty , Gary K. Yeap , Salil R. Raje , Lilly Shieh , Douglas B. Boyle , Dennis Yamamoto
IPC分类号： G06F1750
CPC分类号： G06F17/5072
摘要： The disclosure describes a placement method for the physical design of integrated circuits in which natural topological feature clusters are discovered and exploited during the placement process is disclosed. Topo-clusters drive initial placement, with all of the gates of a topo-cluster being placed initially in a single bin of the placement layout or within a group of positionally-related bins. An iterative placement refinement process is done using a technique referred to as Dual Geometrically-Bounded FM (GBFM). GBFM is applied on a local basis to windows encompassing a number of bins. From iteration to iteration, windows may shift position and vary in size. When a region bounded by a window meets a specified cost threshold in terms of a specified cost function, that region stops participating. Following the foregoing global placement process the circuit is then ready for detailed placement in which cells are assigned to placement rows.
摘要翻译：本公开描述了用于集成电路的物理设计的放置方法，其中公开了在放置过程期间发现和利用自然拓扑特征簇。拓扑群集驱动初始位置，其中所有的拓扑群集的门最初都放置在放置布局的一个bin或一组位置相关的区域中。使用称为双重几何限幅FM（GBFM）的技术完成迭代放置细化过程。 GBFM在本地基础上应用于包含多个分区的窗口。从迭代到迭代，窗口可能会改变位置并且大小变化。当由窗口界定的区域在指定的成本函数方面满足指定的成本阈值时，该区域停止参与。按照上述全局放置过程，电路准备好进行详细的放置，其中将单元格分配给放置行。

5. 发明申请

US20130036397A1 Standard Cell Placement Technique For Double Patterning Technology 有权
标题翻译：双图案技术的标准电池放置技术
公开(公告)号：US20130036397A1
公开(公告)日：2013-02-07
申请号：US13196640
申请日：2011-08-02
申请人： John Jung Lee , Gary K. Yeap , Renata Zaliznyak , Paul David Friedberg
发明人： John Jung Lee , Gary K. Yeap , Renata Zaliznyak , Paul David Friedberg
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method for generating legal colorable multiple patterning standard cell placement is provided. In this method, a standard cell library including color information can be accessed. For each standard cell, edge labels can be assigned based on colors of objects within a predetermined distance from each edge. A truth table, which indicates legal spacing between pairs of standard cells based on their edge labels, can be accessed. A plurality of standard cells of a design can then be placed based on the truth table.
摘要翻译：提供了一种用于产生合法可着色多重图案化标准单元放置的方法。在该方法中，可以访问包括颜色信息的标准单元库。对于每个标准单元，可以基于距每个边缘预定距离内的对象的颜色分配边缘标签。可以访问真实表，其中表示基于其边缘标签的标准单元对之间的合法间隔。然后可以基于真值表放置设计的多个标准单元。

6. 发明申请

US20120198409A1 Two-Chip Co-Design And Co-Optimization In Three-Dimensional Integrated Circuit Net Assignment 有权
标题翻译：三维集成电路网络分配中的双芯片协同设计与协同优化
公开(公告)号：US20120198409A1
公开(公告)日：2012-08-02
申请号：US13019280
申请日：2011-02-01
申请人： Yifan Zhang , Gary K. Yeap , Yonghua Liao , Dalei Wang
发明人： Yifan Zhang , Gary K. Yeap , Yonghua Liao , Dalei Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/86
摘要： A method of generating optimized input/output (IO) pair and inter-chip connection combinations for two chips is described. In this method, first and second designs for two chips can be specified. Then inter-chip signals based on the first and second designs can be specified. IO pairs for the first and second chips can be determined based on the inter-chip signals. At this point, electrical contacts between micro-bumps (MBs) of the first and second chips can be formed. Inter-chip paths with through-silicon-vias (TSVs) and MBs of the first and second chips can also be formed. At this point, the costs of assigning the IO pairs to the inter-chip paths can be determined. A cost matrix can be built based on these costs. A bipartite matching algorithm can be applied to the cost matrix to determine the optimized IO pair and inter-chip path combinations.
摘要翻译：描述了为两个芯片生成优化的输入/输出（IO）对和芯片间连接组合的方法。在该方法中，可以指定用于两个芯片的第一和第二设计。那么可以指定基于第一和第二设计的片间信号。可以基于芯片间信号来确定用于第一和第二芯片的IO对。此时，可以形成第一和第二芯片的微凸块（MB）之间的电接触。还可以形成具有第一和第二芯片的通硅通孔（TSV）和MB的芯片间路径。此时，可以确定将IO对分配给芯片间路径的成本。可以基于这些成本构建成本矩阵。二分法匹配算法可以应用于成本矩阵，以确定优化的IO对和芯片间路径组合。

7. 发明申请

US20090288045A1 Design-For-Test-Aware Hierarchical Design Planning 有权
标题翻译：设计为测试意识分层设计规划
公开(公告)号：US20090288045A1
公开(公告)日：2009-11-19
申请号：US12123209
申请日：2008-05-19
申请人： Hung-Chun Chien , Ben Mathew , Padmashree Takkars , Bang Liu , Chang-Wei Tai , Xiao-Ming Xiong , Gary K. Yeap
发明人： Hung-Chun Chien , Ben Mathew , Padmashree Takkars , Bang Liu , Chang-Wei Tai , Xiao-Ming Xiong , Gary K. Yeap
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/14
摘要： Full-chip scan data can be advantageously used during design planning to minimize top-level scan wires and scan feedthroughs. The scan cells can be reordered using a modified cost function to promote connecting all scan cells in one plan group before crossing to a scan cell in another plan group. The modified cost function can take into account penalty parameters. The penalty parameters can include at least one of: membership in a plan group or a top-level physical hierarchy, size of a plan group, FLOATING/ORDERED scan element in scan data, location of endpoints of an ORDERED list, location of endpoints of a macro, and membership in a plan group containing a STOP point. Scan data, at the block-level and at the top-level, can be automatically updated to reflect the plan groups and optimized scan chains.
摘要翻译：在设计规划期间可以有利地使用全片扫描数据，以最小化顶层扫描线和扫描馈通。扫描单元可以使用修改的成本函数重新排序，以促进连接一个计划组中的所有扫描单元，然后再与另一个计划组中的扫描单元交叉。修改的成本函数可以考虑惩罚参数。惩罚参数可以包括以下中的至少一个：计划组或顶层物理层次结构中的成员身份，计划组的大小，扫描数据中的FLOATING / ORDERED扫描元素，ORDERED列表的端点的位置，宏，以及包含STOP点的计划组中的成员资格。可以自动更新块级和顶级的扫描数据，以反映计划组和优化的扫描链。

8. 发明授权

US06961916B2 Placement method for integrated circuit design using topo-clustering 有权
公开(公告)号：US06961916B2
公开(公告)日：2005-11-01
申请号：US10136161
申请日：2002-05-01
申请人： Majid Sarrafzadeh , Lawrence Pileggi , Sharad Malik , Feroze Peshotan Taraporevala , Abhijeet Chakraborty , Gary K. Yeap , Salil R. Raje , Lilly Shieh , Douglas B. Boyle , Dennis Yamamoto
发明人： Majid Sarrafzadeh , Lawrence Pileggi , Sharad Malik , Feroze Peshotan Taraporevala , Abhijeet Chakraborty , Gary K. Yeap , Salil R. Raje , Lilly Shieh , Douglas B. Boyle , Dennis Yamamoto
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： The present invention, generally speaking, provides a placement method for the physical design of integrated circuits in which natural topological feature clusters (topo-clusters) are discovered and exploited during the placement process. Topo-clusters may be formed based on various criteria including, for example, functional similarity, proximity (in terms of number of nets), and genus. Genus refers to a representation of a netlist in terms of a number of planar netlists—netlists in which no crossing of nets occurs. Topo-clusters drive initial placement, with all of the gates of a topo-cluster being placed initially in a single bin of the placement layout or within a group of positionally-related bins. The portion of a topo-cluster placed within a given bin is called a quanto-cluster. An iterative placement refinement process then follows, using a technique referred to herein as Geometrically-Bounded FM (GBFM), and in particular Dual GBFM. In GBFM, FM is applied on a local basis to windows encompassing some number of bins. From iteration to iteration, windows may shift position and vary in size. When a region bounded by a window meets a specified cost threshold in terms of a specified cost function, that region does not participate. The cost function takes account of actual physical metrics—delay, area, congestion, power, etc. “Dual” refers to the fact that each iteration has two phases. During a first phase, FM is performed within a region on a quanto-cluster basis. During a second phase, FM is performed within the region on a gate basis. GBFM occurs in the context of recursive quadrisection. Hence, after GBFM has been completed, a further quadrisection step is performed in which each bin is divided into four bins, with a quarter of the gates of the original bin being placed in the center of each of the resulting bins. GBFM then follows, and the cycle repeats until each bin contains a fairly small number of gates. Following the foregoing global placement process, the circuit is then ready for detailed placement in which cells are assigned to placement rows.

9. 发明授权

US06192508B1 Method for logic optimization for improving timing and congestion during placement in integrated circuit design 失效
标题翻译：用于在集成电路设计中放置时改善时序和拥塞的逻辑优化方法
公开(公告)号：US06192508B1
公开(公告)日：2001-02-20
申请号：US09097076
申请日：1998-06-12
申请人： Sharad Malik , Lawrence Pileggi , Abhijeet Chakraborty , Gary K. Yeap , Douglas B. Boyle
发明人： Sharad Malik , Lawrence Pileggi , Abhijeet Chakraborty , Gary K. Yeap , Douglas B. Boyle
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F17/5072
摘要： This invention recognizes the ability of logic optimization to help placement relieve congestion. Different types of logic optimizations are used to help placement relieve congestion. In one type of optimization, the speed of parts of the circuit is improved by selecting faster cells. In another type of optimization, the topology of the circuit is changed such that placement can now move cells, which could not have been moved before, to reduce congestion and thus enable routing. A distinguishing feature of this methodology is that it not only uses the placement information for interconnection delay/area estimates during logic optimization, but also uses logic optimization to aid the physical placement steps by providing support to placement so that the congestion of the circuit is improved. The aim is to avoid getting into a situation where the placed circuit cannot be routed.
摘要翻译：本发明认识到逻辑优化能够帮助放置缓解拥塞。使用不同类型的逻辑优化来帮助放置缓解拥塞。在一种类型的优化中，通过选择更快的单元来提高电路部分的速度。在另一种类型的优化中，改变电路的拓扑结构，使得放置现在可以移动以前不能被移动的单元，以减少拥塞并由此实现路由。该方法的一个突出特点是，它不仅在逻辑优化期间使用放置信息进行互连延迟/面积估计，而且还通过为放置提供支持来使用逻辑优化来辅助物理放置步骤，从而改善电路的拥塞。目的是避免进入放置的电路不能路由的情况。

10. 发明授权

US08726215B2 Standard cell placement technique for double patterning technology 有权
标题翻译：双重图案化技术的标准电池放置技术
公开(公告)号：US08726215B2
公开(公告)日：2014-05-13
申请号：US13196640
申请日：2011-08-02
申请人： John Jung Lee , Gary K. Yeap , Renata Zaliznyak , Paul David Friedberg
发明人： John Jung Lee , Gary K. Yeap , Renata Zaliznyak , Paul David Friedberg
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method for generating legal colorable multiple patterning standard cell placement is provided. In this method, a standard cell library including color information can be accessed. For each standard cell, edge labels can be assigned based on colors of objects within a predetermined distance from each edge. A truth table, which indicates legal spacing between pairs of standard cells based on their edge labels, can be accessed. A plurality of standard cells of a design can then be placed based on the truth table.
摘要翻译：提供了一种用于产生合法可着色多重图案化标准单元放置的方法。在该方法中，可以访问包括颜色信息的标准单元库。对于每个标准单元，可以基于距每个边缘预定距离内的对象的颜色分配边缘标签。可以访问真实表，其中表示基于其边缘标签的标准单元对之间的合法间隔。然后可以基于真值表放置设计的多个标准单元。

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