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1. 发明授权

US06969683B2 Method of preventing resist poisoning in dual damascene structures 有权
标题翻译：防止双重镶嵌结构抗蚀剂中毒的方法
公开(公告)号：US06969683B2
公开(公告)日：2005-11-29
申请号：US10750348
申请日：2003-12-31
申请人： Rongxiang Hu , Yongbae Kim , Sang-Yun Lee , Hiroaki Takikawa , Shumay Dou , Sarah Neuman , Philippe Schoenborn , Keith Chao , Dilip Vijay , Kai Zhang , Masaichi Eda
发明人： Rongxiang Hu , Yongbae Kim , Sang-Yun Lee , Hiroaki Takikawa , Shumay Dou , Sarah Neuman , Philippe Schoenborn , Keith Chao , Dilip Vijay , Kai Zhang , Masaichi Eda
IPC分类号： H01L21/311 , H01L21/44 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/76831 , H01L21/31144 , H01L21/76807 , H01L21/76808 , H01L21/76826 , H01L21/76829
摘要： A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.
摘要翻译：提供了一种在电介质层中形成双镶嵌互连的方法。通常，在电介质中蚀刻第一孔。在电介质的一部分上形成中毒阻挡层，防止抗蚀剂中毒。在毒物屏障层上形成图案化掩模。第二孔被蚀刻到电介质层中，其中第一孔的至少一部分具有与第二孔的至少一部分相同的面积。

2. 发明授权

US06743725B1 High selectivity SiC etch in integrated circuit fabrication 有权
标题翻译：集成电路制造中的高选择性SiC蚀刻
公开(公告)号：US06743725B1
公开(公告)日：2004-06-01
申请号：US09928570
申请日：2001-08-13
申请人： Rongxiang Hu , Philippe Schoenborn , Masaichi Eda
发明人： Rongxiang Hu , Philippe Schoenborn , Masaichi Eda
IPC分类号： H01L21311
CPC分类号： C09K13/00 , C09K13/08 , H01L21/31116 , H01L21/76807
摘要： The subject matter described herein involves an improved etch process for use in fabricating integrated circuits on semiconductor wafers. The selectivity of the etch process for silicon carbide versus silicon oxide, organo silica-glass or other low dielectric constant type material is enhanced by adding hydrogen (H2) or ammonia (NH3) or other hydrogen-containing gas to the etch chemistry.
摘要翻译：本文描述的主题涉及用于制造半导体晶片上的集成电路的改进的蚀刻工艺。碳化硅与氧化硅，有机二氧化硅玻璃或其他低介电常数型材料的蚀刻工艺的选择性通过向蚀刻化学品中加入氢（H 2）或氨（NH 3）或其它含氢气体来增强。

3. 发明授权

US06713386B1 Method of preventing resist poisoning in dual damascene structures 有权
公开(公告)号：US06713386B1
公开(公告)日：2004-03-30
申请号：US10025304
申请日：2001-12-19
申请人： Rongxiang Hu , Yongbae Kim , Sang-Yun Lee , Hiroaki Takikawa , Shumay Dou , Sarah Neuman , Philippe Schoenborn , Keith Chao , Dilip Vijay , Kai Zhang , Masaichi Eda
发明人： Rongxiang Hu , Yongbae Kim , Sang-Yun Lee , Hiroaki Takikawa , Shumay Dou , Sarah Neuman , Philippe Schoenborn , Keith Chao , Dilip Vijay , Kai Zhang , Masaichi Eda
IPC分类号： H01L214763
CPC分类号： H01L21/76831 , H01L21/31144 , H01L21/76807 , H01L21/76808 , H01L21/76826 , H01L21/76829
摘要： A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.

4. 发明授权

US5877530A Formation of gradient doped profile region between channel region and heavily doped source/drain contact region of MOS device in integrated circuit structure using a re-entrant gate electrode and a higher dose drain implantation 失效
标题翻译：在集成电路结构中MOS器件的沟道区域和重掺杂源极/漏极接触区域之间的梯度掺杂分布区域的形成使用入口栅电极和较高剂量漏极注入
公开(公告)号：US5877530A
公开(公告)日：1999-03-02
申请号：US690592
申请日：1996-07-31
申请人： Sheldon Aronowitz , Laique Khan , Philippe Schoenborn
发明人： Sheldon Aronowitz , Laique Khan , Philippe Schoenborn
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/28114 , H01L29/42376 , H01L29/7833
摘要： A novel integrated circuit structure, and process for making same, is disclosed wherein a tapered or gradient doped profile region is provided in a semiconductor substrate between the heavily doped drain region and the channel region in the substrate comprising an MOS device. In the process of the invention, a re-entrant or tapered gate electrode, resembling an inverted trapezoid, is used as a mask during a first doping step at a dosage level higher than normally used to form a conventional LDD region. This doping step forms a doped region having a dopant gradient which gradually increases in dosage level with distance from the channel region. Conventional oxide spacers may then be formed on the sidewalls of the gate electrode followed by conventional high level doping to form the heavily doped source and drain region in the unmasked portions of the substrate between the oxide spacers and the field oxide isolation. Since the doped region beneath the oxide spacers includes a gradient doped profile region, with the lightest level of dopant adjacent the channel region (since more of the tapered gate electrode acted as a mask for the initial implantation), the overall dosage level used in the first implantation step to form the gradient doped profile region may be higher than the dosage level conventionally used to form a conventional LDD region. The resistance of the path between the heavily doped drain contact region and the channel region, which includes the gradient doped profile region, is therefore lower than the resistance of a conventional LDD region.
摘要翻译：公开了一种新颖的集成电路结构及其制造方法，其中在包括MOS器件的衬底中的重掺杂漏极区域和沟道区域之间的半导体衬底中提供锥形或梯度掺杂型态区域。在本发明的方法中，在第一掺杂步骤期间，以比通常用于形成常规LDD区域的剂量水平，使用类似倒梯形的入口或锥形栅极电极作为掩模。该掺杂步骤形成具有掺杂剂梯度的掺杂区域，其随着与沟道区域的距离而逐渐增加剂量水平。然后可以在栅电极的侧壁上形成常规的氧化物间隔物，接着是常规的高电平掺杂，以在氧化物间隔物和场氧化物隔离之间的衬底的未屏蔽部分中形成重掺杂的源极和漏极区。由于氧化物间隔物下面的掺杂区域包括梯度掺杂的轮廓区域，其中掺杂剂的最弱级别与沟道区域相邻（因为更多的锥形栅极电极用作初始注入的掩模），所以在形成梯度掺杂轮廓区域的第一注入步骤可以高于常规用于形成常规LDD区域的剂量水平。因此，重掺杂漏极接触区域和沟道区域（包括梯度掺杂分布区域）之间的路径电阻比常规LDD区域的电阻低。

5. 发明授权

US5413966A Shallow trench etch 失效
标题翻译：浅沟蚀刻
公开(公告)号：US5413966A
公开(公告)日：1995-05-09
申请号：US179751
申请日：1993-09-09
申请人： Philippe Schoenborn
发明人： Philippe Schoenborn
IPC分类号： H01L21/28 , H01L21/3105 , H01L21/3213 , H01L21/762 , H05K1/11 , H05K3/46 , H01L21/302
CPC分类号： H01L21/31053 , H01L21/28026 , H01L21/3105 , H01L21/32137 , H01L21/32139 , H01L21/7621 , H01L21/76227 , H01L21/76235 , H05K1/115 , H05K3/4644 , Y10S148/05
摘要： A trench mask is formed of two dissimilar layers of material deposited over a substrate. The lower of the two layers is an insulating layer such as silicon dioxide or silicon nitride, or combinations of both, and the upper of the two layers is doped or undoped polysilicon. Together, the two layers are patterned in a first etch step to form a trench mask for subsequent etching of trenches in the substrate. The upper layer is deposited to a thickness "t" related to the desired depth "d" of the trenches to be etched. In a second etch step, the trenches are formed in the substrate. In the case of substantially uniform etching of the polysilicon and the substrate, the thickness of the polysilicon is substantially equal to the desired trench depth. In the case of unequal etching of the polysilicon and the substrate, the thickness of the polysilicon is based on the etch rate disparity. In either case, trench etch endpoint detection is provided by clearing of the polysilicon and consequent exposure of the lower layer of the trench mask. In both cases, loading effects during the second etch step are alleviated, or completely eliminated, because both the upper layer and the substrate are silicon-based materials.
摘要翻译：沟槽掩模由沉积在衬底上的两种不同的材料层形成。两层中较低的一层是绝缘层，如二氧化硅或氮化硅，或两者的组合，两层的上层是掺杂或未掺杂的多晶硅。一起，在第一蚀刻步骤中图案化两层以形成用于随后蚀刻衬底中的沟槽的沟槽掩模。上层被沉积成与要蚀刻的沟槽的期望深度“d”相关的厚度“t”。在第二蚀刻步骤中，在衬底中形成沟槽。在多晶硅和基板的基本均匀蚀刻的情况下，多晶硅的厚度基本上等于所需的沟槽深度。在多晶硅和衬底的不均匀蚀刻的情况下，多晶硅的厚度基于蚀刻速率差异。在任一种情况下，通过清除多晶硅并随后暴露沟槽掩模的下层来提供沟槽蚀刻端点检测。在这两种情况下，由于上层和衬底都是基于硅的材料，所以在第二蚀刻步骤期间的负载效应被缓解或完全消除。

6. 发明授权

US06579777B1 Method of forming local oxidation with sloped silicon recess 失效
标题翻译：用倾斜硅凹槽形成局部氧化的方法
公开(公告)号：US06579777B1
公开(公告)日：2003-06-17
申请号：US08587417
申请日：1996-01-16
申请人： Ting P. Yen , Pamela S. Trammel , Philippe Schoenborn , Alexander H. Owens
发明人： Ting P. Yen , Pamela S. Trammel , Philippe Schoenborn , Alexander H. Owens
IPC分类号： H01L2176
CPC分类号： H01L21/7621
摘要： A method of forming a localized oxidation having reduced bird's beak encroachment in a semiconductor device by providing an opening in the silicon substrate that has sloped sidewalls with a taper between about 10° and about 75° as measured from the vertical axis of the recess opening and then growing field oxide within the tapered recess opening for forming the localized oxidation.
摘要翻译：一种通过在硅衬底中设置开口的方式形成局部氧化的方法，所述局部氧化具有缩小的鸟嘴刺入半导体器件中，所述开口具有从所述凹部开口的垂直轴线测量的具有约10°至约75°之间的锥度的倾斜侧壁，然后在锥形凹槽开口内生长场氧化物以形成局部氧化。

7. 发明授权

US5663083A Process for making improved MOS structure with hot carrier reduction 失效
标题翻译：具有热载流子减少的改进的MOS结构的方法
公开(公告)号：US5663083A
公开(公告)日：1997-09-02
申请号：US695569
申请日：1996-08-12
申请人： Sungki O , Philippe Schoenborn
发明人： Sungki O , Philippe Schoenborn
IPC分类号： H01L21/336 , H01L29/78 , H01L21/265
CPC分类号： H01L29/6659 , H01L29/6656 , H01L29/66636 , H01L29/7834 , Y10S438/965
摘要： An MOS structure is disclosed which is provided with a trench in the substrate adjacent the channel region of the substrate, i.e., adjacent the area of the substrate over which the gate oxide and gate electrode are formed. The region of the substrate beneath the trench is lightly doped to provide a deeper LDD region in the substrate between the channel and the drain region so that electrons traveling through the channel to the drain region follow a path deeper in the substrate and farther spaced from the gate oxide in the region of the substrate between the source region and the drain region where high fields are encountered by electrons traveling through the channel from the source region to the drain region.
摘要翻译：公开了一种MOS结构，其在与基板的沟道区相邻的基板中设置有沟槽，即邻近形成栅极氧化物和栅电极的基板的区域。在沟槽下面的衬底的区域被轻掺杂以在沟道和漏极区域之间的衬底中提供更深的LDD区域，使得通过沟道传导到漏极区的电子遵循衬底中更深的路径，并且与衬底的间隔更远在源极区域和漏极区域之间的衬底的区域中的栅极氧化物，其中通过从源极区域到漏极区域的沟道的电子遇到高场。

8. 发明授权

US5639519A Method for igniting low pressure inductively coupled plasma 失效
标题翻译：点火低压感应耦合等离子体的方法
公开(公告)号：US5639519A
公开(公告)日：1997-06-17
申请号：US560934
申请日：1995-11-20
申请人： Roger Patrick , Philippe Schoenborn , Mark Franklin , Frank Bose
发明人： Roger Patrick , Philippe Schoenborn , Mark Franklin , Frank Bose
IPC分类号： H05H1/46 , C23C16/50 , C23C16/507 , H01J37/32 , H01L21/205 , H01L21/302 , H01L21/3065 , H01L21/31 , H05H1/24
CPC分类号： H01J37/321 , C23C16/507 , H01J37/32009 , H01J37/32082
摘要： An apparatus for producing a plasma suitable for semiconductor processing at pressures in the low millitorr range. The apparatus includes a vacuum chamber with a dielectric window, a generally planar coil disposed adjacent the window outside the chamber and coupled to an appropriate power source, and a plasma initiator disposed within the chamber. Once the plasma is initiated, the planar coil sustains the plasma by inductive power coupling. In one embodiment the plasma initiator is a secondary electrode disposed within the chamber and coupled to a second RF power source. In an alternative embodiment both the secondary electrode and a target pedestal are coupled to the secondary RF power source through a power splitter. In an alternative embodiment, the plasma initiator is used to ionize a portion of the process gas and provide a plasma that may then inductively couple with the planar coil. Initial ionization of the process gas may be achieved by use of an ultraviolet light source, an ultraviolet laser, a high voltage power source such as a tesla coil, or an electrical arc forming device such as a spark plug.
摘要翻译：一种用于生产适用于低压力范围内的半导体加工的等离子体的装置。该设备包括具有电介质窗口的真空室，与室外的窗口相邻设置并且耦合到适当的电源的大致平面的线圈以及设置在室内的等离子体启动器。一旦等离子体启动，平面线圈通过感应功率耦合来维持等离子体。在一个实施例中，等离子体引发器是设置在室内并且耦合到第二RF电源的次级电极。在替代实施例中，辅助电极和目标基座都通过功率分配器耦合到次级RF电源。在替代实施例中，等离子体引发器用于电离一部分工艺气体并提供等离子体，其然后可以与平面线圈感应耦合。处理气体的初始电离可以通过使用紫外光源，紫外激光器，诸如特斯拉线圈的高压电源或诸如火花塞的电弧形成装置来实现。

9. 发明授权

US5578165A Coil configurations for improved uniformity in inductively coupled plasma systems 失效
标题翻译：线圈配置，用于提高电感耦合等离子体系统的均匀性
公开(公告)号：US5578165A
公开(公告)日：1996-11-26
申请号：US412088
申请日：1995-03-27
申请人： Roger Patrick , Frank Bose , Philippe Schoenborn , Harry Toda
发明人： Roger Patrick , Frank Bose , Philippe Schoenborn , Harry Toda
IPC分类号： H01J37/32 , H05H1/46 , H05H1/00
CPC分类号： H01J37/321 , H05H1/46
摘要： The present invention relates to a method for generating a low pressure plasma circulating in a planar direction within a process enclosure. The invention generates plasma having substantially uniform density characteristics across a planar axis. The invention achieves improved uniformity of the plasma density by delivering more radio frequency power toward the periphery of the circulating plasma than toward the center of the plasma. Increasing the periphery power to the circulating plasma compensates for increased plasma losses due to interaction with the side walls of the process containment enclosure.
摘要翻译：本发明涉及在工艺外壳内产生在平面方向上循环的低压等离子体的方法。本发明产生了跨平面轴线具有基本均匀密度特性的等离子体。本发明通过相对于等离子体的中心向循环等离子体的周边输送更多的射频功率来实现等离子体密度的均匀性提高。增加循环等离子体的周边功率可以补偿由于与过程容纳外壳的侧壁相互作用而导致的等离子体损耗增加。

10. 发明授权

US06503840B2 Process for forming metal-filled openings in low dielectric constant dielectric material while inhibiting via poisoning 有权
公开(公告)号：US06503840B2
公开(公告)日：2003-01-07
申请号：US09848758
申请日：2001-05-02
申请人： Wilbur G. Catabay , Wei-Jen Hsia , Hong-Qiang Lu , Yong-Bae Kim , Kiran Kumar , Kai Zhang , Richard Schinella , Philippe Schoenborn
发明人： Wilbur G. Catabay , Wei-Jen Hsia , Hong-Qiang Lu , Yong-Bae Kim , Kiran Kumar , Kai Zhang , Richard Schinella , Philippe Schoenborn
IPC分类号： H01L21302
CPC分类号： H01L21/31144 , H01L21/02063 , H01L21/31116 , H01L21/31138 , H01L21/31633 , H01L21/76802 , H01L21/76814 , H01L21/76826 , H01L21/76843
摘要： A composite layer of dielectric material is first formed over the integrated circuit structure, comprising a thin barrier layer of dielectric material, a layer of low k dielectric material over the barrier layer, and a thin capping layer of dielectric material over the layer of low k dielectric material. A photoresist mask, formed over the capping layer, is baked in the presence of UV light to cross-link the mask material. The composite layer is then etched through the resist mask using an etchant gas mixture including CO, but not oxygen. Newly exposed surfaces of low k dielectric material are then optionally densified to harden them. The resist mask is then removed using a plasma of a neutral or reducing gas. Exposed surfaces of low k dielectric material are then passivated by a low power oxygen plasma. Preferably, optional densification, mask removal, and passivation are all done in the same vacuum apparatus. The substrate is then solvent cleaned to remove etch residues and then annealed to degasify the low k dielectric material. The substrate is then RF cleaned and a thin layer of PVD titanium is then formed in the same chamber over the surfaces of the openings. CVD titanium nitride is then formed over the titanium in the same vacuum apparatus. The coated openings are then filled with aluminum, tungsten, or copper.

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