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1. 发明授权

US06969683B2 Method of preventing resist poisoning in dual damascene structures 有权
标题翻译：防止双重镶嵌结构抗蚀剂中毒的方法
公开(公告)号：US06969683B2
公开(公告)日：2005-11-29
申请号：US10750348
申请日：2003-12-31
申请人： Rongxiang Hu , Yongbae Kim , Sang-Yun Lee , Hiroaki Takikawa , Shumay Dou , Sarah Neuman , Philippe Schoenborn , Keith Chao , Dilip Vijay , Kai Zhang , Masaichi Eda
发明人： Rongxiang Hu , Yongbae Kim , Sang-Yun Lee , Hiroaki Takikawa , Shumay Dou , Sarah Neuman , Philippe Schoenborn , Keith Chao , Dilip Vijay , Kai Zhang , Masaichi Eda
IPC分类号： H01L21/311 , H01L21/44 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/76831 , H01L21/31144 , H01L21/76807 , H01L21/76808 , H01L21/76826 , H01L21/76829
摘要： A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.
摘要翻译：提供了一种在电介质层中形成双镶嵌互连的方法。通常，在电介质中蚀刻第一孔。在电介质的一部分上形成中毒阻挡层，防止抗蚀剂中毒。在毒物屏障层上形成图案化掩模。第二孔被蚀刻到电介质层中，其中第一孔的至少一部分具有与第二孔的至少一部分相同的面积。

2. 发明授权

US06503840B2 Process for forming metal-filled openings in low dielectric constant dielectric material while inhibiting via poisoning 有权
公开(公告)号：US06503840B2
公开(公告)日：2003-01-07
申请号：US09848758
申请日：2001-05-02
申请人： Wilbur G. Catabay , Wei-Jen Hsia , Hong-Qiang Lu , Yong-Bae Kim , Kiran Kumar , Kai Zhang , Richard Schinella , Philippe Schoenborn
发明人： Wilbur G. Catabay , Wei-Jen Hsia , Hong-Qiang Lu , Yong-Bae Kim , Kiran Kumar , Kai Zhang , Richard Schinella , Philippe Schoenborn
IPC分类号： H01L21302
CPC分类号： H01L21/31144 , H01L21/02063 , H01L21/31116 , H01L21/31138 , H01L21/31633 , H01L21/76802 , H01L21/76814 , H01L21/76826 , H01L21/76843
摘要： A composite layer of dielectric material is first formed over the integrated circuit structure, comprising a thin barrier layer of dielectric material, a layer of low k dielectric material over the barrier layer, and a thin capping layer of dielectric material over the layer of low k dielectric material. A photoresist mask, formed over the capping layer, is baked in the presence of UV light to cross-link the mask material. The composite layer is then etched through the resist mask using an etchant gas mixture including CO, but not oxygen. Newly exposed surfaces of low k dielectric material are then optionally densified to harden them. The resist mask is then removed using a plasma of a neutral or reducing gas. Exposed surfaces of low k dielectric material are then passivated by a low power oxygen plasma. Preferably, optional densification, mask removal, and passivation are all done in the same vacuum apparatus. The substrate is then solvent cleaned to remove etch residues and then annealed to degasify the low k dielectric material. The substrate is then RF cleaned and a thin layer of PVD titanium is then formed in the same chamber over the surfaces of the openings. CVD titanium nitride is then formed over the titanium in the same vacuum apparatus. The coated openings are then filled with aluminum, tungsten, or copper.

3. 发明授权

US06062163A Plasma initiating assembly 失效
标题翻译：等离子体起始组装
公开(公告)号：US06062163A
公开(公告)日：2000-05-16
申请号：US876082
申请日：1997-06-13
申请人： Roger Patrick , Philippe Schoenborn , Mark Franklin , Frank Bose
发明人： Roger Patrick , Philippe Schoenborn , Mark Franklin , Frank Bose
IPC分类号： H05H1/46 , C23C16/50 , C23C16/507 , H01J37/32 , H01L21/205 , H01L21/302 , H01L21/3065 , H01L21/31 , C23C16/00 , C23F1/02
CPC分类号： H01J37/321 , C23C16/507 , H01J37/32009 , H01J37/32082
摘要： An apparatus for producing a plasma suitable for semiconductor processing at pressures in the low millitorr range. The apparatus includes a vacuum chamber with a dielectric window, a generally planar coil disposed adjacent the window outside the chamber and coupled to an appropriate power source, and a plasma initiator disposed within the chamber. Once the plasma is initiated, the planar coil sustains the plasma by inductive power coupling. In one embodiment the plasma initiator is a secondary electrode disposed within the chamber and coupled to a second RF power source. In an alternative embodiment both the secondary electrode and a target pedestal are coupled to the secondary RF power source through a power splitter. In an alternative embodiment, the plasma initiator is used to ionize a portion of the process gas and provide a plasma that may then inductively couple with the planar coil. Initial ionization of the process gas may be achieved by use of an ultraviolet light source, an ultraviolet laser, a high voltage power source such as a tesla coil, or an electrical arc forming device such as a spark plug.
摘要翻译：一种用于生产适用于低压力范围内的半导体加工的等离子体的装置。该设备包括具有电介质窗口的真空室，与室外的窗口相邻设置并且耦合到适当的电源的大致平面的线圈以及设置在室内的等离子体启动器。一旦等离子体启动，平面线圈通过感应功率耦合来维持等离子体。在一个实施例中，等离子体引发器是设置在室内并且耦合到第二RF电源的次级电极。在替代实施例中，辅助电极和目标基座都通过功率分配器耦合到次级RF电源。在替代实施例中，等离子体引发器用于电离一部分工艺气体并提供等离子体，其然后可以与平面线圈感应耦合。处理气体的初始电离可以通过使用紫外光源，紫外激光器，诸如特斯拉线圈的高压电源或诸如火花塞的电弧形成装置来实现。

4. 发明授权

US5362356A Plasma etching process control 失效
标题翻译：等离子体蚀刻工艺控制
公开(公告)号：US5362356A
公开(公告)日：1994-11-08
申请号：US821727
申请日：1992-01-14
申请人： Philippe Schoenborn
发明人： Philippe Schoenborn
IPC分类号： H01L21/28 , H01L21/3213 , H01L21/00
CPC分类号： H01L21/28026 , H01L21/32137 , H01L21/32139
摘要： A passive, in-line method of monitoring film removal (or deposition) during plasma etching (or deposition) based on interference phenomena is disclosed. Plasma emission intensity is monitored at a selected wavelength, without additional illuminating apparatus, and variations in plasma emission intensity are correlated to remaining film thickness, etch rate and uniformity, and etch selectivity. The method is useful in conjunction with nitride island etch, polysilicon etch, oxide spacer etch, contact etch, etc. The method is also useful in determining a particular remaining film thickness (e.g., just prior to clearing) at which point the etch recipe can be changed from a high-rate, low selectivity etch to a low-rate, high-selectivity etch.
摘要翻译：公开了一种基于干扰现象在等离子体蚀刻（或沉积）期间监测膜去除（或沉积）的无源的在线方法。在选定的波长下监测等离子体发射强度，而无需额外的照明装置，等离子体发射强度的变化与剩余的膜厚度，蚀刻速率和均匀性以及蚀刻选择性相关。该方法与氮化物岛蚀刻，多晶硅蚀刻，氧化物间隔物蚀刻，接触蚀刻等相结合是有用的。该方法还可用于确定特定的剩余膜厚度（例如，在清除之前），在该点蚀刻配方可以从高速率，低选择性蚀刻改变为低速率，高选择性蚀刻。

5. 发明授权

US5290396A Trench planarization techniques 失效
公开(公告)号：US5290396A
公开(公告)日：1994-03-01
申请号：US711624
申请日：1991-06-06
申请人： Philippe Schoenborn , Nicholas F. Pasch
发明人： Philippe Schoenborn , Nicholas F. Pasch
IPC分类号： C03C15/00 , C03C25/68 , H01L21/304 , H01L21/3105 , H01L21/762 , H01L23/522 , H01L23/528 , H05K1/11 , H05K3/46 , H01L21/00
CPC分类号： H01L21/7621 , H01L21/3105 , H01L21/31053 , H01L21/76227 , H01L21/76235 , H01L23/5226 , H01L23/5283 , H01L2924/0002 , H05K1/115 , H05K3/4644 , Y10S438/959
摘要： Various techniques for quantifying polishing performance are disclosed, and provide insight on the progression from a planarization regime to a smoothing regime to a blanket polish back regime, as well as providing a single, definable parameter (Quality Characteristic) for optimizing polishing performance. With these analytical tools in hand, it is possible to create novel structures which absorb polish rate non-uniformities across a wafer, and it is also possible to define and employ a "quick" polish step to clear high spots which will be followed by a subsequent etch step for rapid removal of material.

6. 发明申请

US20070136023A1 Method of using automated test equipment to screen for leakage inducing defects after calibration to intrinsic leakage 失效
标题翻译：使用自动化测试设备对校准后的渗漏引起的缺陷进行本征泄漏的方法
公开(公告)号：US20070136023A1
公开(公告)日：2007-06-14
申请号：US11300789
申请日：2005-12-14
申请人： Philippe Schoenborn , Ramit Bhandari , Tony Lo , Anh-Ha Tran
发明人： Philippe Schoenborn , Ramit Bhandari , Tony Lo , Anh-Ha Tran
IPC分类号： G01R31/02
CPC分类号： G01R31/3008
摘要： The present invention is directed to a method of identifying test devices having excessive leakage current and also includes computer program products that enable the same. The method obtaining background test data using a test routine to measure the leakage current for a set of test devices as a function of a parameter associated with device speed for the device under test. From the test data, a leakage threshold function is defined that correlates leakage current with the parameter associated with device speed. The test routine and the leakage threshold function are then input into an automated testing apparatus configured to execute the test on production or other devices. Devices are tested to determine leakage current over a range of parameter values associated with device speed. The devices are then screened using the leakage threshold function to determine the status of the device.
摘要翻译：本发明涉及一种识别具有过度泄漏电流的测试装置的方法，并且还包括能够实现该测试装置的计算机程序产品。该方法使用测试程序获得背景测试数据，以测量一组测试设备的泄漏电流，作为与被测设备的设备速度相关联的参数的函数。根据测试数据，定义泄漏阈值函数，将漏电流与与设备速度相关的参数相关联。然后将测试例程和泄漏阈值功能输入到被配置为在生产或其他设备上执行测试的自动测试设备。对器件进行测试，以确定与器件速度相关的参数值范围内的漏电流。然后使用泄漏阈值功能来屏蔽设备以确定设备的状态。

7. 发明授权

US06846569B2 Carbon-doped hard mask and method of passivating structures during semiconductor device fabrication 有权
标题翻译：碳掺杂硬掩模和半导体器件制造期间钝化结构的方法
公开(公告)号：US06846569B2
公开(公告)日：2005-01-25
申请号：US10405666
申请日：2003-04-02
申请人： John Hu , Ana Ley , Philippe Schoenborn
发明人： John Hu , Ana Ley , Philippe Schoenborn
IPC分类号： C23F4/00 , H01L21/3213 , B32B15/00
CPC分类号： H01L21/32139 , C23F4/00 , Y10T428/24322
摘要： A carbon-doped hard mask includes a dielectric material containing carbon which is released from the hard mask during a metal etching process. The released carbon is deposited on and bonds to sidewalls of the metal structure during the metal etching process to passivate the sidewalls of the metal structure and prevent lateral etching of the sidewalls during the metal etching process. The released carbon also prevents accumulation of metal residue in open fields.
摘要翻译：碳掺杂的硬掩模包括在金属蚀刻工艺期间从硬掩模释放的含有碳的电介质材料。在金属蚀刻过程期间，释放的碳沉积在金属结构的侧壁上并结合到金属结构的侧壁上，以钝化金属结构的侧壁并防止在金属蚀刻过程中侧壁的横向蚀刻。释放的碳还防止金属残留物在开放场中的积累。

8. 发明授权

US06743725B1 High selectivity SiC etch in integrated circuit fabrication 有权
标题翻译：集成电路制造中的高选择性SiC蚀刻
公开(公告)号：US06743725B1
公开(公告)日：2004-06-01
申请号：US09928570
申请日：2001-08-13
申请人： Rongxiang Hu , Philippe Schoenborn , Masaichi Eda
发明人： Rongxiang Hu , Philippe Schoenborn , Masaichi Eda
IPC分类号： H01L21311
CPC分类号： C09K13/00 , C09K13/08 , H01L21/31116 , H01L21/76807
摘要： The subject matter described herein involves an improved etch process for use in fabricating integrated circuits on semiconductor wafers. The selectivity of the etch process for silicon carbide versus silicon oxide, organo silica-glass or other low dielectric constant type material is enhanced by adding hydrogen (H2) or ammonia (NH3) or other hydrogen-containing gas to the etch chemistry.
摘要翻译：本文描述的主题涉及用于制造半导体晶片上的集成电路的改进的蚀刻工艺。碳化硅与氧化硅，有机二氧化硅玻璃或其他低介电常数型材料的蚀刻工艺的选择性通过向蚀刻化学品中加入氢（H 2）或氨（NH 3）或其它含氢气体来增强。

9. 发明授权

US06713386B1 Method of preventing resist poisoning in dual damascene structures 有权
公开(公告)号：US06713386B1
公开(公告)日：2004-03-30
申请号：US10025304
申请日：2001-12-19
申请人： Rongxiang Hu , Yongbae Kim , Sang-Yun Lee , Hiroaki Takikawa , Shumay Dou , Sarah Neuman , Philippe Schoenborn , Keith Chao , Dilip Vijay , Kai Zhang , Masaichi Eda
发明人： Rongxiang Hu , Yongbae Kim , Sang-Yun Lee , Hiroaki Takikawa , Shumay Dou , Sarah Neuman , Philippe Schoenborn , Keith Chao , Dilip Vijay , Kai Zhang , Masaichi Eda
IPC分类号： H01L214763
CPC分类号： H01L21/76831 , H01L21/31144 , H01L21/76807 , H01L21/76808 , H01L21/76826 , H01L21/76829
摘要： A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.

10. 发明授权

US06576404B2 Carbon-doped hard mask and method of passivating structures during semiconductor device fabrication 有权
标题翻译：碳掺杂硬掩模和半导体器件制造期间钝化结构的方法
公开(公告)号：US06576404B2
公开(公告)日：2003-06-10
申请号：US09741568
申请日：2000-12-19
申请人： John Hu , Ana Ley , Philippe Schoenborn
发明人： John Hu , Ana Ley , Philippe Schoenborn
IPC分类号： G03C500
CPC分类号： H01L21/32139 , C23F4/00 , Y10T428/24322
摘要： A carbon-doped hard mask includes a dielectric material containing carbon which is released from the hard mask during a metal etching process. The released carbon is deposited on and bonds to sidewalls of the metal structure during the metal etching process to passivate the sidewalls of the metal structure and prevent lateral etching of the sidewalls during the metal etching process. The released carbon also prevents accumulation of metal residue in open fields.
摘要翻译：碳掺杂的硬掩模包括在金属蚀刻工艺期间从硬掩模释放的含有碳的电介质材料。在金属蚀刻过程期间，释放的碳沉积在金属结构的侧壁上并结合到金属结构的侧壁上，以钝化金属结构的侧壁并防止在金属蚀刻过程中侧壁的横向蚀刻。释放的碳还防止金属残留物在开放场中的积累。

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