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1. 发明授权

US07115343B2 Pliant SRAF for improved performance and manufacturability 失效
标题翻译： Pliant SRAF，以提高性能和可制造性
公开(公告)号：US07115343B2
公开(公告)日：2006-10-03
申请号：US10708535
申请日：2004-03-10
申请人： Ronald L. Gordon , Ioana C. Graur , Lars W. Liebmann
发明人： Ronald L. Gordon , Ioana C. Graur , Lars W. Liebmann
IPC分类号： G03F9/00 , G06F17/50
CPC分类号： G03F1/36
摘要： A method for increasing coverage of subresolution assist features (SRAFs) in a layout. A set of possible SRAF placement and sizing rules for a given pitch is provided, ranked according to some figure of merit. During SRAF placement, the fit of a plurality of different SRAF solutions is successively evaluated to find the SRAF solution, or combinations thereof, which most improves lithographic performance while avoiding manufacturability problems. In general, the method comprises: obtaining a plurality of SRAF configurations for the layout; ranking the SRAF configurations based on a figure of merit; applying a highest ranked SRAF configuration to the layout; applying a predetermined number of lower ranked SRAF configurations to the layout; and selecting SRAF features from at least one of the applied SRAF configurations to provide the optimal SRAF configuration for the layout.
摘要翻译：一种用于增加布局中的分解辅助特征（SRAF）的覆盖的方法。提供了一组可能的SRAF放置和给定音调的大小调整规则，根据某些品质因素进行排名。在SRAF放置期间，连续地评估多个不同的SRAF解决方案的拟合，以找到最大程度上提高光刻性能同时避免可制造性问题的SRAF解决方案或其组合。通常，该方法包括：获得用于布局的多个SRAF配置; 基于品质因素对SRAF配置进行排名; 将最高排名的SRAF配置应用于布局; 将预定数量的较低排名的SRAF配置应用于所述布局; 以及从应用的SRAF配置中的至少一个选择SRAF特征以提供布局的最佳SRAF配置。

2. 发明申请

US20090037866A1 ALTERNATING PHASE SHIFT MASK OPTIMIZATION FOR IMPROVED PROCESS WINDOW 审中-公开
标题翻译：改进过程窗口的相位移位掩码优化
公开(公告)号：US20090037866A1
公开(公告)日：2009-02-05
申请号：US11833462
申请日：2007-08-03
申请人： Ioana C. Graur , Donald J. Samuels , Zachary Baum , Lars W. Liebmann
发明人： Ioana C. Graur , Donald J. Samuels , Zachary Baum , Lars W. Liebmann
IPC分类号： G06F17/50
CPC分类号： G03F1/30
摘要： A method for designing alternating phase shift masks is provided, in which narrow phase shapes located between densely spaced design shapes are colored to allow a maximum amount of light transmission. After assigning and ensuring binary legalization of the phase shapes, the narrow phase shapes are assigned a color, such as 0° phase shift, that allows the more light transmission than the alternate or opposite color (e.g. 180° phase shift), which helps avoid printing errors such as resist scumming between closely spaced shapes, and maximizes the lithographic process window.
摘要翻译：提供了一种用于设计交替相移掩模的方法，其中位于密集间隔设计形状之间的窄相形状被着色以允许最大量的光透射。在分配并确保相位形状的二进制合法化之后，窄相位形状被赋予诸如0°相移的颜色，其允许比交替或相反颜色（例如180°相移）更多的光透射，这有助于避免打印错误，例如紧密间隔形状之间的抗污垢浮渣，并使光刻工艺窗口最大化。

3. 发明授权

US06996797B1 Method for verification of resolution enhancement techniques and optical proximity correction in lithography 失效
标题翻译：用于光刻中分辨率增强技术和光学邻近校正的验证方法
公开(公告)号：US06996797B1
公开(公告)日：2006-02-07
申请号：US10904600
申请日：2004-11-18
申请人： Lars W. Liebmann , James A. Culp , Ioana C. Graur , Maharaj Mukherjee
发明人： Lars W. Liebmann , James A. Culp , Ioana C. Graur , Maharaj Mukherjee
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36 , G06F2217/12 , Y02P90/265
摘要： A method for model-based verification of resolution enhancement techniques (RET) and optical proximity correction (OPC) in lithography includes scaling shapes of a drawn mask layout to their corresponding intended wafer dimensions so as to create a scaled image. A first feature of the scaled image is shifted with respect to a second feature thereof in accordance with a predetermined maximum overlay error. An intersection parameter of the first and said second features of the scaled image is calculated so as to determine a yield metric of an ideal layout. A first feature of a simulated wafer image is shifted with respect to a second feature thereof in accordance with the predetermined maximum overlay error. An intersection parameter of the first and said second features of the simulated wafer image is calculated so as to determine a yield metric of a simulated layout, and the yield metric of the simulated wafer image is compared to the yield metric of the scaled image.
摘要翻译：用于光刻中的分辨率增强技术（RET）和光学邻近校正（OPC）的基于模型的验证的方法包括将绘制的掩模布局的形状缩放到其相应的预期晶片尺寸，以便创建缩放图像。根据预定的最大重叠误差，缩放图像的第一特征相对于其第二特征偏移。计算缩放图像的第一和第二特征的交点参数，以便确定理想布局的屈服度量。模拟晶片图像的第一特征相对于其第二特征根据预定的最大重叠误差而偏移。计算模拟晶片图像的第一和第二特征的交叉参数，以便确定模拟布局的屈服度量，并将模拟晶片图像的屈服度量与缩放图像的屈服度量进行比较。

4. 发明授权

US5923566A Phase shifted design verification routine 失效
标题翻译：相移设计验证程序
公开(公告)号：US5923566A
公开(公告)日：1999-07-13
申请号：US823576
申请日：1997-03-25
申请人： Gerald Galan , Ioana C. Graur , Lars W. Liebmann
发明人： Gerald Galan , Ioana C. Graur , Lars W. Liebmann
IPC分类号： G03F1/00 , G03F7/20 , G06F17/00 , G06F17/50
CPC分类号： G03F7/70441 , G03F7/705
摘要： A computer-implemented routine that verifies that an existing chip design can be converted to a PSM or reports localized design conflicts based solely on a knowledge of the specific design constraints applied in the targeted PSM design system and without a prior knowledge of specific layout configurations that will cause PSM design errors.
摘要翻译：一种计算机实现的程序，用于验证现有芯片设计可以转换为PSM，或仅基于在目标PSM设计系统中应用的特定设计约束的知识来报告本地化设计冲突，并且没有具体布局配置的先前知识会导致PSM设计错误。

5. 发明授权

US6057063A Phase shifted mask design system, phase shifted mask and VLSI circuit devices manufactured therewith 失效
标题翻译：相移掩模设计系统，相移掩模和用其制造的VLSI电路器件
公开(公告)号：US6057063A
公开(公告)日：2000-05-02
申请号：US824700
申请日：1997-04-14
申请人： Lars W. Liebmann , Ioana C. Graur , Young O. Kim , Mark A. Lavin , Alfred K. Wong
发明人： Lars W. Liebmann , Ioana C. Graur , Young O. Kim , Mark A. Lavin , Alfred K. Wong
IPC分类号： G03F1/00 , G06F17/50 , G03F9/00
CPC分类号： G06F17/5068 , G03F1/26
摘要： A process for creating and verifying a design of phase-shifted masks utilizing at least one phase shift region employing a computer-aided design system. A chip design is provided. A phase-shift mask design capable of producing the chip design is created. Features in a design of the phase-shifted mask that require phase shifting are located. Uncolored phase regions are created on opposite sides of the features. Proper phase termination of the phase regions is ensured based upon space constraints of a phase-shifted mask technique utilized. Phases are determined for the phase regions. Whether coloring errors and un-phase-shiftable design features exist is determined. Mask process specific overlaps and expansions are applied to the mask design to prepare designed data levels for mask manufacture. A residual phase edge image removal design is derived.
摘要翻译：利用采用计算机辅助设计系统的至少一个相移区域来创建和验证相移掩模的设计的过程。提供芯片设计。产生了能够产生芯片设计的相移掩模设计。定位需要相移的相移掩模设计中的特征。未着色的相位区域在特征的相对侧上创建。基于所采用的相移掩模技术的空间限制，确保相位区域的正确相位终止。确定相位区域的相位。是否存在着色误差和不相移设计特征。掩模过程特定的重叠和扩展被应用于掩模设计以准备用于掩模制造的设计的数据级。导出残留相边缘图像去除设计。

6. 发明授权

US06964032B2 Pitch-based subresolution assist feature design 失效
标题翻译：基于间距的分解辅助功能设计
公开(公告)号：US06964032B2
公开(公告)日：2005-11-08
申请号：US10378579
申请日：2003-02-28
申请人： Lars W. Liebmann , Allen H. Gabor , Ronald L. Gordon , Carlos A. Fonseca , Martin Burkhardt
发明人： Lars W. Liebmann , Allen H. Gabor , Ronald L. Gordon , Carlos A. Fonseca , Martin Burkhardt
IPC分类号： G03F1/00 , G06F17/50 , H01L21/027
CPC分类号： G03F7/70441 , G03F1/36 , G03F7/70125 , G06F17/5068 , G06F2217/12
摘要： A method of designing a mask for imaging an integrated circuit (IC) design layout is provided to efficiently configure subresolution assist features (SRAFs) corresponding to an optimally configured annular illumination source of a lithographic projection system. A critical pitch is identified for the IC design, and optimal inner and outer radial coordinates of an annular illumination source are determined so that the resulting image projected through the mask will be optimized for the full range of pitches in the design layout. A relationship is provided for determining an optimal inner radius and outer radius for the annular illumination source. The number and placement of SRAFs are added to the mask design so that the resulting range of pitches substantially correspond to the critical pitch. The method of configuring SRAFs so that the image will have optimal characteristics, such as good contrast and good depth of focus, is fast.
摘要翻译：提供了一种设计用于对集成电路（IC）设计布局进行成像的掩模的方法，以有效地配置对应于光刻投影系统的最佳配置的环形照明源的分解辅助特征（SRAF）。确定IC设计的关键音调，并且确定环形照明光源的最佳内外径向坐标，以便通过掩模投射的所得图像将针对设计布局中的全部音高进行优化。提供了用于确定环形照明源的最佳内半径和外半径的关系。将SRAF的数量和位置添加到掩模设计中，使得所得到的间距范围基本上对应于临界间距。配置SRAF的方法是使图像具有最佳特征，如良好的对比度和良好的聚焦深度。

7. 发明授权

US08516403B2 Multiple patterning layout decomposition for ease of conflict removal 有权
标题翻译：多重图案化布局分解，便于冲突删除
公开(公告)号：US08516403B2
公开(公告)日：2013-08-20
申请号：US13223844
申请日：2011-09-01
申请人： Rani S. Abou Ghaida , Kanak B. Agarwal , Lars W. Liebmann , Sani R. Nassif
发明人： Rani S. Abou Ghaida , Kanak B. Agarwal , Lars W. Liebmann , Sani R. Nassif
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A mechanism is provided for multiple patterning lithography with conflict removal aware coloring. The mechanism makes multiple patterning coloring aware of the conflict removal overhead. The coloring solution explicitly considers ease of conflict removal as one of the coloring objectives. The mechanism pre-computes how much shapes can move in each direction. The mechanism generates a conflict graph where nodes represent shapes in the layout and edges represent conflicts between shapes. The mechanism assigns weights to edges based on available spatial slack between conflicting features. The mechanism then uses the weights to guide multiple patterning coloring. The mechanism prioritizes conflicting features with higher weights to be assigned different colors.
摘要翻译：提供了一种用于具有冲突消除意识着色的多重图案化光刻的机构。该机制使得多个图案化着色意识到冲突移除开销。着色解决方案明确地将冲突移除的容易性作为着色目标之一。该机制预先计算出每个方向上可以移动多少形状。该机制生成一个冲突图，其中节点表示布局中的形状，边缘表示形状之间的冲突。该机制基于冲突特征之间的可用空间松弛来为边缘分配权重。该机构然后使用重量来引导多个图案化着色。该机制优先处理具有较高权重的冲突特征，以分配不同的颜色。

8. 发明授权

US08473885B2 Physical design system and method 失效
公开(公告)号：US08473885B2
公开(公告)日：2013-06-25
申请号：US13413759
申请日：2012-03-07
申请人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woeltgens
发明人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woeltgens
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5009 , G06F17/5072
摘要： A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

9. 发明授权

US08225255B2 Placement and optimization of process dummy cells 有权
标题翻译：过程虚拟细胞的放置和优化
公开(公告)号：US08225255B2
公开(公告)日：2012-07-17
申请号：US12124472
申请日：2008-05-21
申请人： Xu Ouyang , Geng Han , Lars W. Liebmann
发明人： Xu Ouyang , Geng Han , Lars W. Liebmann
IPC分类号： G06F17/50
CPC分类号： G11C29/24 , G06F2217/12 , G11C5/02 , H01L27/0203 , H01L27/105 , Y02P90/265
摘要： A method for laying out process dummy cells in relationship to inside memory cells of a memory array includes (a) calculating an initial process performance parameter for the memory array; (b) changing dummy cell layout configuration for a layer electrically connected to inside cells; (c) applying lithographic simulation and yield model for both the inside memory cells and the changed layout configuration process dummy cells; and (d) repeating steps (b) and (c) until yield is maximized. Checks may be performed to ensure that there is enough room to make the change and that there is no significant adverse effect to neighboring circuits. The process performance parameter may be yield or a process window for the inside memory cells.
摘要翻译：与存储器阵列的内部存储单元相关地布置处理虚设单元的方法包括：（a）计算存储器阵列的初始处理性能参数; （b）改变电连接到内部单元的层的虚拟单元布局配置; （c）为内部存储单元和改变的布局配置处理虚拟单元应用光刻模拟和屈服模型; 和（d）重复步骤（b）和（c），直到产率最大化。可以进行检查，以确保有足够的空间进行更改，并且对相邻电路没有明显的不利影响。过程性能参数可以是产量或内部存储器单元的处理窗口。

10. 发明授权

US08103983B2 Electrically-driven optical proximity correction to compensate for non-optical effects 有权
标题翻译：电动光学接近校正补偿非光学效果
公开(公告)号：US08103983B2
公开(公告)日：2012-01-24
申请号：US12269477
申请日：2008-11-12
申请人： Kanak B. Agarwal , Shayak Banerjee , Praveen Elakkumanan , Lars W. Liebmann
发明人： Kanak B. Agarwal , Shayak Banerjee , Praveen Elakkumanan , Lars W. Liebmann
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36 , G06F2217/10
摘要： A contour of a mask design for an integrated circuit is modified to compensate for systematic variations arising from non-optical effects such as stress, well proximity, rapid thermal anneal, or spacer thickness. Electrical characteristics of a simulated integrated circuit chip fabricated using the mask design are extracted and compared to design specifications, and one or more edges of the contour are adjusted to reduce the systematic variation until the electrical characteristic is within specification. The particular electrical characteristic preferably depends on which layer is to be fabricated from the mask: on-current for a polysilicon; resistance for contact; resistance and capacitance for metal; current for active; and resistance for vias. For systematic threshold voltage variation, the contour is adjusted to match a gate length which corresponds to an on-current value according to pre-calculated curves for contour current and gate length at a nominal threshold voltage of the chip.
摘要翻译：改进了用于集成电路的掩模设计的轮廓，以补偿由非光学效应（例如应力，阱接近度，快速热退火或间隔物厚度）引起的系统变化。提取使用掩模设计制造的模拟集成电路芯片的电气特性，并将其与设计规范进行比较，并调整轮廓的一个或多个边缘以减少系统变化，直到电气特性在规格范围内。特定的电特性优选地取决于由掩模制成的层：多晶硅的导通电流; 接触阻力; 金属电阻和电容; 当前活跃; 和通孔阻力。对于系统阈值电压变化，调整轮廓以根据芯片的标称阈值电压下的轮廓电流和栅极长度的预先计算的曲线来匹配对应于导通电流值的栅极长度。

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