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1. 发明授权

US07503020B2 IC layout optimization to improve yield 失效
标题翻译： IC布局优化提高产量
公开(公告)号：US07503020B2
公开(公告)日：2009-03-10
申请号：US11424922
申请日：2006-06-19
申请人： Robert J. Allen , Faye D. Baker , Albert M. Chu , Michael S. Gray , Jason Hibbeler , Daniel N. Maynard , Mervyn Y. Tan , Robert F. Walker
发明人： Robert J. Allen , Faye D. Baker , Albert M. Chu , Michael S. Gray , Jason Hibbeler , Daniel N. Maynard , Mervyn Y. Tan , Robert F. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method of and service for optimizing an integrated circuit design to improve manufacturing yield. The invention uses manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The invention further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.
摘要翻译：一种用于优化集成电路设计以提高制造产量的方法和服务。本发明使用制造数据和算法来识别故障概率高的区域，即关键区域。本发明进一步改变电路设计的布局以减少临界面积，从而降低在制造过程中发生故障的可能性。确定关键区域的方法包括通用运行，几何映射和Voronoi图。优化包括但不限于形状尺寸的增量移动和调整，直到达到优化目标并减小关键面积。

2. 发明申请

US20070294648A1 IC Layout Optimization To Improve Yield 失效
标题翻译： IC布局优化提高产量
公开(公告)号：US20070294648A1
公开(公告)日：2007-12-20
申请号：US11424922
申请日：2006-06-19
申请人： Robert J. Allen , Faye D. Baker , Albert M. Chu , Michael S. Gray , Jason Hibbeler , Daniel N. Maynard , Mervyn Y. Tan , Robert F. Walker
发明人： Robert J. Allen , Faye D. Baker , Albert M. Chu , Michael S. Gray , Jason Hibbeler , Daniel N. Maynard , Mervyn Y. Tan , Robert F. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method of and service for optimizing an integrated circuit design to improve manufacturing yield. The invention uses manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The invention further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.
摘要翻译：一种用于优化集成电路设计以提高制造产量的方法和服务。本发明使用制造数据和算法来识别故障概率高的区域，即关键区域。本发明进一步改变电路设计的布局以减少临界面积，从而降低在制造过程中发生故障的可能性。确定关键区域的方法包括通用运行，几何映射和Voronoi图。优化包括但不限于形状尺寸的增量移动和调整，直到达到优化目标并减小关键面积。

3. 发明申请

US20090100386A1 IC Layout Optimization to Improve Yield 有权
标题翻译： IC布局优化提高产量
公开(公告)号：US20090100386A1
公开(公告)日：2009-04-16
申请号：US12342353
申请日：2008-12-23
申请人： Robert J. Allen , Faye D. Baker , Albert M. Chu , Michael S. Gray , Jason Hibbeler , Daniel N. Maynard , Mervyn Y. Tan , Robert F. Walker
发明人： Robert J. Allen , Faye D. Baker , Albert M. Chu , Michael S. Gray , Jason Hibbeler , Daniel N. Maynard , Mervyn Y. Tan , Robert F. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Optimizing an integrated circuit design to improve manufacturing yield using manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The process further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.
摘要翻译：使用制造数据和算法优化集成电路设计以提高制造产量，以识别故障概率高的区域，即关键区域。该过程进一步改变电路设计的布局以减少临界面积，从而降低制造过程中发生故障的可能性。确定关键区域的方法包括通用运行，几何映射和Voronoi图。优化包括但不限于形状尺寸的增量移动和调整，直到达到优化目标并减小关键面积。

4. 发明授权

US08862417B2 Systems and methods for determining adjustable wafer acceptance criteria based on chip characteristics 有权
标题翻译：基于芯片特性确定可调晶片接收标准的系统和方法
公开(公告)号：US08862417B2
公开(公告)日：2014-10-14
申请号：US13151337
申请日：2011-06-02
申请人： Albert M. Chu , Eric D. Johnson , William J. Rensch , Manikandan Viswanath
发明人： Albert M. Chu , Eric D. Johnson , William J. Rensch , Manikandan Viswanath
IPC分类号： G01N37/00 , G06F17/50 , H01L21/66
CPC分类号： H01L22/20 , H01L22/12 , H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： Systems and methods for determining adjustable wafer acceptance criteria based on chip characteristics. The method includes measuring a density of at least one chip. The method further includes computing a difference in density between the density of the at least one chip and a density of at least one kerf structure. The method further includes calculating an offset value to modify a Wafer Acceptance Criteria (WAC) to match the density difference between the at least one chip and the at least one kerf structure. The method further includes applying the offset value to the WAC for a wafer level measurement in order to increase chip yield performance.
摘要翻译：基于芯片特性确定可调晶片接收标准的系统和方法。该方法包括测量至少一个芯片的密度。该方法还包括计算至少一个芯片的密度与至少一个切口结构的密度之间的密度差。该方法还包括计算偏移值以修改晶片验收标准（WAC）以匹配至少一个芯片和至少一个切口结构之间的密度差。该方法还包括将偏移值应用于晶片级测量的WAC以提高芯片产量性能。

5. 发明授权

US08519772B2 Alternate power gating enablement 失效
标题翻译：备用电源门控启用
公开(公告)号：US08519772B2
公开(公告)日：2013-08-27
申请号：US13075652
申请日：2011-03-30
申请人： Albert M. Chu , Daryl M. Seitzer , Rohit Shetty , Douglas W. Stout
发明人： Albert M. Chu , Daryl M. Seitzer , Rohit Shetty , Douglas W. Stout
IPC分类号： H03K17/687
CPC分类号： H03K19/0016
摘要： Structures and methods for implementing alternating power gating in integrated circuits. A semiconductor structure includes a power gated circuit including a group of power gate switches and an alternating enable generator that generates enabling signals. Each respective one of the power gate switches is enabled by a respective one of the enabling signals. The alternating generator generates the enabling signals such that a first enabled power gate switch is alternated amongst the group of power gate switches.
摘要翻译：在集成电路中实现交流电源门控的结构和方法。半导体结构包括电源门控电路，其包括一组电源门开关和产生使能信号的交替使能发生器。每个相应的一个功率门开关由使能信号中的相应一个使能。交替发电机产生使能信号，使得第一使能电源门极开关在一组电源门开关之间交替。

6. 发明授权

US07646573B2 Method for improved triggering and oscillation suppression of ESD clamping devices 失效
标题翻译：改善ESD钳位装置触发和振荡抑制的方法
公开(公告)号：US07646573B2
公开(公告)日：2010-01-12
申请号：US12133424
申请日：2008-06-05
申请人： Albert M. Chu , Robert J. Gauthier, Jr. , Junjun Li , Thomas W. Wyckoff
发明人： Albert M. Chu , Robert J. Gauthier, Jr. , Junjun Li , Thomas W. Wyckoff
IPC分类号： H02H9/00 , H02H1/00
CPC分类号： H01L27/0266
摘要： An apparatus for protecting an integrated circuit from electrostatic discharge (ESD) includes an RC trigger device configured between a pair of power rails, a first control path coupled to the RC trigger device, and a second control path coupled to the RC trigger device. A power clamp is configured between the power rails for discharging current from an ESD event, the power clamp having an input coupled to outputs of the first and second control paths, the power clamp independently controllable by the first and second control paths. The first and second control paths are further configured to prevent the power clamp from reactivating following an initial deactivation of the power clamp.
摘要翻译：用于保护集成电路免受静电放电（ESD）的装置包括RC触发装置，其配置在耦合到RC触发装置的一对电源轨，第一控制路径和耦合到RC触发装置的第二控制路径之间。功率钳被配置在用于从ESD事件放电的电源轨之间，功率钳具有耦合到第一和第二控制路径的输出的输入，功率钳由第一和第二控制路径独立地控制。第一和第二控制路径还被配置为防止在电源钳的初始去激活之后电源钳位被重新激活。

7. 发明申请

US20090240875A1 CONTENT ADDRESSABLE MEMORY WITH HIDDEN TABLE UPDATE, DESIGN STRUCTURE AND METHOD 审中-公开
标题翻译：内容可寻址存储器，具有隐藏表更新，设计结构和方法
公开(公告)号：US20090240875A1
公开(公告)日：2009-09-24
申请号：US12050340
申请日：2008-03-18
申请人： Albert M. Chu , Paul C. Parries , Daryl M. Seitzer
发明人： Albert M. Chu , Paul C. Parries , Daryl M. Seitzer
IPC分类号： G11C15/04 , G11C7/00
CPC分类号： G11C15/043 , G11C11/406
摘要： Disclosed are embodiments of memory circuit having two discrete memory devices with two discrete memory arrays that store essentially identical data banks. The first device is a conventional memory adapted to perform all maintenance operations that require read functions (i.e., all update and refresh operations). The second device is a DRAM-based CAM device adapted to perform parallel search and overwrite operations only. Performance of overwrite operations by the second device occurs in conjunction with performance of maintenance operations by the first device so that corresponding memory cells in the two devices store essentially identical data values. Since the data banks in the memory devices are essentially identical and since maintenance and parallel search operations are not performed by the same device, the parallel search operations can be performed without interruption. Also disclosed are embodiments of an associated design structure and method.
摘要翻译：公开了具有两个分立存储器件的存储器电路的实施例，其具有存储基本上相同的数据库的两个分立存储器阵列。第一设备是适于执行需要读取功能（即，所有更新和刷新操作）的所有维护操作的常规存储器。第二设备是仅适用于执行并行搜索和重写操作的基于DRAM的CAM设备。第二设备的覆盖操作的性能与第一设备的维护操作的性能一起发生，使得两个设备中的相应存储器单元存储基本上相同的数据值。由于存储器件中的数据库基本上相同，并且由于维护和并行搜索操作不由同一设备执行，所以可以不中断地执行并行搜索操作。还公开了相关设计结构和方法的实施例。

8. 发明申请

US20090021289A1 Voltage Detection Circuit in an Integrated Circuit and Method of Generating a Trigger Flag Signal 有权
标题翻译：集成电路中的电压检测电路和产生触发标志信号的方法
公开(公告)号：US20090021289A1
公开(公告)日：2009-01-22
申请号：US12242114
申请日：2008-09-30
申请人： Wagdi W. Abadeer , Jeffrey S. Brown , Albert M. Chu , John A. Fifield
发明人： Wagdi W. Abadeer , Jeffrey S. Brown , Albert M. Chu , John A. Fifield
IPC分类号： H03L7/00
CPC分类号： H03K5/153
摘要： An integrated circuit that includes at least one tunneling device voltage detection circuit for generating a trigger flag signal. The tunneling device voltage detection circuit includes first and second voltage dividers receiving a supply voltage and having corresponding respective first and second internal node output voltages. The first and second voltage dividers are configured so the first output voltage is linear relative to the supply voltage and so that the second output voltage is nonlinear relative to the supply voltage. As the supply voltage ramps up, the profiles of the first and second output voltage cross at a particular voltage. An operational amplifier circuit senses when the first and second output voltages become equal and, in response thereto, outputs a trigger signal that indicates that the supply voltage has reached a certain level.
摘要翻译：一种集成电路，其包括用于产生触发标志信号的至少一个隧道装置电压检测电路。隧道装置电压检测电路包括接收电源电压并具有对应的相应的第一和第二内部节点输出电压的第一和第二分压器。第一和第二分压器被配置为使得第一输出电压相对于电源电压是线性的，并且使得第二输出电压相对于电源电压是非线性的。随着电源电压上升，第一和第二输出电压的曲线在特定电压下交叉。运算放大器电路检测第一和第二输出电压何时相等，并且响应于此，输出指示电源电压达到一定水平的触发信号。

9. 发明授权

US06285229B1 Digital delay line with low insertion delay 失效
标题翻译：具有低插入延迟的数字延迟线
公开(公告)号：US06285229B1
公开(公告)日：2001-09-04
申请号：US09471898
申请日：1999-12-23
申请人： Albert M. Chu , Frank D. Ferraiolo , John A. Fifield , Teresa Thi Nguyen , Michael Sofranko
发明人： Albert M. Chu , Frank D. Ferraiolo , John A. Fifield , Teresa Thi Nguyen , Michael Sofranko
IPC分类号： H03H1126
CPC分类号： H03K5/131 , H03K5/133 , H03K2005/00058
摘要： A variable digital delay line with an insertion delay as low as a single delay element yet capable of providing a large programmable delay with a small simple control mechanism. A loop connects an input to an output through selectable first delay elements such as 2:1 muxes and selectable second delay elements such as pairs of inverters by way of a plurality of intermediate nodes having a tap. A plurality of sneak paths are available wherein the loop by passes a remainder of first delay elements and/or second delay elements by way of the taps at the intermediate nodes.
摘要翻译：一种可变数字延迟线，其插入延迟低至单个延迟元件，但能够利用小的简单控制机制提供大的可编程延迟。环路通过可选择的第一延迟元件（例如2：1多路复用器）和可选择的第二延迟元件（例如成对的反相器）通过具有抽头的多个中间节点将输入连接到输出。多个潜行路径是可用的，其中循环通过中间节点处的抽头通过第一延迟元件的剩余部分和/或第二延迟元件。

10. 发明授权

US06229364B1 Frequency range trimming for a delay line 有权
标题翻译：延迟线的频率范围修整
公开(公告)号：US06229364B1
公开(公告)日：2001-05-08
申请号：US09274633
申请日：1999-03-23
申请人： Jean-Marc Dortu , Albert M. Chu , Christopher P. Miller
发明人： Jean-Marc Dortu , Albert M. Chu , Christopher P. Miller
IPC分类号： H03K513
CPC分类号： H03L7/0814 , H03K5/131
摘要： A delay line, in accordance with the invention, includes a plurality of delay elements connecting an input and an output, the delay elements for causing a delay to be introduced to a signal passing through the delay elements. A voltage device is included for regulating power to the plurality of delay elements, the voltage device being adjustable to provide at least one predetermined voltage to the delay elements such that the delay in the delay elements is modified according to the predetermined voltage(s). The delay line may be employed in a delay locked loop, a clock circuit or other circuits.
摘要翻译：根据本发明的延迟线包括连接输入和输出的多个延迟元件，延迟元件用于引入延迟以引入通过延迟元件的信号。包括用于调节对多个延迟元件的电力的电压装置，所述电压装置是可调节的，以向延迟元件提供至少一个预定电压，使得延迟元件中的延迟根据预定电压被修改。延迟线可以用在延迟锁定环路，时钟电路或其他电路中。

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